EN5365QI 6A Voltage Mode Synchronous Buck PWM DC-DC Converter with Integrated Inductor 3-Pin VID Output Voltage Select RoHS Compliant Halogen Free Description Features This Enpirion solution is a Power System on a Chip (PowerSoC). It is specifically designed to meet the precise voltage and fast transient requirements of present and future highperformance, low-power processor, DSP, FPGA, ASIC, memory boards and system level applications in a distributed power architecture. Advanced circuit techniques, ultra high switching frequency, and very advanced, high-density, integrated circuit and proprietary inductor technology deliver high-quality, ultra compact, non-isolated DC-DC conversion. Operating this converter requires as few as three external components that include small value input and output ceramic capacitors and a soft-start capacitor. • • • • • • • • • • The Enpirion integrated inductor solution significantly helps in low noise system design and productivity by offering greatly simplified board design, layout and manufacturing requirements. • All Enpirion products are RoHS compliant and lead-free manufacturing environment compatible. Typical Application Circuit VIN 47µF 1Ω PVIN VS0 AVIN VS1 VS2 VID Output Voltage Select ENABLE PGND VSENSE SS VOUT AGND PGND 15nF VOUT 47µF Figure 1. Simple Layout. • • • • Integrated INDUCTOR, MOSFETS, Controller Footprint 1/3rd that of competing solutions. Low Part Count: only 3 MLCC Capacitors. Up to 20W continuous output power. Low output impedance optimized for ≤ 90 nm Master/slave configuration for paralleling. 5MHz operating frequency. High efficiency, up to 93%. Wide input voltage range of 2.375V to 5.5V. 3-pin VID output voltage select to choose one of 7 pre-programmed Output Voltages. Output enable pin and Power OK signal. Programmable soft-start time. Optimized for low noise/EMI design. Thermal shutdown, short circuit, over-voltage and under-voltage protection. RoHS compliant, MSL level 3, 260C reflow. Applications • • • • • • • Point of load regulation for low-power processors, network processors, DSPs, FPGAs, and ASICs ≤ 90 nm advanced process loads Notebook computers, servers, workstations Broadband, networking, LAN/WAN, optical Low voltage, distributed power architectures with 2.5V, 3.3V or 5V rails DSL, STB, DVR, DTV, Industrial PC Ripple sensitive applications Ordering Information Part Number EN5365QI EN5365QI-E Temp Rating Package (°C) -40 to +85 58-pin QFN T&R QFN Evaluation Board *Optimized PCB Layout file downloadable from the Enpirion Website to assure first pass design success. 03816 9/18/2009 Rev:B EN5365QI Pin Configuration Below is a top view diagram of the EN5365Q package. NOTE: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. Figure 2. Pin Diagram, top view. ©Enpirion 2009 all rights reserved, E&OE 03816 2 9/18/2009 www.enpirion.com Rev:B EN5365QI Pin Descriptions PIN NAME 1-3 NC 4-5 NC(SW) 6-13 NC 14-20 VOUT 21-22 NC(SW) 23 NC 24-29 PGND 30-35 PVIN 36-37 NC 38 ROCP 39 AVIN 40 AGND 41-42 NC 43 44 45 VS2 VS1 VS0 46 POK 47 VSENSE 48 SS 49 50 51 EAIN EAOUT COMP FUNCTION NO CONNECT: These pins should not be electrically connected to each other or to any external signal, voltage, or ground. One or more of these pins may be connected internally. NO CONNECT – These pins are internally connected to the common drain output of the internal MOSFETs. NC(SW) pins are not to be electrically connected to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. NO CONNECT: These pins should not be electrically connected to each other or to any external signal, voltage, or ground. One or more of these pins may be connected internally. Regulated converter output. Decouple with output filter capacitor to PGND. Refer to layout section for specific layout requirements NO CONNECT – These pins are internally connected to the common drain output of the internal MOSFETs. NC(SW) pins are not to be electrically connected to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. NO CONNECT: These pins should not be electrically connected to each other or to any external signal, voltage, or ground. One or more of these pins may be connected internally. Output power ground. Refer to layout section for specific layout requirements. Input power supply. Connect to input power supply. Decouple with input capacitor to PGND. Refer to layout section for specific layout requirements NO CONNECT: These pins should not be electrically connected to each other or to any external signal, voltage, or ground. One or more of these pins may be connected internally. Optional Over Current Protection adjust pin. Used for diagnostic purposes only. Place 10kΩ resistor between this pin and AGND (pin 40) to raise the over current trip point to approximately 200% of maximum rated current. Analog voltage input for the controller circuits. Connect this pin to PVIN using a 1 Ohm resistor. Analog ground for the controller circuits. NO CONNECT: These pins should not be electrically connected to each other or to any external signal, voltage, or ground. One or more of these pins may be connected internally. Voltage select line 2 input. See Table 1. This pin has internal pull-up Voltage select line 1 input. See Table 1. This pin has internal pull-up Voltage select line 0 input. See Table 1. This pin has internal pull-up Power OK is an open drain transistor for power system state indication. POK is a logic high when VOUT is with -10% to +20% of VOUT nominal. Size pull-up resistor to limit current to 4mA when POK is low. Output Voltage Sense. Connect to output voltage immediately downstream from the output filter capacitors. Soft-Start node. The soft-start capacitor is connected between this pin and AGND. The value of this capacitor determines the startup timing. Optional Error Amplifier input. Allows for customization of the control loop. Optional Error Amplifier output. Allows for customization of the control loop. Optional Error Amplifier Buffer output. Allows for customization of the control loop. ©Enpirion 2009 all rights reserved, E&OE 03816 3 9/18/2009 www.enpirion.com Rev:B EN5365QI PIN NAME 52 ENABLE 53 PWM 54 NC 55 M/S 56-58 NC FUNCTION Input Enable. Applying a logic high, enables the output and initiates a soft-start. Applying a logic low disables the output. PWM input/output. Used for optional master/slave configuration. When M/S pin is asserted “low”, PWM will output the gate-drive PWM waveform. When the M/S pin is asserted “high”, the PWM pin is configured as an input for PWM signal from the “master” device. PWM pin can drive up to 3 slave devices. NOTE: Leave this pin open when not using parallel mode. NO CONNECT: These pins should not be electrically connected to each other or to any external signal, voltage, or ground. One or more of these pins may be connected internally. Optional Master/Slave select pin. Asserting pin “low” places device in Master Mode for current sharing. PWM pin (53) will output PWM drive signal. Asserting pin “high” will place the device in Slave Mode. PWM pin (53) will be configured to input (receive) PWM drive signal from “Master” device. NOTE: Leave this pin open when not using parallel mode. NO CONNECT: These pins should not be electrically connected to each other or to any external signal, voltage, or ground. One or more of these pins may be connected internally. ©Enpirion 2009 all rights reserved, E&OE 03816 4 9/18/2009 www.enpirion.com Rev:B EN5365QI Block Diagram POK PVIN UVLO Power Good Logic Thermal Limit Over Voltage VOUT Current Limit ROCP P-Drive VOUT (-) N-Drive PWM Comp (+) PGND Compensation Sawtooth Generator VSENSE Voltage Selector (-) Error Amp ENABLE SS VS0 VS1 VS2 (+) Reference Voltage selector Soft Start Bandgap Reference EAOUT EAIN COMP AVIN AGND Figure 3. System block diagram. Absolute Maximum Ratings CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond recommended operating conditions is not implied. Stress beyond absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. PARAMETER Input Supply Voltage Voltages on: ENABLE, VSENSE, VS2-VS0, M/S (Note 1) Voltages on: EAIN, EAOUT, COMP Voltages on: SS, PWM Voltages on: POK Storage Temperature Range Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A ESD Rating (based on Human Body Model) SYMBOL MIN MAX UNITS VIN -0.5 -0.5 -0.5 -0.5 -0.5 -65 7.0 VIN 2.5 3.0 VIN + 0.3 150 260 2000 V V V V V °C °C V TSTG NOTES: ©Enpirion 2009 all rights reserved, E&OE 03816 5 9/18/2009 www.enpirion.com Rev:B EN5365QI 1. VS0, VS1 and VS2 pins have an internal pull-up resistor, only ground potentials should be placed on them as required. Recommended Operating Conditions PARAMETER Input Voltage Range Output Voltage Range Operating Ambient Temperature Operating Junction Temperature SYMBOL MIN MAX UNITS VIN VOUT TA TJ 2.375 0.75 -40 -40 5.5 3.3 +85 +125 V V °C °C SYMBOL TYP UNITS θJA θJC TJ-TP 20 1.5 +150 20 °C/W °C/W °C °C Thermal Characteristics PARAMETER Thermal Resistance: Junction to Ambient (0 LFM) (Note 2) Thermal Resistance: Junction to Case (0 LFM) Thermal Overload Trip Point Thermal Overload Trip Point Hysteresis NOTES: 2. Based on a four-layer board and proper thermal design in line with JEDEC EIJ/JESD 51 Standards. ©Enpirion 2009 all rights reserved, E&OE 03816 6 9/18/2009 www.enpirion.com Rev:B EN5365QI Electrical Characteristics NOTE: VIN=5.5V over operating temperature range unless otherwise noted. Typical values are at TA = 25°C. PARAMETER SYMBOL Input Voltage Output Regulation VIN Initial Accuracy Variation due to all causes VOUT VOUT TEST CONDITIONS 2.375V ≤ VIN ≤ 5.5V, ILOAD = 1A; TA = 25°C VID Output Voltage Setting (V): 1.2, 1.25, 1.5, 1.8, 2.5, 3.3 0.8 2.375V ≤ VIN ≤ 5.5V, 0A ≤ ILOAD ≤ 6A -40°C ≤ TA ≤ +85°C VID Output Voltage Setting (V): 1.2, 1.25, 1.5, 1.8, 2.5, 3.3 0.8 Transient Response (IOUT = 0% to 100% or 100% to 0% of Rated Load) VIN = 5V, 1.2V < VOUT < 3.3V, Peak Deviation ∆VOUT COUT = 50µF Under Voltage Lockout Under Voltage Lock VIN Increasing VUVLO out threshold VIN Decreasing Switching Frequency Switching FSWITCH Frequency Load Characteristics Maximum IOUT Continuous Output (Note 3) Current Current Limit IOCP_TH Threshold Supply Current Shut-Down Supply ENABLE=0V IS Current MIN TYP MAX UNITS 2.375 5.5 V -2.0 -3.0 +2.0 +3.0 -3.0 -4.0 +3.0 +4.0 % % 3 % 2.2 2.1 V 5 MHz 6 A 9 A 50 µA Enable Operation Disable Threshold VDISABLE Enable Threshold Enable Pin Current VENABLE IEN Max voltage to ensure the converter is disabled 2.375V ≤ VIN ≤ 5.5V VIN = 5.5V ©Enpirion 2009 all rights reserved, E&OE 03816 7 9/18/2009 0.8 1.8 50 V V µA www.enpirion.com Rev:B EN5365QI PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 0.8 V VIN V Voltage Select Operation Logic Low Threshold VSX-Low Logic High Threshold VSX-High VSx Pin Current Threshold voltage for Logic Low Threshold voltage for Logic High (internally pulled high; can be left floating to achieve logic high) VIN = 5.5V VSx = GND VSx = VIN VSx = Open IVSX 1.8 50 0 0 µA Power OK Operation (Open Drain) POK threshold High POK threshold low POK Low Voltage POK High Voltage Output Rise Time Percentage of VOUT Nominal Percentage of VOUT Nominal IPOK = 4 mA (Max sink Current) VOUT Rise Time Accuracy 120 90 TRISE = Css* 75KΩ; ∆TRISE -25 10nF ≤ CSS ≤30nF 0.4 VIN % % V % +25 % (Note 4) Parallel Operation With 2 – 4 converters in parallel, the difference between any 2 parts. ∆VIN < 50mV; RTRACE < 10mΩ. ∆IOUT Current Balance +/-10 % NOTES: 3. Maximum output current may need to be de-rated, based on operating condition, to meet TJ requirements. 4. Parameter not production tested but is guaranteed by design. Rise time begins when AVIN > VUVLO and Enable=HIGH. Typical Performance Characteristics 95 95 VOUT=2.5V 85 VOUT=1.8V 80 VOUT=1.5V 75 VOUT=1.2V 70 90 VOUT=3.3V 85 VOUT=2.5V VOUT=1.2V 70 65 60 60 VIN=3.3V VOUT=1.5V 75 65 55 VOUT=1.8V 80 Efficiency (%) Efficiency (%) 90 55 VIN=5.0V 50 50 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 0.5 ©Enpirion 2009 all rights reserved, E&OE 03816 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Load Current (A) Load Current (A) Efficiency vs. Load, VIN = 3.3V.; Load = 0-6A. 1 Efficiency vs. Load, VIN = 5.0V.; Load = 0-6A. 8 9/18/2009 www.enpirion.com Rev:B EN5365QI Ripple Voltage, 5.0VIN/1.2VOUT, IOUT=6A, COUT = 3x22uF. Ripple Voltage, 3.3VIN/1.2VOUT, IOUT=6A, COUT = 3x22uF. Transient Response 5.5VIN/1.2VOUT, 0-6A, 10A/uS. COUT = 50uF Transient Response 5.5VIN/3.3VOUT, 0-6A, 10A/uS. COUT = 50uF Start up waveforms VIN=5.0V, VOUT=1.2V, CSS=15nF, Ch 1 = VOUT, Ch 3 = ENABLE, Ch 4 = POK. ©Enpirion 2009 all rights reserved, E&OE 03816 Start up waveforms VIN=5.0V, VOUT=3.3V, CSS=15nF, Ch 1 = VOUT, Ch 3 = ENABLE, Ch 4 = POK. 9 9/18/2009 www.enpirion.com Rev:B EN5365QI Theory of Operation Synchronous Buck Converter Table 1: Output Voltage Select Table The EN5365QI is a synchronous, pin programmable power supply with integrated power MOSFET switches and integrated inductor. The nominal input voltage range is 2.375-5.5V. The output can be set to common pre-set voltages by connecting appropriate combinations of 3 voltage selection pins to ground. The feedback control loop is a type III voltage-mode and the part uses a low-noise PWM topology. Up to 6A of output current can be drawn from this converter. The 5MHz operating frequency enables the use of small-size output capacitors. The power supply has the following protection features: • Programmable over-current protection (to protect the IC from excessive load current) • Thermal shutdown with hysteresis. • Over-voltage protection • Under-voltage lockout circuit to disable the converter output when the input voltage is less than approximately 2.2V Additional features include: • • VS0* Output Voltage 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 3.3V 2.5V 1.8V 1.5V 1.25V 1.2V 0.8V Reserved Input Capacitor Selection The EN5365QI requires about 40-50uF of input capacitance. Low ESR ceramic capacitors are required with X5R or X7R dielectric formulation. Y5V or equivalent dielectric formulations must not be used as they lose capacitance with frequency, temperature and bias voltage. In some applications, lower value ceramic capacitors maybe needed in parallel with the larger capacitors in order to provide high frequency decoupling. Description 22uF, 10V, X5R, 1206 (2 capacitors needed) 47uF, 10V, X5R, 1210 (1 capacitor needed) Output Voltage Programming The EN5365QI output voltage is programmed using a 3-pin voltage-ID or VID selector. Three binary VID pins allow the user to choose one of seven pre-set voltages. Refer to table 1 for the proper VID pin settings to program VOUT. The voltage select pins, VS0, VS1, and VS2, are pulled-up internally and so will default to a logic high, or “1”, if left “open”. Connecting the voltage select pin to ground will result in a logic “0”. 03816 VS1* Table 2. Recommended input capacitors. Soft-start circuit, limiting the in-rush current when the converter is powered up. Power good circuit indicating whether the output voltage is within 90%-120% of the programmed voltage. ©Enpirion 2009 all rights reserved, E&OE VS2* MFG Murata P/N GRM31CR61A226ME19L Taiyo Yuden Murata LMK316BJ226ML-T GRM32ER61A476KE20L Taiyo Yuden LMK325BJ476MM-T Output Capacitor Selection The EN5365QI has been optimized for use with approximately 50µF of output capacitance. Low ESR ceramic capacitors are required with X5R or X7R dielectric formulation. Y5V or equivalent dielectric formulations must not be used as these lose capacitance with frequency, temperature and bias voltage. 10 9/18/2009 www.enpirion.com Rev:B EN5365QI customization for a given application. For more information, contact Enpirion Applications Engineering support. Table 3. Recommended output capacitors. Description 22uF, 6.3V, 10% X5R, 1206 (3 capacitors needed) 47uF, 10V, 10% X5R, 1210 47uF, 6.3V, 10% X5R, 1210 (1 capacitor needed) MFG Murata P/N GRM31CR60J226KE19L Taiyo Yuden JMK316BJ226KL-T Murata GRM32ER61A476KE20L AVX 12106D476KAT2 Enable Operation Output ripple voltage is primarily determined by the aggregate output capacitor impedance. At the 5MHz switching frequency output impedance, denoted as Z, is comprised mainly of effective series resistance, ESR, and effective series inductance, ESL: Z = ESR + ESL. Placing output capacitors in parallel reduces the impedance and will hence result in lower ripple voltage. 1 Z Total = 1 1 1 + + ... + Z1 Z 2 Zn Typical ripple versus capacitor arrangement is given below: Output Capacitor Configuration 1 x 47uF 3 x 22 uF The SS pin in conjunction with a small capacitor between this pin and AGND provides the soft start function to limit the in-rush current during start-up. During start-up of the converter the reference voltage to the error amplifier is gradually increased to its final level by an internal current source of typically 10uA charging the soft start capacitor. The typical soft-start time for the output to reach regulation voltage, from when AVIN > VUVLO and Enable crosses its logic high threshold, is given by: Where the soft-start time TSS is in seconds and the soft-start capacitance CSS is in Farads. Typically, a capacitor of around 15 nF is recommended. Compensation The EN5365 is internally compensated through the use of a type 3 compensation network and is optimized for use with about 50µF of output capacitance and will provide excellent loop bandwidth and transient performance for most applications. Voltage mode operation provides high noise immunity at light load. Further, Voltage mode control provides superior impedance matching to sub 90nm loads. In some cases modifications to the compensation may be required. The EN5365QI provides the capability to modify the control loop to allow for 03816 Soft-Start Operation TSS = CSS * 75KΩ (seconds) Typical Output Ripple (mVp-p) (as measured on EN5365QI Evaluation Board) 30 15 ©Enpirion 2009 all rights reserved, E&OE The ENABLE pin provides a means to shut down the device, or enable normal operation. A logic low will disable the converter and cause it to shut down. A logic high will enable the converter into normal operation. When the ENABLE pin is asserted high, the device will undergo a normal soft start. During the soft-start cycle, when the soft-start capacitor reaches 0.75V, the output has reached its programmed regulation range. Note that the soft-start current source will continue to operate, and during normal operation, the soft-start capacitor will charge up to a final value of 2.5V. POK Operation The POK signal is an open drain signal from the converter indicating the output voltage is within the specified range. The POK signal will be a logic high when the output voltage is within 90% 120% of the programmed output voltage. If the 11 9/18/2009 www.enpirion.com Rev:B EN5365QI output voltage goes outside of this range, the POK signal will be a logic low until the output voltage has returned to within this range. In the event of an over-voltage condition the POK signal will go low and will remain in this condition until the output voltage has dropped to 95% of the programmed output voltage before returning to the high state. Over-Voltage Protection The internal POK FET is designed to tolerate up to 4mA. The pull-up resistor value should be chosen to limit the current from exceeding this value when POK is logic low. Thermal Overload Protection Over-Current Protection The current limit function is achieved by sensing the current flowing through a sense P-MOSFET. When the sensed current exceeds the current limit, both NFET and PFET switches are turned off. If the over-current condition is removed, the over-current protection circuit will re-enable the PWM operation. If the over-current condition persists, the circuit will continue to protect the load. The OCP trip point is nominally set to 150% of maximum rated load. For diagnostic purposes, it is possible to increase the OCP trip point to approximately 200% of the maximum rated load by connecting a 10kΩ resistor between the ROCP pin (pin 38) and AGND (pin 39). This is intended for troubleshooting purposes only and the specification is not guaranteed. ©Enpirion 2009 all rights reserved, E&OE 03816 When the output voltage exceeds 120% of the programmed output voltage, the PWM operation stops, the lower N-MOSFET is turned on and the POK signal goes low. When the output voltage drops below 95% of the programmed output voltage, normal PWM operation resumes and POK returns to its high state. Thermal shutdown will disable operation when the Junction temperature exceeds approximately 150ºC. Once the junction temperature drops by approx 20ºC, the converter will re-start with a normal soft-start. Input Under-Voltage Lock-Out Circuitry is provided to ensure that when the input voltage is below the required voltage level (VUVLO) for normal operation, the converter will not start-up. Circuits for hysteresis and input deglitch are included to ensure high noise immunity and to prevent false tripping. Parallel Device Operation The EN5365QI is capable of paralleling up to a total of four converters to provide up to 24A of continuous current. Please refer to the Parallel Operation Application note, available on the Enpirion website www.enpirion.com, for details on parallel operation. 12 9/18/2009 www.enpirion.com Rev:B EN5365QI Layout Recommendations Compensation Test Points AGND Test Points High-Frequency Noise Suppression Vias VOUT(+) Copper Local Ground Copper Thermal Pad Vias and Soldermask Opening VIN(+) Copper Vout Slit separating input local ground from output local ground PGND Copper Slit Vin Figure 5. Layout of power and ground copper. Figure 6. Use of thermal & noise suppression vias. Recommendation 1: Input and output filter capacitors should be placed as close to the EN5365QI package as possible to reduce EMI from input and output loop currents. This reduces the physical area of the Input and Output AC current loops. These vias can be the same size as the thermal vias discussed in recommendation 3. Recommendation 5: The system ground plane referred to in recommendations 3 and 4 should be the first layer immediately below the surface layer. This ground plane should be continuous and un-interrupted below the converter and the input/output capacitors shown in figure 6. Recommendation 2: Place a slit in the input/output capacitor ground copper starting just below the common connection point of the device GND pins as shown in figures 5 and 6. Recommendation 6: As with any switch-mode DC/DC converter, do not run sensitive signal or control lines underneath the converter package. Recommendation 3: The large thermal pad underneath the component must be connected to the system ground plane through as many vias as possible. The drill diameter of the vias should be less than 0.33mm, and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.26mm. This connection provides the path for heat dissipation from the converter. Please see figures 6, 7, and 8. Please refer to the Gerber files and summarized layout notes available on the Enpirion website www.enpirion.com for more layout details. NOTE: Figures 5 and 6 show only the critical components and traces for a minimum footprint layout. ENABLE, Vout-programming, and other small signal pins need to be connected and routed according to the specific application. Recommendation 4: Multiple small vias should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane as shown in figure 6. ©Enpirion 2009 all rights reserved, E&OE 03816 13 9/18/2009 www.enpirion.com Rev:B EN5365QI Design Considerations for Lead-Frame Based Modules Exposed Metal on Bottom Of Package Lead frame offers many advantages in thermal performance, in reduced electrical lead resistance, , and in overall foot print. However, they do require some special considerations. In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several small pads being exposed on the bottom of the package. Only the large thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board. The PCB top layer under the EN5365QI should be clear of any metal except for the large thermal pad. The “grayed-out” area in Figure 7 represents the area that should be clear of any metal (traces, vias, or planes), on the top layer of the PCB. Figure 8 demonstrates the recommended PCB footprint for the EN5365QI. Figure 9 shows the shape and location of the exposed metal pads as well as the mechanical dimension of the large thermal pad and the pins. Ground copper my extend under this pad. However, DO NOT CONNECT (NC) Figure 7. Lead-Frame exposed metal. Grey area highlights exposed metal that is not to be mechanically or electrically connected to the PCB. ©Enpirion 2009 all rights reserved, E&OE 03816 14 9/18/2009 www.enpirion.com Rev:B EN5365QI Figure 8. Recommended footprint for PCB. ©Enpirion 2009 all rights reserved, E&OE 03816 15 9/18/2009 www.enpirion.com Rev:B EN5365QI Package Dimensions Figure 9. Package dimensions. ©Enpirion 2009 all rights reserved, E&OE 03816 16 9/18/2009 www.enpirion.com Rev:B EN5365QI Contact Information Enpirion, Inc. Perryville III 53 Frontage Road, Suite 210 Hampton, NJ 08827 Phone: 908-894-6000 Fax: 908-894-6090 www.Enpirion.com Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment used in hazardous environment without the express written authority from Enpirion. ©Enpirion 2009 all rights reserved, E&OE 03816 17 9/18/2009 www.enpirion.com Rev:B