MP7533 15 V CMOS Multiplying10-Bit Digital-to-Analog Converter FEATURES BENEFITS • • • • • • • • • • Accurate Converter at Low Cost • Can be used in Reverse Mode (Voltage Out) • Flexible Design 10-Bit Resolution Non-Linearity: 1/2 LSB to 2 LSB Nonlinearity Tempco: 0.2 ppm of FSR/°C, Max. Low Power Dissipation: 20 mW Current Settling Time: 500 ns Feedthrough Error: 1 mV p-p @ 10 kHz, Max. TTL/CMOS Compatible Latch-Up Free Improved Replacement for AD7533 APPLICATIONS • • • • Digital/Analog Multiplication Character Generation Programmable Power Supplies Gain Controlled Circuits Pin and functional equivalent to the industry standard MP7520, the MP7533 is recommended as a lower cost alternative for old MP7520 sockets or new 10-bit DAC designs. GENERAL DESCRIPTION The MP7533 is a low cost, 10-bit multiplying Digital-to-Analog Converter. This device uses EXAR’s patented advanced thin film resistor and CMOS technologies, providing up to 10-bit accuracies with TTL/CMOS compatibility. The MP7533 applications include: digital-to-analog multiplication, CRT character generation, programmable power supplies, digitally controlled gain circuits, etc. SIMPLIFIED BLOCK DIAGRAM VDD 2R 2R 2R RFB VREF 4R 4R 4R 4R 4R 4R 4R R IOUT1 IOUT2 2 to 3 Decoder Switch Drivers & Switches R = 10k BIT 1 MSB BIT 10 LSB 3 Segment D/A Converter with Termination to DGND Logical “1” at Digital Input Steers Current to IOUT1 Rev. 2.00 1 MP7533 ORDERING INFORMATION Package Type Temperature Range Part No. INL (LSB) DNL (LSB) Gain Error (% FSR) Plastic Dip –40 to +85°C MP7533JN +2 +1 1.5 Plastic Dip –40 to +85°C MP7533KN +1 +1 1.5 Plastic Dip –40 to +85°C MP7533LN +1/2 +1 1.5 SOIC –40 to +85°C MP7533JS +2 +1 1.5 SOIC –40 to +85°C MP7533KS +1 +1 1.5 SOIC –40 to +85°C –40 to +85°C MP7533LS +1/2 +1 1.5 Ceramic Dip MP7533AD +2 +1 1.5 Ceramic Dip –40 to +85°C MP7533BD +1 +1 1.5 Ceramic Dip –40 to +85°C MP7533CD +1/2 +1 1.5 Ceramic Dip –55 to +125°C MP7533SD* +2 +1 1.5 Ceramic Dip –55 to +125°C MP7533TD* –55 to +125°C +1 +1 1.5 Ceramic Dip MP7533UD* +1/2 +1 1.5 *Contact factory for non-compliant military processing PIN CONFIGURATIONS IOUT1 IOUT2 GND (MSB) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 See Packaging Section for Package Dimensions 16 1 15 2 3 14 4 13 5 12 6 11 7 10 8 9 RFB VREF VDD BIT 10 (LSB) BIT 9 BIT 8 BIT 7 BIT 6 1 16 2 15 3 4 5 16 Pin CDIP, PDIP (0.300”) D16, N16 See Pin Out at Left 14 13 12 6 11 7 10 8 9 16 Pin SOIC (Jedec, 0.300”) S16 PIN OUT DEFINITIONS PIN NO. NAME DESCRIPTION PIN NO. NAME DESCRIPTION 1 IOUT1 Current Output 1 9 BIT 6 Data Input Bit 6 2 IOUT2 Current Output 2 10 BIT 7 Data Input Bit 7 3 GND Ground 11 BIT 8 Data Input Bit 8 4 BIT 1 Data Input Bit 1 (MSB) 12 BIT 9 Data Input Bit 9 5 BIT 2 Data Input Bit 2 13 BIT 10 Data Input Bit 10 (LSB) 6 BIT 3 Data Input Bit 3 14 VDD Positive Power Supply 7 BIT 4 Data Input Bit 4 15 VREF Reference Input Voltage 8 BIT 5 Data Input Bit 5 16 RFB Internal Feedback Resistor Rev. 2.00 2 MP7533 ELECTRICAL CHARACTERISTICS (VDD = + 15 V, VREF = +10 V unless otherwise noted) Parameter Symbol Min 25°C Typ Max Tmin to Tmax Min Max Units STATIC PERFORMANCE1 Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) A, S, J B, T, K C, U, L Differential Non-Linearity A, S, J B, T, K C, U, L Gain Error FSR = Full Scale Range N 10 10 Bits INL LSB +2 +1 +1/2 +1 +1 +1 +1 +1 +1 +1.5 +1.5 % FSR Using Internal RFB +2 ppm/°C ∆Gain/∆Temperature +50 +50 ppm/% |∆Gain/∆VDD| ∆VDD = + 5% +50 +200 nA 20 kΩ 0.8 +1 V V µA LSB GE TCGE Power Supply Rejection Ratio PSRR Best Fit Straight Line Spec. (Max INL – Min INL) / 2 +2 +1 +1/2 DNL Gain Temperature Coefficient2 Output Leakage Current Test Conditions/Comments +0.4 +30 IOUT REFERENCE INPUT Input Resistance RIN 5 10 VIH VIL 3.0 2.4 20 5 DIGITAL INPUTS3 Logical “1” Voltage Logical “0” Voltage Input Leakage Current 3.0 ILKG 0.8 +1 COUT1 COUT1 COUT2 COUT2 52 26 13 45 ANALOG OUTPUTS Output Capacitance2 pF pF pF pF DAC Inputs all 1’s DAC Inputs all 0’s DAC Inputs all 1’s DAC Inputs all 0’s V mA mW All digital inputs = 0 or all = 5 V POWER SUPPLY4 Functional Voltage Range2 Supply Current Total Dissipation VDD IDD 4.5 15 2 20 4.5 15 2 NOTES: 1 2 3 4 Full Scale Range (FSR) is 10V for unipolar mode. Guaranteed but not production tested Digital Input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. Specified values guarantee functionality. Refer to other parameters for accuracy. Specifications are subject to change without notice Rev. 2.00 3 MP7533 ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 seconds) . . . . . . +300°C Package Power Dissipation Rating to 75°C CDIP, PDIP, SOIC, PLCC . . . . . . . . . . . . . . . . . . 700mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 10mW/°C VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V Digital Input Voltage to GND . . . . GND –0.5 to VDD +0.5 V IOUT1, IOUT2 to GND . . . . . . . . . . . . . . . . –0.5 to VDD +0.5 V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 20mA for less than 100µs. APPLICATION NOTES Refer to Section 8 for Applications Information Rev. 2.00 4 MP7533 16 LEAD CERAMIC DUAL-IN-LINE (300 MIL CDIP) D16 S1 See Note 1 S 16 9 1 8 E1 E D Q Base Plane Seating Plane A L e c b INCHES SYMBOL L1 b1 NOTES MILLIMETERS MIN MAX MIN A –– 0.200 –– 5.08 –– b 0.014 0.023 0.356 0.584 –– b1 0.038 0.065 0.965 1.65 2 c 0.008 0.015 0.203 0.381 –– D –– 0.840 –– 21.34 4 E 0.220 0.310 5.59 7.87 4 E1 0.290 0.320 7.37 8.13 7 e 0.100 BSC MAX 2.54 BSC NOTES 5 L 0.125 0.200 3.18 5.08 –– L1 0.150 –– 3.81 –– –– Q 0.015 0.060 0.381 1.52 3 S –– 0.080 –– 2.03 6 0.005 –– 0.13 –– 6 0° 15° 0° 15° –– S1 α α Rev. 2.00 5 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center. MP7533 16 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) N16 S 16 9 1 8 Q1 E1 E D A1 Seating Plane A L B B1 e α MILLIMETERS INCHES SYMBOL MIN MAX MIN –– 0.200 –– 5.08 A1 0.015 –– 0.38 –– B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 0.745 0.785 18.92 19.94 E 0.295 0.325 7.49 8.26 E1 0.220 0.310 5.59 7.87 A e 0.100 BSC MAX 2.54 BSC L 0.115 0.150 2.92 3.81 α 0° 15° 0° 15° Q1 0.055 0.070 1.40 1.78 S 0.020 0.080 0.51 2.03 Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. Rev. 2.00 6 C MP7533 16 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S16 D 16 9 E H 8 h x 45° C A Seating Plane B e α A1 L INCHES SYMBOL MIN MILLIMETERS MAX MIN MAX A 0.097 0.104 2.46 2.64 A1 0.0050 0.0115 0.127 0.292 B 0.014 0.019 0.356 0.482 C 0.0091 0.0125 0.231 0.318 D 0.402 0.412 10.21 10.46 E 0.292 0.299 7.42 7.59 e 0.050 BSC 1.27 BSC H 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 L 0.016 0.035 0.406 0.889 α 0° 8° 0° 8° Rev. 2.00 7 MP7533 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.00 8