MP7680 5 V CMOS 12-Bit Quad Double-Buffered Multiplying Digital-to-Analog Converter June 2000-2 FEA TURES · · · · · · · · · Exar Pioneered Segmented DAC Approach Four Double-Buffered 12-bit DACs on a Single Chip Independent Reference Inputs Lowest Gain Error in a Multiple DAC Chip Guaranteed Monotonic TTL/5 V CMOS Compatible Inputs Industry Standard Digital Interface Four Quadrant Multiplication Latch-Up Free GENERAL · Reduced Board Space; Lower System Cost. · Independent Control of DACs · Excellent DAC-to-DAC Matching and Tracking APPLICA TIONS · · · · Function Generators Automatic Test Equipment Precision Process Controls Recording Studio Control Boards DESCRIPTIONS The MP7680 and the integrate four 12-bit four-quadrantmultiplying DACs with independent reference inputs and excellent matching characteristics. The MP7680 grades offer 1/2, 1 and 2 LSB of relative accuracy. The superior offers a low 2 LSB of gain error. ORDERING BENEFITS INFORMA Each DAC has double-buffering (an 8 and 4-bit latch and a 12-bit latch) between the data bus (DB11 - DB0) and the DAC. The internal 4-bit mux allows the use of 8 or 16-bit buses. The flexible latch control logic allows to update one or more DACs simultaneously. TION Package Type Temperature Range Part No. INL (LSB) DNL (LSB) Gain Error (LSB) Plastic Dip Plastic Dip -40 to +85°°C -40 to +85°°C MP7680JN +2 +4 +16 MP7680KN +1 +2 +16 PQFP -40 to +85°°C MP7680JE +2 +4 +16 PQFP -40 to +85°°C MP7680KE +1 +2 +16 Rev. 3.10 E1998 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7017 MP7680 DVDD AVDD 8-Bit Latch 12-Bit Latch 4-Bit Latch 8-Bit Latch 4-Bit Latch 8-Bit Latch 4-Bit Latch DB11 - DB4 (MSB) 8 4 DB3 - DB0 (LSB) B1/B2 4 0 MUX 1 8 4 8-Bit Latch 12-Bit Latch DAC B 12-Bit Latch DAC C 12-Bit Latch 4-Bit Latch 8 DAC A DAC D DAC Latches Control A1 A0 CS WR2 XFER WR2 Figure 1. Simplified Rev. 3.10 2 Block Diagram IOUT2A VREFA RFBB IOUT1B IOUT2B VREFB RFBC IOUT1C IOUT2C VREFC RFBD IOUT1D IOUT2D VREFD 1 Input Latches Control RFBA IOUT1A DGND AGND MP7680 PIN CONFIGURA TIONS A1 XFER WR2 WR1 CS NC VREFA RFBA IOUT1A IOUT2A IOUT2B IOUT1B RFBB VREFB (MSB) DB11 DB10 DB9 DB8 DB7 DB6 1 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 A0 B1/B2 DVDD AVDD DGND AGND VREFD RFBD IOUT1D IOUT2D IOUT2C IOUT1C RFBC VREFC DB0 (LSB) DB1 DB2 DB3 DB4 DB5 AGND V REFD R FBD I OUT1D I OUT2D NC I OUT2C I OUT1C V FBC V REFC DBO 40 Pin PDIP , (0.600”) 33 DGND AV DD DVDD B1/B2 AO NC A1 XFER WR2 WR1 CS 23 22 34 See the following page for pin descriptions 12 44 1 11 DB11 V REFB R FBB I OUT1B I OUT2B NC I OUT2A I OUT1A R FBA V REFA NC 44 Pin PQFP Rev. 3.10 3 DB1 DB2 DB3 DB4 DB5 NC DB6 DB7 DB8 DB9 DB10 MP7680 PIN DESCRIPTION 40 Pin PDIP , CDIP PIN NO. 44 Pin PQFP NAME DESCRIPTION PIN NO. NAME DESCRIPTION 1 A1 DAC Address Bit 1 1 NC No Connection 2 XFER Transfer: Updates all DAC’s 2 VREFA Reference Input for DAC A 3 WR2 Write 2: Gates the XFER Function 3 RFBA Feedback Resistor for DAC A 4 WR1 Write 1: Gates the DAC Selection 4 IOUT1A Current Output A IOUT2A Complement of Output A 5 CS Chip Select 5 6 NC No Connection 6 NC No Connection 7 VREFA Reference Input for DAC A 7 IOUT2B Complement of Output B 8 RFBA Feedback Resistor for DAC A 8 IOUT1B Current Output B 9 IOUT1A Current Output A 9 RFBB Feedback Resistor for DAC B 10 IOUT2A Complement of Output A 10 VREFB Reference Input for DAC B 11 IOUT2B Complement of Output B 1116 DB11 to Input Data Bits 11 (MSB) to 6 DB6 12 IOUT1B Current Output B 17 NC No Connection 13 RFBB Feedback Resistor for DAC B VREFB Reference Input for DAC B DB5DB0 Input Data Bits 5 to 0 (LSB) 14 1823 15 26 DB11 to Input Data Bits 11 (MSB) to 0 (LSB) DB0 24 VREFC Reference input for DAC C 25 RFBC Feedback Resistor for DAC C 27 VREFC Reference input for DAC C 26 IOUT1C Current Output C 28 RFBC Feedback Resistor for DAC C 27 IOUT2C Complement of Output C 29 IOUT1C Current Output C 28 NC No Connection IOUT2D Complement of Output D 30 IOUT2C Complement of Output C 29 31 IOUT2D Complement of Output D 30 IOUT1D Current Output D 32 IOUT1D Current Output D 31 RFBD Feedback Resistor for DAC D 33 RFBD Feedback Resistor for DAC D 32 VREFD Reference input for DAC D 34 VREFD Reference input for DAC D 33 AGND Analog Ground 35 AGND Analog Ground 34 DGND Digital Ground 36 DGND Digital Ground 35 AVDD Analog Power Supply 37 AVDD Analog Power Supply 36 DVDD Digital Power Supply 38 DVDD Digital Power Supply 37 B1/B2 Select Input Format (8/4 or 12 bits in) 39 B1/B2 Select Input Format (8/4 or 12 bits in) 38 A0 DAC Address Bit 0 39 NC No Connection 40 A0 DAC Address Bit 0 40 A1 DAC Address Bit 1 41 XFER Transfer: Updates all DAC’s 42 WR2 Write 2: Gates the XFER Function 43 WR1 Write 1: Gates the DAC Selection 44 CS Chip Select Rev. 3.10 4 MP7680 ELECTRICAL CHARACTERISTICS (V D D = + 5 V, V R E F = +10 V, I O U T 1 = I O U T 2 = DGND = AGND 25 °C Parameter Symbol ST ATIC PERFORMANCE Min Typ Max = 0 V Unless Tmin to Tmax Min Max Units N Integral Non-Linearity (Relative Accuracy) K J 12 12 LSB +1 +2 +1 +2 +1 +4 +2.0 +4.0 +16 +16 +16 +16 DNL Gain Error K J LSB Using Internal RFB +2 ppm/°°C DGain/DTemperature ppm/% |DGain/DVDD| DVDD = + 5% nA IOUT1 VIN = 0 V IOUT2 VIN = VDD Gain Temperature Coefficient2 TCGE Power Supply Rejection Ratio PSRR +50 +70 IOUT +50 +200 Output Leakage Current REFERENCE Best Fit Straight Line Spec. (Max INL - Min INL) / 2 LSB GE Current Settling Time Test Conditions/Comments Bits INL Differential Non-Linearity K J PERFORMANCE Noted) 1 Resolution (All Grades) DYNAMIC Otherwise RL=100W, CEXT=13pF 2 tS 1.0 ms Full scale change to 1/2 LSB INPUT Input Resistance Voltage Input Range2 RIN VIN 3 VIH VIL 2.4 5 +10 7 +25 3 7 kW V DIGIT AL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance2 Data Control ANALOG OUTPUTS 2.4 0.8 +1 ILKG 0.8 +4 V V mA CIN CIN 7.0 7.0 pF pF COUT1 COUT1 COUT2 COUT2 100 50 50 100 pF pF pF pF VIN = 0 V and VDD 2 Output Capacitance Rev. 3.10 5 DAC all 1’s DAC all 0’s DAC all 1’s DAC all 0’s MP7680 ELECTRICAL CHARACTERISTICS (CONT’D) 25 °C Parameter POWER Symbol Typ Tmin to Tmax Max Min 5.5 2 1 4.5 Max Units Test Conditions/Comments SUPPL Y 4 Functional Voltage Range Supply Current TIMING Min CHARACTERISTICS VDD IDD 4.5 5.5 2 1 V mA mA tWR tCS tAS tH 75 100 100 0 85 120 120 0 ns ns ns ns tBS tBH tDS tDH 120 10 100 0 65 175 150 15 120 0 75 200 ns ns ns ns ns ns Digital inputs = VIL or VIH Digital inputs = 0 or 5 V 2, 3 Write Pulse Width Chip Select Set-Up Time Address Set-Up Time Chip Select and Address Hold Time Latch Select Set-Up Time Latch Select Hold Time Data Valid Set-Up Time Data Valid Hold Time Transfer Pulse Width Write Cycle (per DAC) tXFER tWC Notes: 1 2 Full Scale Range (FSR) is 10V for unipolar mode. Guaranteed but not production tested. See timing diagram (Figure 2.). DV D D and AV D D are connected through the silicon substrate. Connect DC voltage differences will cause undesirable internal currents. 3 4 Specifications ABSOLUTE MAXIMUM RA TINGS are subject to change (T A = +25 °C unless VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 V Digital Input Voltage to DGND . . . . GND -0.5 to VDD +0.5 V Any IOUT1, IOUT2 to AGND . . . . . . . GND -0.5 to VDD +0.5 V Any VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality Guaranteed +0.5 V) together without at the package. notice otherwise noted) 1, 2 Any VRFB to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V Storage Temperature . . . . . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (Soldering, 10 seconds) . . . . . . . +300°C Package Power Dissipation Rating to 75°C CDIP, PDIP, PQFP . . . . . . . . . . . . . . . . . . . . . . . . . 800mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 11mW/°C Notes: 1 2 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability . Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100 ms. Rev. 3.10 6 MP7680 CS tCS tH tAS tH NOTES: A0, A1 1. tBH tBS 2. B1/B2 WR1 The timing of Figure the conditions Theory VALID of Operation). tWR tWC XFER tXFER WR2 Figure XFER = WR2 2. reproduces 2. W rite Cycle T iming Rev. 3.10 7 (Each DAC) graphically that all control signals must meet in any of the many possible tDH tDS DATA t XFER is the timing of the condition = Low . VALID writing cycles (see MP7680 INPUT LA TCHES 8 DB11-DB4 (MSB) D 0 DB11DB8 4 MUX 1 DB3-DB0 (LSB) Q B1 E Latch B2 Q 4 E Latch 8 B1/B2 B2 Q 4 E Latch 4 Enable A A1 (MSB) A0 (LSB) CS Latch Address Decoder Q DAC DD11 - DD0 12 D D B2 Q 4 E Latch RFBB IOUT1B IOUT2B RFBC IOUT1C IOUT2C VREFC E 8 Enable B DAC DC11 - DC0 12 D IOUT2A VREFB 8 B2 Q 4 E Latch Q B1 E Latch Q E D D Disable-B1 D RFBA IOUT1A VREFA DB11 - DB0 12 D Q B1 E Latch DAC E Q B1 E Latch D 4 Q 8 D 8 DA11 - DA0 12 D D 8 4 DAC LA TCHES LA11 - LA0 8 Q E DAC RFBD IOUT1D IOUT2D VREFD Transfer Enable C Enable D WR1 XFER WR2 Figure 3. Latches Control Logic THEOR Y OF OPERA TION Digital Interface W riting to Input Latches shows the internal control logic. The logic that controls the writing of the input latches and the one that controls the DAC latches are completely separated. It is easy to understand how the MP7680/80A works by understanding each basic operation. By keeping B1/B2 = high, a 12-bit bus has direct access to the 12 bits of the input latches. The condition CS = WR1 = 0 loads the values contained in the data bus DB11-DB0 into the input latch addresses by A1, A0 (Figure 4. , Table 1. ). Figure 3. Rev. 3.10 8 MP7680 A1 A0 0 0 1 1 0 1 0 1 (Figure 5. ) During the second cycle the condition B1/B2 = low muxes DB11-DB8 to the B2 latches (Figure 3. ). SELECTED DAC Two important notes: A B C D 1) Timing diagrams show the inputs CS, A1, A0, DB11-DB0 to be stable during the entire writing cycle. In reality all the above signals can change (Figure 4. ) as long as they meet the timing conditions specified in the Electrical Characteristic Table. 2) Only 16-bit bus cycles are shown in the next few examples of interface timing. It is possible to generate an 8-bit interface timing by replacing a single 12-bit write cycle (Figure 4. ) with a double 8-bit write cycles (Figure 5. ) 8-bit applications should ground inputs DB3-DB0. Table 1. DAC Selection An 8-bit bus must use two cycles. The second cycle is like the first one with the difference that B1/B2 = low CS CS A1, A0 A1, A0 B1/B2 DATA High High or B1/B2 DATA to B1 & B2 WR1 to B1 to B2 WR1 Figure 4. 12 Bit W rite Cycle Figure 5. 8-Bit Double XFER WR2 or or DA11-0 IOUT tS Figure 6. Transfer Cycles from Input Latches Rev. 3.10 9 to DAC Latches W rite Cycle MP7680 Transferring Data to the DAC Latches Once one or all of the input latches have been loaded, the condition XFER = WR2= low transfers the content of ALL the input latches in the DAC latches. The output of the DAC latches (DA11-DA0) changes and the DAC current (IOUT) will reach a new stable value within the settling time tS (Figure 6. ). transfer cycle updates the output of all DACs (Figure 7. ) 2) Individual DAC update. The condition WR2 = XFER = low makes the DAC latches transparent. A writing to the B1/B2 latches updates the DAC outputs (Figure 8. ). 3) Automatic transfer to DAC latches. An 8-bit bus can update any DAC with two cycles by connecting WR1 = WR2 and B1/B2= XFER. This is the correct individual DAC update for 8-bit busses (Figure 9. ). 4) Transfer by a second device. A processor may load the input latches while the final XFER pulse is left to another device. Examples of DACs updating sequences: 1) Simultaneous updates of any number of DACs. The system uses from one (two) to four (eight) cycles to write from a 12 (8) bit bus into B1/B2 latches. One CS CS A0, A1 =0 =1 =2 =3 DATA Valid Valid Valid Valid A1, A0 =1 DATA Valid Valid WR1 WR2 = XFER WR1 XFER=WR2 IOUT1B IOUT1A, B, C, D IOUT1D Figure =3 7. Simultaneous Updates of DACs Figure 8. Individual CS A1, A0 =1 =2 B1/B2 and XFER WR1 and WR2 IOUTB IOUTC Figure 9. Automatic Transfer Rev. 3.10 10 to DAC Latches DAC Update MP7680 RFBA +15 V VREFA +10 V 7 2 6 +10 V 10k REF01 4 5k 5k 4 DAC A IOUT2A 10 + VOUTA 0 V to -10 V + VOUTB 0 V to +10 V + VOUTC 0 V to +5 V + VOUTD 0 V to -5 V RFBB 14 10 V 13 IOUT1B 12 DAC B IOUT2B 11 VREFB RFBC VREFC 5V 27 + REF02 10k 6 +5 V IOUT1A 9 10k + 8 DAC C IOUT2C 30 RFBD 10k 34 +5 V VREFD 2 28 IOUT1C 29 33 IOUT1D 32 DAC D IOUT2D 31 +15 V Figure 10. Digitally Programmable Quad Voltage Output + 10 V, + 5 V RFBA RA DAC A Left Channel Input + RFBB + DAC B Left Channel Output (+10 V MAX) Right Channel Input + RFBD DAC D DAC A 11. “Clickless” + Audio 33k 10k 1.2 V DAC B + 33k MP5010 DAC C VOUTC 10k DAC D + 33k 10k Figure 11 + 33k Matched Pairs: Rev. 3.10 VOUTB 10k Right Channel Output (+10 V MAX) Attenuator/Amplifier VOUTA 10k RFBA to RA RFBD to RD Figure + 10k RD DAC C 0.6 V +5 V + RFBC + + 12. Quad DAC for Single +5 V Supply VOUTD MP7680 Notes Rev. 3.10 12