SP504
61 SD(a)
62 VCC
63 TT(a)
64 GND
65 TT(b)
66 CS(a)
67 CS(b)
69 DM(b)
70 RD(a)
68 DM(a)
71 RD(b)
72 GND
73 VCC
74 VCC
75 GND
76 SCT(a)
77 SCT(b)
78 DSR
79 SCT
RxD 1
60 GND
RDEC0 2
59 SD(b)
RDEC1 3
58 TR(a)
RDEC2 4
57 GND
RDEC3 5
56 TR(b)
TTEN 6
55 VCC
SCTEN 7
54 RS(a)
N/C 8
53 GND
SP504
TDEC3 9
TDEC2 10
TDEC1 11
52 RS(b)
51 LL(a)
50 GND
TDEC0 12
49 LL(b)
IC(b) 40
IC(a) 39
RT(b) 38
RT(a) 37
RR(b) 36
RR(a) 35
GND 34
VCC 33
C2- 31
C2+ 28
VSS 32
41 VCC
C1- 30
42 ST(a)
RxC 20
GND 29
43 GND
DCD 19
V DD 27
44 ST(b)
V35_STAT 18
C1+ 26
45 RL(b)
RL 17
VCC 25
46 GND
RTS 16
LL 24
47 RL(a)
TxC 15
RI 21
48 VCC
TxD 14
ST 22
DTR 13
STEN 23
• +5V Only
• Seven (7) Drivers and Seven (7) Receivers
• Driver and Receiver Tri-State Control
• Reduced V.35 Termination Network
• Pin Compatible with the SP503
• Software Selectable Interface Modes:
-RS-232E (V.28)
-RS-422A (V.11, X.21)
-RS-449 (V.11 & V.10)
-RS-485
-V.35
-EIA-530 (V.11 & V.10)
-EIA-530A (V.11 & V.10)
-V.36
80 CTS
WAN Multi-Mode Serial Transceiver
DESCRIPTION
The SP504 is a single chip device that supports eight (8) physical serial interface standards
for Wide Area Network connectivity. The SP504 is fabricated using a low power BiCMOS
process technology, and incorporates an Exar patented (5,306,954) charge pump allowing
+5V only operation. Seven (7) drivers and seven (7) receivers can be configured via software for any of the above interface modes at any time. The SP504 is suitable for DTE-DCE
applications. The SP504 requires only one external resistor per V.35 driver for compliant
V.35 Operation.
Vcc
SWITCHABLE V.35
TERMINATION RESISTOR
NETWORKS
22µF, 16V
22µF, 16V
RxD
Vdd
C1C2+
Programmable Charge Pump
RxD
TxD
RxC
CTS
CTS
DSR
DSR
DCD
DCD
RI
22µF, 16V
Vss
C2-
RxC
SCT
22µF, 16V
C1+
SP504
DTR
DTR
RTS
RTS
RL
RL
LL
LL
ST
ST
TT
TT
RI
SCT
Receiver Decode
TxD
Driver Decode
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
SP504_102_121708
ABSOLUTE MAXIMUM RATINGS
STORAGE CONSIDERATIONS
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may
affect reliability.
Due to the relatively large package size of the 80-pin
quad flat-pack, storage in a low humidity environment
is preferred. Large high density plastic packages
are moisture sensitive and should be stored in Dry
Vapor Barrier Bags. Prior to usage, the parts should
remain bagged and stored below 40°C and 60%RH.
If the parts are removed from the bag, they should be
used within 48 hours or stored in an environment at
or below 20%RH. If the above conditions cannot be
followed, the parts should be baked for four hours at
125°C in order remove moisture prior to soldering.
Exar ships the 80-pin QFP in Dry Vapor Barrier Bags
with a humidity indicator card and desiccant pack.The
humidity indicator should be below 30%RH.
VCC.......................................................................+7V
Input Voltages:
Logic...........................-0.3V to (VCC+0.5V)
Drivers........................-0.3V to (VCC+0.5V)
Receivers..........................................±15V
Output Voltages:
Logic...........................-0.3V to (VCC+0.5V)
Drivers...............................................±14V
Receivers....................-0.3V to (VCC+0.5V)
Storage Temperature.......................-65˚C to +150˚C
Power Dissipation.......................................2000mW
Package Derating:
øJA................................................46 °C/W
øJC................................................16 °C/W
SPECIFICATIONS
TA = +25°C and VCC = +5.0V unless otherwise noted.
PARAMETER
MIN.
TYP.
MAX.
UNITS
0.8
Volts
CONDITIONS
Logic Inputs
VIL
VIH
2.0
Volts
LOGIC OUTPUTS
VOL
0.4
VOH
2.4
Volts
IOUT = +3.2mA
Volts
IOUT = -1.0mA
RS-485 DRIVER
TTL Input Levels
VIL
0.8
VIH
2.0
Volts
Volts
Outputs
HIGH Level Output
+6.0
LOW Level Output
-0.3
Differential Output
+/-1.5
Balance
Offset
Volts
+/-5.0
Volts
RL = 54Ω, CL = 50pF
+/-0.2
Volts
|VT| - |VT|
+2.5
Volts
Open Circuit Voltage
Output Current
+/-6.0
28.0
Short-Circuit Current
+/-250
Transition Time
20
Max. Transmission Rate
10
Propagation Delay tPHL
50
Volts
40
Volts
mA
RL = 54Ω
mA
Terminated in -7V to +10V
ns
Rise/Fall time, 10% to 90%
Mbps
80
100
ns
RL = 54Ω; Figure 3a
TA @ 25°C and VCC = +5V only Figures 3a and 5; RL= 54Ω, CL=50pF
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
SP504_102_121708
SPECIFICATIONS
TA = +25°C and VCC = +5.0V unless otherwise noted.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
50
80
100
ns
TA @ 25°C and VCC = +5V only Figures 3a and 5; RL= 54Ω, CL=50pF
20
40
ns
|tPHL - tPLH|; TA @ 25°C
0.4
Volts
RS-485 DRIVER (continued)
Propagation Delay tPLH
Differential Driver Skew
RS-485 RECEIVER
TTL Output Levels
VOL
VOH
2.4
Volts
Input
HIGH Threshold
+0.2
+12
Volts
(a)-(b)
LOW Threshold
-7.0
-0.2
Volts
(a)-(b)
Common Mode Range
-7.0
+12
Volts
HIGH Input Current
Refer to Receiver input graph
LOW Input Current
Refer to Receiver input graph
Receiver Sensitivity
+/-0.2
Volts
Input Impedance
12
kΩ
Max. Transmission Rate
10
Mbps
Propagation Delay tPHL
80
110
180
ns
Propagation Delay tPLH
80
110
180
ns
Differential Receiver Skew
30
ns
Over -7V to +12V common mode
Range
Figure 3a
TA @ 25°C and VCC = +5V only.
Figures 3a and 7; A is inverting
and B is non-inverting.
|tPHL - tPLH|; TA @ +25°C
V.35 DRIVER
TTL Input Levels
VIL
0.8
VIH
Outputs
2.0
Volts
Volts
All Outputs measured with 150Ω termination resistor connected to the non-inverting
outputs as shown in Figure 19.
Differential Output
+/-0.44
+/-0.66
Volts
Source Impedance
50
100
150
Ω
Short-Circuit Impedance
135
150
165
Ω
Voltage Output Offset
-0.6
Transition Time
+0.6
Volts
35
60
ns
Max. Transmission Rate
10
Propagation Delay tPHL
50
80
100
ns
Propagation Delay tPLH
50
80
100
ns
30
40
ns
0.4
Volts
DIfferential Driver Skew
Mbps
RL = 100Ω
VOUT = -2V to +2V; A = B
48kbps data rate; TA @ 25°C
RL = 100Ω
TA @ 25°C and VCC = +5V only
Figures 3b and 5
|tPHL - tPLH|; TA @ +25°C
V.35 RECEIVER
TTL Output Levels
VOL
VOH
2.4
Volts
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
SP504_102_121708
SPECIFICATIONS
TA = +25°C and VCC = +5.0V unless otherwise noted.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
V.35 RECEIVER (continued)
Input
Differential Threshold
+/-80
mV
Input Impedance
90
100
110
Ω
Short-Circuit Impedance
135
150
165
Ω
Max. Transmission Rate
10
Propagation Delay tPHL
100
130
200
ns
Propagation Delay tPLH
100
130
200
ns
DIfferential Receiver Skew
VIN = +2V to -2V
Mbps
30
ns
TA @ 25°C and VCC = +5V only
Figures 3b and 7; A is inverting and
B is non-inverting.
|tPHL - tPLH|; TA @ 25°C
RS-422 DRIVER (V.11)
TTL Input Levels
VIL
0.8
VIH
2.0
Volts
Volts
Outputs
Open circuit Voltage, VO
Differential Output, VT
+/-6.0
Volts
RL = 3.9kΩ
+/-2.0
+/-5.0
Volts
RL = 100Ω
0.5VO
0.67VO
Volts
TA @ 25°C
+/-0.4
Volts
|VT| - |VT|
Balance
Offset
Short Circuit Current
Power Off Current
Transition Time
+3.0
Volts
+/-150
mA
VOUT = 0V
+/-100
µA
VCC = 0V, VOUT = +/-0.25V
20
40
ns
Rise/Fall time, 10% - 90%
Max. Transmission Rate
10
Propagation Delay tPHL
50
80
100
ns
Propagation Delay tPLH
50
80
100
ns
TA @ 25°C and VCC = +5V only
Figures 3a and 5; RDIFF = 100Ω
20
40
ns
|tPHL - tPLH|; TA @ 25°C
0.4
Volts
Differential Skew
Mbps
RL = 100Ω; Figure 3a
RS-422 RECEIVER (V.11)
TTL Output Levels
VOL
VOH
2.4
Volts
Input
HIGH Threshold
+0.2
+6.0
Volts
(a)-(b)
LOW Threshold
-6.0
-0.2
Volts
(a)-(b)
Common Mode Range
-7.0
+7
Volts
HIGH Input Current
Refer to Receiver input graph
LOW Input Current
Refer to Receiver input graph
Receiver Sensitivity
+/-0.3
Volts
VCM = +7V to -7V
VIN = +10V to -10V
Input Impedance
4
kΩ
Max. Transmission Rate
10
Mbps
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
SP504_102_121708
SPECIFICATIONS
TA = +25°C and VCC = +5.0V unless otherwise noted.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
RS-422 RECEIVER (V.11) (continued)
Propagation Delay tPHL
80
110
180
ns
Propagation Delay tPLH
80
110
180
ns
DIfferential Receiver Skew
30
ns
TA @ 25°C and VCC = +5V only.
Figures 3b and 7; A is inverting and
B is non-inverting.
|tPHL - tPLH|; TA @ 25°C
RS-232 DRIVER (V.28)
TTL Input Levels
VIL
0.8
VIH
2.0
Volts
Volts
Outputs
HIGH Level Output
+5.0
+15.0
Volts
RL = 3kΩ, VIN = 0.8V
LOW Level Output
-15.0
-5.0
Volts
RL = 3kΩ, VIN = 2.0V
-15
+15
Volts
+/-100
mA
Open Circuit Voltage
Short Circuit Current
Power Off Impedance
300
Ω
Slew Rate
Transistion Time
VOUT = 0V
VCC = 0V, VOUT = +/-2.0V
30
V/µs
RL = 3kΩ, CL = 50pF; VCC = +5.0V,
TA @ 25°C
1.56
µs
RL = 3KΩ, CL = 2500pF; between
+/-3V, TA @ +25°C
Max. Transmission Rate
120
230.4
kbps
Propagation Delay tPHL
0.5
1
4
µs
Propagation Delay tPLH
0.5
1
4
µs
0.4
Volts
RL = 3kΩ, CL = 2500pF
TA @ 25°C and VCC = +5V only.
Measured from 1.5V of VIN to 50%
of VOUT; RL = 3kΩ
RS-232 RECEIVER (V.28)
TTL Output Levels
VOL
VOH
2.4
Volts
Input
HIGH Threshold
1.7
LOW Threshold
0.8
3.0
1.2
Volts
Reciever Open Circuit Bias
Input Impedance
Volts
+2.0
7
Volts
3
5
Max. Transmission Rate
120
230.4
kΩ
Propagation Delay tPHL
0.05
0.25
1
µs
Propagation Delay tPLH
0.05
0.25
1
µs
0.8
Volts
VIN = +15V to -15V
kbps
TA @ 25°C and VCC = +5V only.
Measured from 50% of VIN to 1.5V
of VOUT
RS-423 DRIVER (V.10)
TTL Input Levels
VIL
VIH
2.0
Volts
Outputs
Open Circuit Voltage, VO
+/-4.0
+/-6.0
Volts
RL = 3.9kΩ
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
SP504_102_121708
SPECIFICATIONS
TA = +25°C and VCC = +5.0V unless otherwise noted.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
+3.6
+6.0
Volts
RL = 450Ω; VOUT ≥0.9VOC
-6.0
-3.6
Volts
RL = 450Ω; VOUT ≥0.9VOC
Volts
TA = +25°C, VCC = +5.0V
RS-423 DRIVER (V.10) (continued)
HIGH Level Output, VT
LOW Level Output, VT
0.9VOC
Short Circuit Current
+/-150
mA
VOUT = 0V, VCC = +5.0V
Power Off Current
+/-100
µA
VCC = 0V, VOUT = +/-0.25V
ns
Rise/Fall time, between +/-3V
Transition Time
100
Max. Transmission Rate
120
kbps
Propagation Delay tPHL
0.05
0.5
2
µs
Propagation Delay tPLH
0.05
0.5
2
µs
0.4
Volts
RL = 450Ω
TA @ 25°C and VCC = +5V only.
Measured from 1.5V of VIN to 50%
of VOUT; RL = 450Ω
RS-423 RECEIVER (V.10)
TTL Output Levels
VOL
VOH
2.4
Volts
Input
HIGH Threshold
+0.3
+7.0
Volts
LOW Threshold
-7.0
-0.3
Volts
HIGH Input Current
Refer to Receiver input graph
LOW Input Current
Refer to Receiver input graph
Receiver Sensitivity
+/-0.3
Input Impedance
4
Volts
VCM = +7V to -7V
kΩ
VIN = +10V to -10V
Max. Transmission Rate
120
Propagation Delay tPHL
0.05
0.2
1
kbps
µs
Propagation Delay tPLH
0.05
0.2
1
µs
4.75
5.00
5.25
Volts
TA @ 25°C and VCC = +5V only
Measured from 50% of VIN to 1.5V
of VOUT
POWER REQUIREMENTS
VCC
ICC (No Mode Selected)
30
mA
All ICC values are with VCC = +5V
ICC (RS-232 Mode)
140
mA
fIN = 120kbps; Drivers loaded
ICC (RS-422 Mode)
320
mA
fIN = 2Mbps; Drivers loaded
ICC (RS-449 Mode)
320
mA
fIN = 2Mbps; Drivers loaded
ICC (EIA-530 Mode)
320
mA
fIN = 2Mbps Drivers loaded
ICC (EIA-530A Mode)
320
mA
fIN = 2Mbps Drivers loaded
ICC (RS-485 Mode)
370
mA
fIN = 2Mbps Drivers loaded
ICC (V.35 Mode)
210
mA
fIN = 2Mbps Drivers loaded
ICC (V.36 Mode)
310
mA
fIN = 2Mbps Drivers loaded
ENVIRONMENTAL AND MECHANICAL
Operating Temperature Range
Storage Temperature Range
ESD
0
-65
500
+70
°C
+150
°C
V
HBM
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
SP504_102_121708
RECEIVER INPUT GRAPHS
RS-423 RECEIVER
RS-422 RECEIVER
+3.25mA
+3.25mA
-10V
-10V
-3V
+3V
-3V
+3V
+10V
+10V
Maximum Input Current
Versus Voltage
Maximum Input Current
Versus Voltage
-3.25mA
-3.25mA
RS-485 RECEIVER
+1.0mA
-7V
-3V
+6V
+12V
1 Unit Load
Maximum Input Current
Versus Voltage
-0.6mA
OTHER AC CHARACTERISTICS
TA = +70°C to 0°C and VCC = +4.75V to +5.25V unless otherwise noted.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE
RS-232 Mode
tPZL; Tri-state to Output LOW
0.70
5.0
µs
CL = 100pF, Fig. 4 ; S1 closed
tPZH; Tri-state to Output HIGH
0.40
2.0
µs
CL = 100pF, Fig. 4 ; S2 closed
tPLZ; Output LOW to Tri-state
0.20
2.0
µs
CL = 100pF, Fig. 4 ; S1 closed
tPHZ; Output HIGH to Tri-state
0.40
2.0
µs
CL = 100pF, Fig. 4 ; S2 closed
tPZL; Tri-state to Output LOW
0.15
2.0
µs
CL = 100pF, Fig. 4 ; S1 closed
tPZH; Tri-state to Output HIGH
0.20
2.0
µs
CL = 100pF, Fig. 4 ; S2 closed
tPLZ; Output LOW to Tri-state
0.20
2.0
µs
CL = 100pF, Fig. 4 ; S1 closed
tPHZ; Output HIGH to Tri-state
0.15
2.0
µs
CL = 100pF, Fig. 4 ; S2 closed
tPZL; Tri-state to Output LOW
2.80
10.0
µs
CL = 100pF, Fig. 4 & 6; S1 closed
tPZH; Tri-state to Output HIGH
0.10
2.0
µs
CL = 100pF, Fig. 4 & 6; S2 closed
tPLZ; Output LOW to Tri-state
0.10
2.0
µs
CL = 15pF, Fig. 4 & 6; S1 closed
tPHZ; Output HIGH to Tri-state
0.10
2.0
µs
CL = 15pF, Fig. 4 & 6; S2 closed
tPZL; Tri-state to Output LOW
2.60
10.0
µs
CL = 100pF, Fig. 4 & 6; S1 closed
tPZH; Tri-state to Output HIGH
0.10
2.0
µs
CL = 100pF, Fig. 4 & 6; S2 closed
tPLZ; Output LOW to Tri-state
0.10
2.0
µs
CL = 15pF, Fig. 4 & 6; S1 closed
tPHZ; Output HIGH to Tri-state
0.15
2.0
µs
CL = 15pF, Fig. 4 & 6; S2 closed
RS-423 MODE
RS-422, RS-485 MODES
V.35 MODE
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
SP504_102_121708
OTHER AC CHARACTERISTICS
TA = +70°C to 0°C and VCC = +4.75V to +5.25V unless otherwise noted.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE
RS-232 Mode
tPZL; Tri-state to Output LOW
0.12
2.0
µs
CL = 100pF, Fig. 2 ; S1 closed
tPZH; Tri-state to Output HIGH
0.10
2.0
µs
CL = 100pF, Fig. 2 ; S2 closed
tPLZ; Output LOW to Tri-state
0.10
2.0
µs
CL = 100pF, Fig. 2 ; S1 closed
tPHZ; Output HIGH to Tri-state
0.10
2.0
µs
CL = 100pF, Fig. 2 ; S2 closed
tPZL; Tri-state to Output LOW
0.10
2.0
µs
CL = 100pF, Fig. 2 ; S1 closed
tPZH; Tri-state to Output HIGH
0.10
2.0
µs
CL = 100pF, Fig. 2 ; S2 closed
tPLZ; Output LOW to Tri-state
0.10
2.0
µs
CL = 100pF, Fig. 2 ; S1 closed
tPHZ; Output HIGH to Tri-state
0.10
2.0
µs
CL = 100pF, Fig. 2 ; S2 closed
tPZL; Tri-state to Output LOW
0.10
2.0
µs
CL = 100pF, Fig. 2 & 8; S1 closed
tPZH; Tri-state to Output HIGH
0.10
2.0
µs
CL = 100pF, Fig. 2 & 8; S2 closed
tPLZ; Output LOW to Tri-state
0.10
2.0
µs
CL = 15pF, Fig. 2 & 8; S1 closed
tPHZ; Output HIGH to Tri-state
0.10
2.0
µs
CL = 15pF, Fig. 2 & 8; S2 closed
tPZL; Tri-state to Output LOW
0.10
2.0
µs
CL = 100pF, Fig. 2 & 8; S1 closed
tPZH; Tri-state to Output HIGH
0.10
2.0
µs
CL = 100pF, Fig. 2 & 8; S2 closed
tPLZ; Output LOW to Tri-state
0.10
2.0
µs
CL = 15pF, Fig. 2 & 8; S1 closed
tPHZ; Output HIGH to Tri-state
0.10
2.0
µs
CL = 15pF, Fig. 2 & 8; S2 closed
TRANSCEIVER TO TRANSCEIVER SKEW
[(tPHL-tPLH)Trcvr1 - (tPHL - tPLH)TRCVRX]
RS-423 MODE
RS-422, RS-485 MODES
V.35 MODE
RS-232 Driver
20
50
ns
VCC = +5.0V, TA @ 25ºC
RS-232 Receiver
20
50
ns
VCC = +5.0V, TA @ 25ºC
RS-422 Driver
20
50
ns
VCC = +5.0V, TA @ 25ºC
RS-422 Receiver
20
50
ns
VCC = +5.0V, TA @ 25ºC
RS-423 Driver
20
50
ns
VCC = +5.0V, TA @ 25ºC
RS-423 Receiver
20
50
ns
VCC = +5.0V, TA @ 25ºC
V.35 Driver
20
50
ns
VCC = +5.0V, TA @ 25ºC
V.35 Receiver
20
50
ns
VCC = +5.0V, TA @ 25ºC
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
SP504_102_121708
A
VOD
1KΩ
VOC
S2
B
Figure 1. Driver DC Test Load Circuit
DI
A
B
CL1
RL
CL2
A
B
Figure 2. Receiver Timing Test Load Circuit
DI
RO
Output
Under
Test
A
A
B
B
RO
15pF
15pF
Figure 3a. Driver / Receiver Timing Test Circuit
500Ω
VCC
S1
CRL
R
1KΩ
Test Point
Receiver
Output
R
S1
Figure 3b.Timing Test Circuit (V.35 Mode only)
VCC
CL
S2
Figure 4.Driver Timing Test Load #2 Circuit
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
SP504_102_121708
DRIVER INPUT
f = 1MHz; TR ≤ 10ns; TF ≤ 10nS
+3V
A
DRIVER
OUTPUT
1.5V
0V
B
1.5V
t PLH
t PHL
VO 1/2VO
1/2VO
DIFFERENTIAL VO+
0V
OUTPUT
VO–
VA - VB
t SKEW
t SKEW
tF
tR
Figure 5. Driver Propagation Delays
TDECx
A, B
A, B
f = 1MHz; t R < 10ns; t F < 10ns
+3V
1.5V
0V
1.5V
t ZL
5V
2.3V
VOL
VOH
2.3V
0V
t LZ
Output normally LOW
0.5V
Output normally HIGH
0.5V
t ZH
t HZ
Figure 6. Driver Enable and Disable Times
A– B
f = 1MHz; t R ≤ 10ns ; t F ≤ 10ns
VOD2 +
0V
VOD2 –
VOH
RECEIVER OUT
VOL
0V
INPUT
1.5V
1.5V
OUTPUT
t PHL
t PLH
Figure 7. Receiver Propagation Delays
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10
SP504_102_121708
RDECx
+3V
RECEIVER OUT
0V
1.5V f = 1MHz; t ≤ 10ns; t ≤ 10ns
R
F
t ZL
5V
VIL
1.5V
VIH
RECEIVER OUT
0V
1.5V
t ZH
1.5V
DRIVER INPUT
t LZ
Output normally LOW
0.5V
Output normally HIGH
0.5V
t HZ
DRIVER OUTPUT
Figure 8. Receiver Enable and Disable Times
Figure 9. Typical RS-232 Driver Output Waveform
DRIVER INPUT
DRIVER INPUT
DRIVER OUTPUT
DRIVER OUTPUT
Figure 10. Typical RS-423 Driver Output Waveform
Figure 11. Typical RS-422/RS-485 Driver Output
Waveform
V.35 Driver VOD over Temperature
DRIVER INPUT
0.825
0.66
VOD+
0.495
V.35 VOD
0.33
DRIVER OUTPUT
0.65
0
-0.65
-0.33
-0.495
VOD-
-0.66
Vcc = 5.0V
-0.825
0
0
20
30
40
50
60
70
Temperature (deg C)
Figure 12. Typical V.35 Driver Output Waveform
Figure 13. V.35 Driver Output VOD VS. Temperature
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11
SP504_102_121708
Pin 63 — TT(a) — Analog Out — Terminal
Timing, inverted; sourced from TxC
61 SD(a)
62 VCC
63 TT(a)
64 GND
65 TT(b)
66 CS(a)
67 CS(b)
69 DM(b)
70 RD(a)
68 DM(a)
71 RD(b)
72 GND
73 VCC
74 VCC
75 GND
76 SCT(a)
77 SCT(b)
78 DSR
Pin 61 — SD(a) — Analog Out — Send
data, inverted; sourced from TxD.
79 SCT
80 CTS
PINOUT…
RxD 1
Pin 65 — TT(b) — Analog Out — Terminal
Timing, non–inverted; sourced from TxC.
60 GND
RDEC0 2
59 SD(b)
RDEC1 3
58 TR(a)
RDEC2 4
57 GND
RDEC3 5
56 TR(b)
TTEN 6
55 VCC
SCTEN 7
Pin 70 — RD(a) — Receive Data, analog
input; inverted; source for RxD.
54 RS(a)
N/C 8
53 GND
SP504
TDEC3 9
TDEC2 10
TDEC1 11
Pin 71 — RD(b) — Receive Data; analog
input; non-inverted; source for RxD.
52 RS(b)
51 LL(a)
50 GND
TDEC0 12
49 LL(b)
Pin 76 — SCT(a) — Serial Clock Transmit;
analog input, inverted; source for SCT.
Pin 77 — SCT(b) — Serial Clock Transmit:
analog input, non–inverted; source for
SCT
IC(b) 40
IC(a) 39
RT(b) 38
RT(a) 37
RR(b) 36
RR(a) 35
GND 34
VCC 33
C2- 31
C2+ 28
VSS 32
41 VCC
C1- 30
42 ST(a)
RxC 20
GND 29
43 GND
DCD 19
V DD 27
V35_STAT 18
C1+ 26
44 ST(b)
VCC 25
45 RL(b)
RL 17
LL 24
46 GND
RTS 16
RI 21
47 RL(a)
TxC 15
ST 22
48 VCC
TxD 14
STEN 23
DTR 13
Pin 79 — SCT — Serial Clock Transmit; TTL
output; sources from SCT(a) and SCT(b)
inputs.
PIN ASSIGNMENTS…
CLOCK AND DATA GROUP
Pin 1 — RxD — Receive Data; TTL output,
sourced from RD(a) and RD(b) inputs.
CONTROL LINE GROUP
Pin 13 — DTR — Data Terminal Ready; TTL
input; source for TR(a) and TR(b) outputs.
Pin 14 — TxD — TTL input ; transmit data
source for SD(a) and SD(b) outputs.
Pin 16 — RTS — Ready To Send; TTL input;
source for RS(a) and RS(b) outputs.
Pin 15 — TxC — Transmit Clock; TTL input
for TT driver outputs.
Pin 17 — RL — Remote Loopback; TTL input;
source for RL(a) and RL(b) outputs.
Pin 20 — RxC — Receive Clock; TTL output
sourced from RT(a) and RT(b) inputs.
Pin 18 — V35_STAT — V.35 Status; TTL
output; outputs logic high when in V.35
mode.
Pin 22 — ST — Send Timing; TTL input;
source for ST(a) and ST(b) outputs.
Pin 37 — RT(a) — Receive Timing; analog
input, inverted; source for RxC.
Pin 19 — DCD— Data Carrier Detect; TTL
output; sourced from RR(a) and RR(b)
inputs.
Pin 38 — RT(b) — Receive Timing; analog
input, non-inverted; source for RxC.
Pin 21 — RI — Ring Indicate; TTL output;
sourced from IC(a) and IC(b) inputs.
Pin 42 — ST(a) — Send Timing; analog
output, inverted; sourced from ST.
Pin 24 — LL — Local Loopback; TTL input;
source for LL(a) and LL(b) outputs.
Pin 44 — ST(b) — Send Timing; analog
output, non-inverted; sourced from ST.
Pin 35 — RR(a)— Receiver Ready; analog
input, inverted; source for DCD.
Pin 59 — SD(b) — Analog Out — Send data,
non-inverted; sourced from TxD.
Pin 36 — RR(b)— Receiver Ready; analog
input, non-inverted; source for DCD.
Pin 39 — IC(a)— Incoming Call; analog
input, inverted; source for RI.
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12
SP504_102_121708
Pins 12–9 — TDEC0 – TDEC3 — Transmitter decode register; configures transmitter
modes; TTL inputs.
Pin 40 — IC(b)— Incoming Call; analog
input,non-inverted; source for RI.
Pin 45 — RL(b) — Remote Loopback; analog
output, non-inverted; sourced from RL.
Pin 23 — STEN — Enables ST driver; active
low; TTL input.
Pin 47 — RL(a) — Remote Loopback; analog
output inverted; sourced from RL.
POWER SUPPLIES
Pins 25, 33, 41, 48, 55, 62, 73, 74 — VCC
— +5V input.
Pin 49— LL(b) — Local Loopback; analog
output, non-inverted; sourced from LL.
Pin 51 — LL(a) — Local Loopback; analog
output, inverted; sourced from LL.
Pins 29, 34, 43, 46, 50, 53, 57, 60, 64, 72,
75 — GND — Ground.
Pin 52 — RS(b) — Ready To Send; analog
output, non-inverted; sourced from RTS.
Pin 27 — VDD +10V Charge Pump Capacitor
— Connects from VDD to VCC. Suggested
capacitor size is 22µF, 16V.
Pin 54 — RS(a) — Ready To Send; analog
output, inverted; sourced from RTS.
Pin 32 — VSS –10V Charge Pump Capacitor
— Connects from ground to VSS. Suggested
capacitor size is 22µF, 16V.
Pin 56 — TR(b) — Terminal Ready; analog
output, non-inverted; sourced from DTR.
Pin 58 — TR(a) — Terminal Ready; analog
output, inverted; sourced from DTR.
Pins 26 and 30 — C1+ and C1– — Charge
Pump Capacitor — Connects from C1+ to C1–.
Suggested capacitor size is 22µF, 16V.
Pin 66 — CS(a)— Clear To Send; analog
input, inverted; source for CTS.
Pins 28 and 31 — C2+ and C2– — Charge
Pump Capacitor — Connects from C2+ to C2–.
Suggested capacitor size is 22µF, 16V.
Pin 67 — CS(b)— Clear To Send; analog
input, non-inverted; source for CTS.
Pin 68 — DM(a)— Data Mode; analog input,
inverted; source for DSR.
NOTE: NC pins should be left floating; internal signals may be present.
Pin 69 — DM(b)— Data Mode; analog input,
non-inverted; source for DSR
Pin 78 — DSR— Data Set Ready; TTL output;
sourced from DM(a), DM(b) inputs.
Pin 80 — CTS— Clear To Send; TTL output;
sourced from CS(a) and CS(b) inputs.
CONTROL REGISTERS
Pins 2–5 — RDEC0 – RDEC3 — Receiver
decode register; configures receiver modes;
TTL inputs.
Pin 6 — TTEN — Enables TT driver, active
low; TTL input.
Pin 7 — SCTEN — Enables SCT receiver;
active high; TTL input.
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13
SP504_102_121708
FEATURES…
The SP504 is a highly integrated serial transceiver that allows software control of its interface modes. Similar to the SP503, the SP504
offers the same hardware interface modes
for RS-232 (V.28), RS-422A (V.11), RS-449,
RS-485, V.35, EIA-530 and includes V.36 and
EIA-530A. The interface mode selection is done via an 8–bit switch; four
(4) bits control the drivers and four (4)
bits control the receivers. The SP504
is fabricated using low power BiCMOS
process technology, and incorporates a
Exar patented (5,306,954) charge pump
allowing +5V only operation. Each device
is packaged in an 80–pin JEDEC Quad
FlatPack package.
The SP504 charge pump is used for RS-232
where the output voltage swing is typically
±10V and also used for RS-423. However,
RS-423 requires the voltage swing on the
driver output be between ±4V to ±6V during
an open circuit (no load). The charge pump
would need to be regulated down from ±10V
to ±5V. A typical ±10V charge pump would
require external clamping such as 5V zener
diodes on VDD and VSS to ground. The ±5V
output has symmetrical levels as in the ±10V
output. The ±5V is used in the following
modes where RS-423 levels are used: RS449, EIA-530, EIA-530A and V.36.
Phase 1 (±10V)
— VSS charge storage — During this phase
of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to +5V.
The Cl+ is then switched to ground and the
charge on C1– is transferred to C2–. Since C2+
is connected to +5V, the voltage potential
across capacitor C2 is now 10V.
The SP504 is ideally suited for wide area
network connectivity based on the interface
modes offered and the driver and receiver
configurations. The SP504 has seven (7)
independent drivers and seven (7) independent receivers. In V.35 mode, the SP504
includes the necessary components and
termination resistors internal within the device for compliant V.35 operation.
Phase 1 (±5V)
— VSS & VDD charge storage and transfer
— With the C1 and C2 capacitors initially
charged to +5V, Cl+ is then switched to
ground and the charge on C1– is transferred
to the VSS storage capacitor. Simultaneously the C2– is switched to ground and the
5V charge on C2+ is transferred to the VDD
storage capacitor.
Theory of Operation
The SP504 is made up of five separate
circuit blocks — the charge pump, drivers,
receivers, decoder and switching array. Each
of these circuit blocks is described in more
detail below.
VCC = +5V
Charge–Pump
The SP504's charge pump design is based
on the SP503 where Exar's patented charge
pump design (5,306,954) uses a four–phase
voltage shifting technique to attain symmetrical ±10V power supplies. In addition,
the SP504 charge pump incorporates a
"programmable" feature that produces
an output of ±10V or ±5V for VSS and VDD
depending on the mode of operation. The
charge pump still requires external capacitors to store the charge. Figure 18a shows
the waveform found on the positive side of
capacitor C2, and Figure 18b shows the
negative side of capcitor C2. There is a
free–running oscillator that controls the four
phases of the voltage shifting. A description
of each phase follows.
+5V
C1
+
C2
–
+
C4
+
–
VDD Storage Capacitor
+
VSS Storage Capacitor
–
–5V
–
C3
–5V
Figure 14a. Charge Pump Phase 1 for ±10V.
VCC = +5V
+5V
C1
+
–
C2
+
C4
+
–
VDD Storage Capacitor
+
VSS Storage Capacitor
–
–5V
–
C3
Figure 14b. Charge Pump Phase 1 for ±5V.
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SP504_102_121708
VCC = +5V
VCC = +5V
C4
C1
+
C2
–
+
+
C4
–
VDD Storage Capacitor
C1
–
–10V
+
–
+
–
C2
+
–
Figure 15a. Charge Pump Phase 2 for ±10V.
VSS Storage Capacitor
VCC = +5V
+5V
–
+
Figure 15b. Charge Pump Phase 2 for ±5V.
VCC = +5V
C1
VDD Storage Capacitor
C3
C3
+
–
–
–5V
VSS Storage Capacitor
+
C2
+
C4
+
–
+10V
VDD Storage Capacitor
C1
–
–5V
–
–5V
+
+
–
C2
+
C4
+
–
VDD Storage Capacitor
+
VSS Storage Capacitor
–
–
VSS Storage Capacitor
C3
C3
Figure 16. Charge Pump Phase 3.
Figure 17. Charge Pump Phase 4.
Phase 2 (±10V)
— VSS transfer — Phase two of the clock
connects the negative terminal of C2 to
the VSS storage capacitor and the positive
terminal of C2 to ground, and transfers the
generated –l0V or the generated –5V to C3.
Simultaneously, the positive side of capacitor
C 1 is switched to +5V and the negative side
is connected to ground.
transferred to the VSS storage capacitor. VSS
receives a continuous charge from either C1
or C2. With the C1 capacitor charged to 5V,
the cycle begins again.
Phase 3
— VDD charge storage — The third phase
of the clock is identical to the first phase
— the charge transferred in C1 produces
–5V in the negative terminal of C1, which
is applied to the negative side of capacitor
C2. Since C2+ is at +5V, the voltage potential
across C2 is l0V. For the 5V output, C2+ is
connected to ground so that the potential
on C2 is only +5V.
Phase 2 (±5V)
— VSS & VDD charge storage — C1+ is reconnected to VCC to recharge the C1 capacitor.
C2+ is switched to ground and C2– is connected
to C3. The 5V charge from Phase 1 is now
(a)
+5V
C 2+
GND
(b)
GND
C 2–
–5V
+10V
C 2+
GND
GND
C2
–
–10V
Figure 18a and 18b. Charge Pump Waveforms
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SP504_102_121708
Since both VDD and VSS are separately generated from VCC in a no–load condition, VDD
and VSS will be symmetrical. Older charge
pump approaches that generate V– from
V+ will show a decrease in the magnitude
of V– compared to V+ due to the inherent
inefficiencies in the design.
The RS-232 drivers are used in RS232 mode for all signals, and also in
V.35 mode where they are used as
the control line signals such as DTR
and RTS.
The RS-423 drivers are also single–ended
signals with a minimum voltage output of
±3.6V (with 450Ω loading) and can operate
up to 120kbps. Open circuit VOL and VOH
measurements are ±4.0V to ±6.0V. The RS423 drivers are used in RS-449, EIA-530,
EIA-530A and V.36 modes as Category II
signals from each of their corresponding
specifications.
The clock rate for the charge pump typically
operates at 15kHz. The external capacitors
must be a minimum of 22µF with a 16V
breakdown rating.
External Power Supplies
For applications that do not require +5V only,
external supplies can be applied at the V+ and
V– pins. The value of the external supply voltages must be no greater than ±l0.5V. The tolerance should be ±5% from ±10V. The current
drain for the supplies is used for RS-232 and
RS-423 drivers. For the RS-232 driver,
the current requirement will be 3.5mA per
driver. The RS-423 driver worst case current drain will be 11mA per driver. Power
sequencing is required for the SP504. The
supplies must be sequenced accordingly:
+10V, +5V and –10V. An external circuit
would be needed for proper power supply
sequencing. Consult factory for application
circuitry.
The third type of driver produces a differential
signal that can maintain RS-485, ±1.5V differential output levels with a worst case load
of 54Ω. The signal levels and drive capability
of the RS-485 drivers allow the drivers to
also support RS-422 (V.11) requirements
of ±2V differential output levels with 100Ω
loads. The RS-422 drivers are used in RS449, EIA-530, EIA-530A and V.36 modes as
Category I signals which are used for clock
and data.
The fourth type of driver is the V.35 driver.
V.35 levels require ±0.55V driver output signals with a load of 100Ω. The SP504 drivers
simplify existing V.35 implementations that
use external termination schemes. The
drivers were specifically designed to comply
with the requirements of V.35 as well as the
driver output impedance values of V.35. The
drivers achieve the 50Ω to 150Ω source
impedance. However, an external 150Ω
resistor to ground must be connected to
the non-inverting outputs; SD(b), ST(b), and
TT(b), in order to comply with the 135Ω to
165Ω short-circuit impedance for V.35. The
V.35 driver itself is disabled and transparent
when the decoder is in all other modes. All
of the differential drivers; RS-485, RS-422,
and V.35, can operate up to 10Mbps.
Drivers
The SP504 has seven (7) enhanced independent drivers. Control for the mode
selection is done via a four–bit control word.
The drivers are pre-arranged such that for
each mode of operation, the relative position and functionality of the drivers are set
up to accommodate the selected interface
mode. As the mode of the drivers is changed,
the electrical characteristics will change to
support the requirements of clock, data, and
control line signal levels. Table 1 shows the
mode of each driver in the different interface
modes that can be selected.
There are four basic types of driver circuits
— RS-232, RS-423, RS-485 and V.35.
The driver inputs are both TTL or CMOS
compatible. Since there are no pull-up or
pull-down resistors on the driver inputs, they
should be tied to a known logic state in order
to define the driver output.
The RS-232 drivers output single–ended
signals with a minimum of ±5V (with 3kΩ
and 2500pF loading), and can operate up
to 120kbps.
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16
SP504_102_121708
Receivers
The SP504 has seven (7) independent receivers which can be programmed for the
different interface modes. Control for the
mode selection is done via a 4–bit control
word that is independent from the driver
control word. The coding for the drivers and
receivers is identical. Therefore, if the modes
for the drivers and receivers are supposed
to be identical in the application, the control
lines can be tied together.
receivers.
RS-422 receivers are used in RS-449,
EIA-530, EIA-530A and V.36 as Category I
signals for receiving clock, data, and some
control line signals. The differential receivers
can receive data up to 10Mbps.
The RS-485 receivers are also used for the
V.35 mode. Unlike the older implementations
of differential or V.35 receivers, the SP504
contains an internal resistor termination network that ensures a V.35 input impedance of
100Ω (±10Ω) and a short-circuit impedance
of 150Ω (±15Ω). The traditional V.35 implementations required external termination
resistors to acheive the proper V.35 impedances. The internal network is connected
via low on-resistance FET switches when
the decoder is changed to V.35 mode. The
termination network is transparent when all
other modes are selected. The V.35 receivers can operate up to 10Mbps.
Like the drivers, the receivers are pre-arranged for the specific requirements of
the interface. As the operating mode of
the receivers is changed, the electrical
characteristics will change to support the
requirements of clock, data, and control line
receivers. Table 2 shows the mode of each
receiver in the different interface modes that
can be selected.
There are three basic types of receiver circuits — RS-232, RS-423, and RS-485.
All receivers include a fail-safe feature that
outputs a logic HIGH when the receiver
inputs are open. For single-ended RS-232
receivers, there are internal 5kΩ pull-down
resistors on the inputs which produces a
logic HIGH ("1") at the receiver outputs. The
single-ended RS-423 receivers produce a
logic LOW ("0") on the output when the inputs
are open. This is due to a pull-up device
connected to the input. The differential receivers have the same internal pull-up device
on the non-inverting input which produces a
logic HIGH ("1") at the receiver output. The
three differential receivers when configured
in V.35 mode (RxD, RxC & SCT) do not have
fail-safe because the internal termination
resistor network is connected.
The RS-232 receiver is a single–ended
input with a threshold of 0.8V to 2.4V. The
RS-232 receiver has an operating voltage
range of ±15V and can receive signals up
to 120kbps. The input sensitivity complies
with EIA-RS-232 and V.28 at +3V to -3V.
The input impedance is 3kΩ to 7kΩ. RS232 receivers are used in RS-232 mode for
all data, clock and control signals. They
are also used in V.35 mode for control line
signals such as CTS and DSR.
The RS-423 receivers are also single–ended
but have an input threshold as low as
±200mV. The input impedance is guaranteed
to be greater than 4kΩ, with an operating voltage range of ±7V. The RS-423 receivers can
operate up to 120kbps. RS-423 receivers are
used in RS-449, EIA-530, EIA-530A and V.36
modes as Category II signals as indicated
by their corresponding specifications.
Decoder
The SP504 has the ability to change the
interface mode of the drivers or receivers via
an 8–bit switch. The decoder for the drivers
and receivers is not latched; it is merely a
combinational logic switch.
The third type of receiver is a differential which
supports RS-485. The RS-485 receiver has
an input impedance of 15kΩ and a differential
threshold of ±200mV. Since the characteristics of an RS-422 (V.11) receiver are actually
subsets of RS-485, the receivers for RS-422
requirements are covered by the RS-485
The control word can be externally latched
either HIGH or LOW to write the appropriate
code into the SP504. The codes shown in
Tables 1 and 2 are the only specified, valid
modes for the SP504. Undefined codes
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17
SP504_102_121708
may represent other interface modes not
specified (consult the factory for more information). The drivers are controlled with
the data bits labeled TDEC3–TDEC0. All of
the drivers can be put into tri-state mode
by writing 0000 to the driver decode switch.
The three drivers TxD, ST and TxC, have a
150Ω pull-down resistor to ground connected
at the (b) output. This resistor is part of the
V.35 driver circuitry and should be connected
when in V.35 mode. Tri-state is possible for
all drivers in RS-232 mode. The receivers
are controlled with data bits RDEC3–RDEC0;
the code 0000 written to the receivers will
place the outputs into tri-state mode. The
0000 decoder word will override the enable
control line for the one receiver (SCT).
Using the V.35_STAT Pin
The SP504 includes a V.35 status pin where
the V35_STAT pin (pin 18) is a logic HIGH
("1") when the decoder is set to V.35 mode.
The pin is a logic LOW ("0") when in all other
modes including tri-state (decoder set at
"0000"). Pin 18 allows the user to easily
add FET switches or solid state relays to
connect the external 150Ω resistor for V.35
operation. V35_STAT can be connected to
the gate of the FET switches or the control
of the relays so that the 150Ω resistors are
connected to the non-inverting output of the
three V.35 drivers. The output current of the
V35_STAT pin is that of a typical TTL load
of –3.2mA. The electrical specifications
are similar to the SP504 receiver outputs.
This feature would reduce additional logic
required by older traditional methods.
NET1/NET2 Testing and Compliancy
Many system designers are required to certify
their system for use in the European public
network. Electrical testing is performed in
adherence to the NET (Norme Européenne
de Télécommunication) which specifies the
ITU Series V specifications. The SP504
adheres to all the required physical layer
testing for NET1 and NET2. Consult factory
for details.
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18
SP504_102_121708
SP504 Driver Mode Selection
Pin Label
Mode:
RS232
V.35
RS422
RS485
RS449
EIA530
EIA-530A
TDEC3 - TDEC0
0000
0010
1110
0100
0101
1100
1101
1111
0110
SD(a)
tri-state
V.28
V.35–
V.11–
RS485–
V.11–
V.11–
V.11–
V.11–
SD(b)
tri-state
tri-state
V.35+
V.11+
RS485+
V.11+
V.11+
V.11+
V.11+
TR(a)
tri-state
V.28
V.28
V.11–
RS485–
V.11–
V.11–
V.10
V.10
TR(b)
tri-state
tri-state
tri-state
V.11+
RS485+
V.11+
V.11+
tri-state
tri-state
RS(a)
tri-state
V.28
V.28
V.11–
RS485–
V.11–
V.11–
V.11–
V.10
RS(b)
tri-state
tri-state
tri-state
V.11+
RS485+
V.11+
V.11+
V.11+
tri-state
RL(a)
tri-state
V.28
V.28
V.11–
RS485–
V.10
V.10
V.11–
V.10
RL(b)
tri-state
tri-state
tri-state
V.11+
RS485+
tri-state
tri-state
V.11+
tri-state
LL(a)
tri-state
V.28
V.28
V.11–
RS485–
V.10
V.10
V.10
V.10
LL(b)
tri-state
tri-state
tri-state
V.11+
RS485+
tri-state
tri-state
tri-state
tri-state
ST(a)
tri-state
V.28
V.35–
V.11–
RS485–
V.11–
V.11–
V.11–
V.11–
ST(b)
tri-state
tri-state
V.35+
V.11+
RS485+
V.11+
V.11+
V.11+
V.11+
TT(a)
tri-state
V.28
V.35–
V.11–
RS485–
V.11–
V.11–
V.11–
V.11–
TT(b)
tri-state
tri-state
V.35+
V.11+
RS485+
V.11+
V.11+
V.11+
V.11+
V.36
Table 1. Driver Mode Selection
SP504 Receiver Mode Selection
Pin Label
Mode:
RS232
V.35
RS422
RS485
RS449
EIA530
EIA-530A
V.36
RDEC3 - RDEC0
0000
0010
1110
0100
0101
1100
1101
1111
0110
RD(a)
>12kΩ to GND
V.28
V.35–
V.11–
RS485–
V.11–
V.11–
V.11–
V.11–
RD(b)
>12kΩ to GND >12kΩ to GND
V.35+
V.11+
RS485+
V.11+
V.11+
V.11+
V.11+
RT(a)
>12kΩ to GND
V.35–
V.11–
RS485–
V.11–
V.11–
V.11–
V.11–
RT(b)
>12kΩ to GND >12kΩ to GND
V.35+
V.11+
RS485+
V.11+
V.11+
V.11+
V.11+
CS(a)
>12kΩ to GND
CS(b)
>12kΩ to GND >12kΩ to GND
DM(a)
>12kΩ to GND
DM(b)
>12kΩ to GND >12kΩ to GND
RR(a)
>12kΩ to GND
RR(b)
>12kΩ to GND >12kΩ to GND
IC(a)
>12kΩ to GND
IC(b)
>12kΩ to GND >12kΩ to GND
V.28
V.28
V.28
V.28
V.28
SCT(a)
>12kΩ to GND
SCT(b)
>12kΩ to GND >12kΩ to GND
V.28
V.28
>12kΩ to GND
V.11–
RS485–
V.11–
V.11–
V.11–
V.11+
RS485+
V.11+
V.11+
V.11+
V.10
>12kΩ to GND
V.10
V.11–
RS485–
V.11–
V.11–
V.10
V.11+
RS485+
V.11+
V.11+
>12kΩ to GND
V.28
V.11–
RS485–
V.11–
V.11–
V.11–
>12kΩ to GND
V.11+
RS485+
V.11+
V.11+
V.11+
V.28
V.11–
RS485–
>12kΩ to GND
V.11+
RS485+
V.35–
V.11–
RS485–
V.11–
V.11–
V.11–
V.11–
V.35+
V.11+
RS485+
V.11+
V.11+
V.11+
V.11+
V.28
>12kΩ to GND
V.10
>12kΩ to GND
>12kΩ to GND
V.10
>12kΩ to GND
V.10
V.10
V.10
>12kΩ to GND
>12kΩ to GND
>12kΩ to GND
Table 2. Receiver Mode Selection
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
19
SP504_102_121708
1N5819
22µF
22µF
+5V
25
10µF
VCC
22µF
31
27
26
VDD
C1+ C1- C2+
30 28
Charge Pump
14 TxD
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT (a) 37
13 DTR
16 RTS
54 RS(a)
CTS 80
52 RS(b)
CS(b) 67
17 RL
DM(a) 68
47 RL(a)
DSR 78
45 RL(b)
DM (b) 69
24 LL
RR(a) 35
51 LL(a)
DCD 19
49 LL(b)
A — Receiver Tri-State Circuitry & V.35
terminaiton resistor circuitry for
RR(b) 36
RxD, RxC & SCT
.
22 ST
IC(a) 39
42 ST(a)
RI 21
44 ST(b)
IC(b) 40
23 STEN
SCT(a) 76
Note 1
63 TT(a)
65 TT(b)
SCTEN 7
SCT(b) 77
150Ω
Note 1
X
RDEC
X
6 TTEN
TDEC
External
Latch
150Ω
15 TxC
SCT 79
0
1
0
0
0
1
0
0
Note 1
56 TR(b)
RT (b) 38
CS(a) 66
5
4
3
2
9
10
11
12
150Ω
58 TR(a)
RxC 20
RS-422 Mode
Input Word
22µF
32
B
A
RD(a) 70
B — Driver Tri-State circuitry & V.35
termination circuitry for TxD,
TxC & ST
.
C2VSS
SP504
(SEE PAGE 12 FOR GROUND PINS)
Note 1
For V.35 Termination, needs to be connected
for proper V.35 operation. A low onresistance (≤1Ω) FET or switch can be used
to connect and disconnect the resistor from
the non-inverting output.
Figure 19. SP504 Typical Operating Circuit
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20
SP504_102_121708
MODE: RS-232
DRIVER
RECEIVER
TDEC3 TDEC 2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC0
0
0
1
0
0
0
1
0
14 TxD
RD(a) 70
61 SD(a)
RxD 1
13 DTR
RT(a) 37
58 TR(a)
RxC 20
16 RTS
CS(a) 66
54 RS(a)
CTS 80
17 RL
DM(a) 68
47 RL(a)
DSR 78
24 LL
RR(a) 35
DCD 19
51 LL(a)
IC(a) 39
22 ST
RI 21
42 ST(a)
23 STEN
SCT(a) 76
15 TxC
SCT 79
63 TT(a)
SCTEN 7
6 TTEN
RECEIVERS
STEN
DRIVERS
1
ST
Disabled
TTEN
1
TT
Disabled
SCTEN
1
SCT
Enabled
0
Enabled
0
Enabled
0
Disabled
Figure 20. Mode Diagram — RS-232
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
21
SP504_102_121708
MODE: V.35
DRIVER
RECEIVER
TDEC 3 TDEC 2 TDEC 1 TDEC 0 RDEC 3 RDEC 2 RDEC 1 RDEC 0
1
1
1
0
1
1
1
0
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
RxC 20
16 RTS
RT(b) 38
CS(a) 66
54 RS(a)
CTS 80
17 RL
DM(a) 68
47 RL(a)
DSR 78
24 LL
RR(a) 35
51 LL(a)
DCD 19
22 ST
IC(a) 39
42 ST(a)
RI 21
44 ST(b)
23 STEN
SCT(a) 76
15 TxC
SCT 79
SCTEN 7
SCT(b) 77
STEN
1
0
63 TT(a)
65 TT(b)
RECEIVERS
ST
Disabled
Enabled
TTEN
1
0
DRIVERS
6 TTEN
TT
SCTEN
SCT
Disabled
1
Enabled
Enabled
0
Disabled
Figure 21. Mode Diagram — V.35
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
22
SP504_102_121708
MODE: RS-422
DRIVER
RECEIVER
TDEC 3 TDEC 2 TDEC 1 TDEC 0 RDEC 3 RDEC 2 RDEC 1 RDEC 0
0
1
0
0
0
1
0
0
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
RxC 20
55 TR(b)
16 RTS
RT(b) 38
CS(a) 66
54 RS(a)
52 RS(b)
CTS 80
17 RL
CS(b) 67
DM(a) 68
47 RL(a)
45 RL(b)
DSR 78
24 LL
51 LL(a)
DM(b) 69
RR(a) 35
DCD 19
49 LL(b)
22 ST
RR(b) 36
IC(a) 39
42 ST(a)
44 ST(b)
RI 21
23 STEN
IC(b) 40
SCT(a) 76
SCT 79
SCTEN 7
SCT(b) 77
STEN
1
0
15 TxC
63 TT(a)
65 TT(b)
RECEIVERS
DRIVERS
6 TTEN
ST
TT
SCTEN
TTEN
Disabled
1
Disabled
1
Enabled
0
Enabled
0
SCT
Enabled
Disabled
Figure 22. Mode Diagram — RS-422
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23
SP504_102_121708
MODE: RS-449
DRIVER
RECEIVER
TDEC 3 TDEC 2 TDEC 1 TDEC 0 RDEC 3 RDEC 2 RDEC 1 RDEC 0
1
1
0
0
1
1
0
0
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
RxC 20
55 TR(b)
16 RTS
RT(b) 38
CS(a) 66
54 RS(a)
52 RS(b)
CTS 80
17 RL
CS(b) 67
DM(a) 68
47 RL(a)
DSR 78
24 LL
DM(b) 69
RR(a) 35
DCD 19
51 LL(a)
22 ST
RR(b) 36
IC(a) 39
42 ST(a)
44 ST(b)
RI 21
23 STEN
SCT(a) 76
15 TxC
63 TT(a)
SCT 79
SCTEN 7
SCT(b) 77
STEN
1
0
65 TT(b)
RECEIVERS
DRIVERS
6 TTEN
ST
TT
SCTEN
TTEN
Disabled
1
Disabled
1
Enabled
0
Enabled
0
SCT
Enabled
Disabled
Figure 23. Mode Diagram — RS-449
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24
SP504_102_121708
MODE: RS-485
DRIVER
RECEIVER
TDEC 3 TDEC 2 TDEC 1 TDEC 0 RDEC 3 RDEC 2 RDEC 1 RDEC 0
0
1
0
1
0
1
0
1
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
RxC 20
55 TR(b)
16 RTS
RT(b) 38
CS(a) 66
54 RS(a)
52 RS(b)
CTS 80
17 RL
CS(b) 67
DM(a) 68
47 RL(a)
45 RL(b)
DSR 78
24 LL
51 LL(a)
DM(b) 69
RR(a) 35
DCD 19
49 LL(b)
22 ST
RR(b) 36
IC(a) 39
42 ST(a)
44 ST(b)
RI 21
23 STEN
IC(b) 40
SCT(a) 76
SCT 79
SCTEN 7
SCT(b) 77
STEN
1
0
15 TxC
63 TT(a)
65 TT(b)
RECEIVERS
DRIVERS
6 TTEN
ST
TT
SCTEN
TTEN
Disabled
1
Disabled
1
Enabled
0
Enabled
0
SCT
Enabled
Disabled
Figure 24. Mode Diagram — RS-485
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25
SP504_102_121708
MODE: EIA-530
DRIVER
RECEIVER
TDEC 3 TDEC 2 TDEC 1 TDEC 0 RDEC 3 RDEC 2 RDEC 1 RDEC 0
1
1
0
1
1
1
0
1
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
RxC 20
55 TR(b)
16 RTS
RT(b) 38
CS(a) 66
54 RS(a)
52 RS(b)
CTS 80
17 RL
CS(b) 67
DM(a) 68
47 RL(a)
DSR 78
24 LL
DM(b) 69
RR(a) 35
DCD 19
51 LL(a)
22 ST
RR(b) 36
IC(a) 39
42 ST(a)
44 ST(b)
RI 21
23 STEN
SCT(a) 76
15 TxC
63 TT(a)
SCT 79
SCTEN 7
SCT(b) 77
STEN
1
0
65 TT(b)
RECEIVERS
DRIVERS
6 TTEN
ST
TT
SCTEN
TTEN
Disabled
1
Disabled
1
Enabled
0
Enabled
0
SCT
Enabled
Disabled
Figure 25. Mode Diagram — EIA-530
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
26
SP504_102_121708
MODE: EIA-530A
DRIVER
RECEIVER
TDEC 3 TDEC 2 TDEC 1 TDEC 0 RDEC 3 RDEC 2 RDEC 1 RDEC 0
1
1
1
1
1
1
1
1
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
RxC 20
16 RTS
RT(b) 38
CS(a) 66
54 RS(a)
52 RS(b)
CTS 80
17 RL
CS(b) 67
DM(a) 68
47 RL(a)
45 RL(b)
DSR 78
24 LL
RR(a) 35
51 LL(a)
DCD 19
22 ST
RR(b) 36
IC(a) 39
42 ST(a)
44 ST(b)
RI 21
23 STEN
SCT(a) 76
15 TxC
63 TT(a)
SCT 79
SCTEN 7
SCT(b) 77
STEN
1
0
65 TT(b)
RECEIVERS
DRIVERS
6 TTEN
ST
TT
SCTEN
TTEN
Disabled
1
Disabled
1
Enabled
0
Enabled
0
SCT
Enabled
Disabled
Figure 26. Mode Diagram — EIA-530A
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
27
SP504_102_121708
MODE: V.36
DRIVER
RECEIVER
TDEC 3 TDEC 2 TDEC 1 TDEC 0 RDEC 3 RDEC 2 RDEC 1 RDEC 0
0
1
1
0
0
1
1
0
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
RxC 20
16 RTS
RT(b) 38
CS(a) 66
54 RS(a)
CTS 80
17 RL
DM(a) 68
47 RL(a)
DSR 78
24 LL
RR(a) 35
51 LL(a)
DCD 19
22 ST
IC(a) 39
42 ST(a)
RI 21
44 ST(b)
23 STEN
SCT(a) 76
15 TxC
SCT 79
SCTEN 7
SCT(b) 77
STEN
1
0
63 TT(a)
65 TT(b)
RECEIVERS
ST
Disabled
Enabled
DRIVERS
6 TTEN
TTEN
TT
SCTEN
SCT
1
Disabled
1
Enabled
0
Enabled
0
Disabled
Figure 27. Mode Diagram — V.36
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28
SP504_102_121708
Additional transceivers
with the SP504
Serial ports usually can have two data signals (SD, RD), three clock signals (TT, ST,
RT), and at least eight control signals (CS,
RS, etc.). EIA-RS-449 contains twenty six
signal types for a DB-37 connector. A DB37 serial port design may require thirteen
drivers and fourteen receivers1. Although
many applications do not use all these
signals, some applications may need to
support extra functions such as diagnostics.
The SP504 supports enough transceivers
for the primary channels of data, clock and
control signals. Configuring LL, RL and TM
would require two additional drivers and one
receiver if designing for a DTE (one driver
and two receivers for a DCE).
the receiver is used for the TM signal. This
configuration was selected because the two
RS-232 drivers can be used for RS-423 by
connecting a zener clamping diode to ground
on the two driver outputs. The diodes will
limit the voltage swing on the outputs so that
the VOC = ±4V to ±6V adheres to the RS-423
specification. The differential receiver can
be easily configured to RS-423 by grounding the non-inverting input. The receiver will
adhere to the RS-423 specifications.
A programmable transceiver such as the
SP332 is a convenient solution in a design
that requires extra single ended or differential
drivers/receivers. As shown in Figure 28, the
SP332 can be configured to four different
variations.
The SP332 in Figure 29 is configured for two
single-ended drivers and one diffferential
receiver. For a DTE design, the two drivers
are used for LL and RL signals and
1
SG
SC
RC
IS
IC
TR
DM
SD
RD
TT
ST
RT
RS
CS
RR
SQ
NS
SF
SR
SI
SSD
SRD
SRS
SCS
SRR
LL
RL
TM
SS
SB
SIGNAL GROUND
SEND COMMON
RECEIVE COMMON
TERMINAL IN SERVICE
INCOMING CALL
TERMINAL READY
DATA MODE
SEND DATA
RECEIVE DATA
TERMINAL TIMING
SEND TIMING
RECEIVE TIMING
REQUEST TO SEND
CLEAR TO SEND
RECEIVER READY
SIGNAL QUALITY
NEW SIGNAL
SELECT FREQUENCY
SIGNAL RATE SELECTOR
SIGNAL RATE INDICATOR
SECONDARY SEND DATA
SECONDARY RD
SECONDARY RS
SECONDARY CS
SECONDARY RR
LOCAL LOOPBACK
REMOTE LOOPBACK
TEST MODE
SELECT STANDBY
STANDBY INDICATOR
CIRCUIT
DIRECTION
--------------
TO DCE
FROM DCE
TO DCE
FROM DCE
TO DCE
FROM DCE
TO DCE
FROM DCE
TO DCE
FROM DCE
FROM DCE
TO DCE
FROM DCE
FROM DCE
FROM DCE
TO DCE
TO DCE
TO DCE
FROM DCE
TO DCE
FROM DCE
TO DCE
FROM DCE
FROM DCE
TO DCE
TO DCE
FROM DCE
TO DCE
FROM DCE
CIRCUIT
TYPE
COMMON
CONTROL
DATA
TIMING
CONTROL
DATA
CONTROL
PRIMARY CHANNEL
CIRCUIT NAME
SECONDARY
CHANNEL
CIRCUIT
MNEMONIC
CONTROL
CONTROL
RS-449 Interchange Circuits Table
SEL A
0
011
SEL B
01
01
LOOPBACK1111
SHUTDOWN
0
0
0
0
Figure 28. Mode selection for the SP332
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29
SP504_102_121708
1N5819
+5V
10µF
22µF
22µF
25
VCC
Drivers
27 26
VDD
22µF
30
C1+
28
31
C1V
C2+ C2- SS
TxD
14
4
22
12
30
7
25
17
35
58
56
54
RTS
16
52
63
TxC
15
65
42
ST
22
44
47
RL
17
16
45
51
LL
24
34
49
70
RxD
1
6
24
8
26
9
27
11
29
13
31
15
71
37
RxC
20
38
66
CTS
80
67
68
DSR
78
69
35
DCD
19
36
39
RI
21
TDEC 3 —TDEC 0 (pins 9-12)
DB-37 Connector
61
59
DTR
13
Receivers
22µF
32
40
76
SCT
79
5
23
77
see pinout diagram for various ground pins
SP504
"1100" for RS-449 mode
RDEC 3 —RDEC 0 (pins 5-2)
+5V
0.1µF
0.1µF
Note: The SP332 will require clamping
diodes on the driver outputs to limit the
voltage to +/-6V and comply with the RS-423
driver output specification of Voc = +/-4.0V to
+/-6.0V and VOUT ≥ +/-3.6V with a 450Ω load.
13
C2-
VCC
V+
10
V- 14
SP332
0.1µF
10 µF
0.1µF
26
T1
6
LL
10
27
T2
7
RL
14
TM
18
28
0
1
5
9
C1+
12
C111
C2+
T3
3
4
19
R1
15
20
R2
16
21
R3
24
2
SEL A
SEL B
LOOPBACK
18
17
23
8
1
Figure 29. Adding extra differential and single-ended transceivers using the SP332
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
30
SP504_102_121708
PACKAGE: 80 Pin LQFP
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
31
SP504_102_121708
ORDERING INFORMATION
Model
Temperature Range
Package Types
SP504MCM-L....................................................................... 0°C to +70°C................................................................................................80–pin LQFP
revision history
DATE
REVISION
DESCRIPTION
01-27-04
A
7-7-08
1.0.0
Implemented tracking revision.
SP504 is no longer available in MQFP package per PCN 07-1102-06a. SP514 is
now only available in LQFP package compliant to RoHS. Changed to Exar datasheet format and revision to 1.0.0.
10/28/08
1.0.1
Added ESD rating of 500V HBM to electrical characteristics.
12/17/08
1.0.2
Add new V.35 Driver output VOD vs. Temperature graph and update figure numbers.
Notice
EXAR Corporation reserves the right to make changes to any products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for
illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for
use in such applications unless EXAR Corporation receives, in writting, assurances to its satisfaction that: (a) the risk of injury or damage has been
minimized ; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 2008 EXAR Corporation
Datasheet December 2008
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Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
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