SIPEX SP503EM

®
SP503
61 SD(a)
62 VCC
63 TT(a)
64 GND
65 TT(b)
66 CS(a)
67 CS(b)
68 DM(a)
69 DM(b)
70 RD(a)
71 RD(b)
72 GND
74 VCC
73 VCC
75 GND
76 SCT(a)
77 SCT(b)
78 DSR
80 CTS
■ Single Chip Programmable Serial
Transceiver
■ Seven (7) Drivers and Seven (7)
Receivers
■ Software-Selectable Industry Standard
Protocols:
— RS-232 (V.28)
— EIA-530
— RS-449
— RS-422A (V.11, X.27)
— RS-485
— V.35
■ Independant Driver and Receiver Mode
Selection
■ +5V Single Power Supply Operation
■ Surface Mount Packaging
79 SCT
Multiprotocol Transceiver
RxD 1
60 GND
RDEC0 2
59 SD(b)
RDEC1 3
58 TR(a)
RDEC2 4
57 GND
RDEC3 5
56 TR(b)
TTEN 6
55 VCC
54 RS(a)
SCTEN 7
VCC 8
53 GND
TDEC3 9
52 RS(b)
SP503
TDEC2 10
TDEC1 11
51 LL(a)
50 GND
TDEC0 12
49 LL(b)
IC(b) 40
IC(a) 39
RT(b) 38
RT(a) 37
RR(b) 36
RR(a) 35
GND 34
VCC 33
41 VCC
VSS 32
42 ST(a)
RxC 20
GND 29
C1– 30
C2– 31
43 GND
DCD 19
VDD 27
C2+ 28
44 ST(b)
NC 18
VCC 25
C1+ 26
45 RL(b)
RL 17
LL 24
46 GND
RTS 16
RI 21
47 RL(a)
TxC 15
ST 22
48 VCC
TxD 14
STEN 23
DTR 13
Now Available in Lead Free Packaging
DESCRIPTION
The SP503 is a highly integrated serial transceiver that allows software control of its interface
modes. It offers hardware interface modes for RS-232 (V.28), RS-422A (V.11), RS-449, RS-485,
V.35, and EIA-530. The SP503 is fabricated using low–power BiCMOS process technology, and
incorporates a Sipex patented (5,306,954) charge pump allowing +5V only operation.
Drivers
Receivers
SP503
Charge
Pump
Date: 7/29/04
Driver
Decode
SP503 Multiprotocol Transceiver
1
Receiver
Decode
© Copyright 2004 Sipex Corporation
ELECTRICAL CHARACTERISTICS
TMIN to TMAX @ Vcc = +5V ±5% unless otherwise noted.
MIN.
LOGIC INPUTS
VIL
VIH
LOGIC OUTPUTS
VOL
VOH
RS-485 DRIVER
TTL Input Levels
VIL
VIH
Outputs
HIGH Level Output
LOW level Output
Differential Output
Balance
Open Circuit Voltage
Output Current
Short Circuit Current
Transition Time
Maximum Transmission Rate
Propagation Delay
tPHL
tPLH
RS-485 RECEIVER
TTL Output Levels
VOL
VOH
Input
HIGH Threshold
LOW Threshold
Common Mode Range
HIGH Input Current
LOW Input Current
Receiver Sensitivity
TYP.
0.8
Volts
Volts
0.4
Volts
Volts
0.8
Volts
Volts
+6.0
Volts
Volts
Volts
Volts
Volts
mA
mA
ns
Mbps
2.4
2.0
–0.3
±1.5
±5.0
±0.2
±6.0
28.0
±250
120
5
200
200
ns
ns
0.4
Volts
Volts
+12.0
–0.2
+12.0
Volts
Volts
Volts
2.4
+0.2
–7.0
–7.0
±0.2
Output Impedance
50
Short Circuit Impedance
135
Date: 7/29/04
UNITS
2.0
Input Impedance
12
Maximum Transmission Rate
5
Propagation Delay
tPHL
tPLH
V.35 DRIVER
TTL Input Levels
VIL
VIH
2.0
Outputs
Differential Output
±0.44
Transition Time
Maximum Transmission Rate
Propagation Delay
tPHL
tPLH
MAX.
Volts
CONDITIONS
IOUT= -3.2mA
IOUT= 1.0mA
RL=54Ω, CL=50pF
|VT| - |VT|
RL=54Ω
Terminated in –7V to +12V
Rise/fall time, 10%–90%
RL=54Ω
RL=54Ω
RL=54Ω
(a)-(b)
(a)-(b)
Refer to graph
Refer to graph
Over –7V to +12V common
mode range
kΩ
Mbps
150
200
200
ns
ns
0.8
Volts
Volts
±0.66
Volts
With termination network in
Figure 6; RL=100Ω
With termination network in
Figure 6.
With termination network
in Figure 6.
150
Ω
165
Ω
40
ns
Mbps
RL=100Ω
ns
ns
RL=100Ω
RL=100Ω
5
200
200
SP503 Multiprotocol Transceiver
2
© Copyright 2004 Sipex Corporation
ELECTRICAL CHARACTERISTICS
TMIN to TMAX @ Vcc = +5V ±5% unless otherwise noted.
MIN.
TYP.
MAX.
UNITS
0.4
Volts
Volts
V.35 RECEIVER
TTL Output Levels
VOL
VOH
Input
Receiver Sensitivity
Input Impedance
2.4
90
±0.2
100
110
Volts
Ω
Short Circuit Impedance
135
150
165
Ω
Maximum Transmission Rate
5
Propagation Delay
tPHL
tPLH
RS-422 DRIVER
TTL Input Levels
VIL
VIH
2.0
Outputs
Differential Output
±2.0
Open Circuit Voltage,VO
Balance
Offset
Short Circuit Current
Power Off Current
Transition Time
Maximum Transmission Rate
5
Propagation Delay
tPHL
tPLH
RS-422 RECEIVER
TTL Output Levels
VOL
VOH
2.4
Input
HIGH Threshold
+0.2
LOW Threshold
–6.0
Common Mode Range
–7.0
HIGH Input Current
LOW Input Current
Receiver Sensitivity
Input Impedance
4
Maximum Transmission Rate
5
Propagation Delay
tPHL
tPLH
RS-232 DRIVER
TTL Input Level
VIL
VIH
2.0
Outputs
HIGH Level Output
+5.0
LOW Level Output
–15.0
Open Circuit Voltage
–15
Short Circuit Current
Power Off Impedance
300
Date: 7/29/04
CONDITIONS
With termination network
in Figure 6.
With termination network
in Figure 6.
Mbps
200
200
ns
ns
0.8
Volts
Volts
±5.0
±6.0
±0.4
+3.0
±150
±100
60
Volts
Volts
Volts
Volts
mA
µA
ns
Mbps
200
200
ns
ns
0.4
Volts
Volts
+6.0
–0.2
+7.0
Volts
Volts
Volts
±0.2
Volts
kΩ
Mbps
200
200
ns
ns
0.8
Volts
Volts
+15
–5.0
+15
±100
Volts
Volts
Volts
mA
Ω
SP503 Multiprotocol Transceiver
3
RL=100Ω
|VT| – |VT|
VOUT=0V
Vcc = 0V, Vout = ±0.25V
Rise/fall time, 10%-90%
RL=100Ω
RL=100Ω
RL=100Ω
(a)-(b)
(a)-(b)
Refer to graph
Refer to graph
VCM=+7V to -7V
VCM=+10V to -10V
RL=3kΩ, VIN=0.8V, Vcc = 5V
RL=3kΩ, VIN=2.0V, Vcc = 5V
VOUT=0V
Vcc = 0V, Vout = ±2.0V
© Copyright 2004 Sipex Corporation
ELECTRICAL CHARACTERISTICS
TMIN to TMAX @ Vcc = +5V ±5% unless otherwise noted.
MIN.
TYP.
Slew Rate
Transition Time
Maximum Transmission Rate 120
Propagation Delay
tPHL
2
tPLH
2
RS-232 RECEIVER
TTL Output Levels
VOL
VOH
2.4
Input
HIGH Threshold
1.7
LOW Threshold
0.8
1.2
Receiver Open Circuit Bias
Input Impedance
3
5
Maximum Transmission Rate 120
Propagation Delay
tPHL
tPLH
RS-423 DRIVER
TTL Input Levels
VIL
VIH
2.0
Output
Open Circuit Voltage
±4.0
HIGH Level Output
+3.6
LOW Level Output
–6.0
Short Circuit Current
Power Off Current
Transition Time
0.8
Maximum Transmission Rate 120
Propagation Delay
tPHL
2
tPLH
2
RS-423 RECEIVER
TTL Output Levels
VOL
VOH
2.4
Input
HIGH Threshold
+0.2
LOW Threshold
–7.0
HIGH Input Current
LOW Input Current
Receiver Sensitivity
Input Impedance
4
Maximum Transmission Rate 120
Propagation Delay
tPHL
tPLH
POWER REQUIREMENTS
VCC
4.75
ICC
20
ENVIRONMENTAL AND MECHANICAL
Operating Temperature Range
0
Storage Temperature Range
–65
Package
80–pin QFP
Date: 7/29/04
MAX.
30
1.56
UNITS
V/µs
µs
kbps
8
8
µs
µs
0.4
Volts
Volts
2.4
Volts
Volts
Volts
kΩ
kbps
+2.0
7
1
1
Volts
Volts
±10.0
+6.0
–3.6
±150
±100
2.4
Volts
Volts
Volts
mA
µA
µs
kbps
µs
µs
0.4
Volts
Volts
+7.0
–0.2
Volts
Volts
±0.2
1
1
Volts
kΩ
kbps
Volts
mA
+70
+150
°C
°C
4
VIN=+15V to -15V
RL=550Ω
RL=550Ω
VOUT=0V
Vcc = 0V, Vout = ±0.25V
Rise/fall time, 10-90%
RL=550Ω
RL=550Ω
RL=550Ω
Refer to graph
Refer to graph
VCM = +7V to -7V
VIN = +10V to -10V
µs
µs
5.25
30
SP503 Multiprotocol Transceiver
RL=3kΩ
RL=3kΩ
µs
µs
0.8
8
8
CONDITIONS
RL=3kΩ, CL=15pF
RL=3kΩ, CL=2500pF
RL=3kΩ, CL=2500pF
VCC =5V; no interface selected
© Copyright 2004 Sipex Corporation
RECEIVER INPUT GRAPHS
RS-422 RECEIVER
RS-423 RECEIVER
+3.25mA
–10V
+3.25mA
–3V
–10V
+3V
–3V
+10V
+3V
Maximum Input Current
versus Voltage
+10V
Maximum Input Current
versus Voltage
–3.25mA
–3.25mA
RS-485 RECEIVER
+1.0mA
–7V
–3V
+6V
+12V
1 Unit Load
Maximum Input Current
versus Voltage
–0.6mA
POWER MATRIX
Typical @ 25°C and Vcc = +5V unless otherwise noted. Input is applied to one driver.
Mode
Open Input Input to 5V Input to GND AC Signal Input to 5V Input to GND AC Signal
to Input
with Load
with Load
with Load
Conditions
With external termination resistor network;
Input @ 60kHz, Load is 3kΩ & 2500pF for
RS-232 and 100Ω for V.35
V.35
47.0mA
48.8mA
47.3mA
54.5mA
104.2mA
100.9mA
100.9mA
RS-232
35.4mA
37.8mA
35.2mA
43.6mA
54.1mA
57.1mA
55.9mA
Input @ 60kHz
Load is 3kΩ & 2500pF for RS-232.
RS-422
25.8mA
31.4mA
25.8mA
27.5mA
140.2mA
135.9mA
145.2mA
Input @ 2.5MHz
Load is 100Ω.
RS-485
33.4mA
37.91mA
33.51mA
34.81mA
200.3mA
194.8mA
203.3mA
Input @ 2.5MHz
Load is 54Ω.
RS-449
37.8mA
40.3mA
41.1mA
42.9mA
142.3mA
138.8mA
147.4mA
Input @ 60kHz
Load is 100Ω for RS-422
450Ω for RS-423
EIA-530
45.2mA
48.1mA
44.4mA
50.3mA
148.9mA
145.7mA
147.3mA
Input @ 60kHz
Load is 100Ω for RS-422
450Ω for RS-423
Date: 7/29/04
SP503 Multiprotocol Transceiver
5
© Copyright 2004 Sipex Corporation
OTHER AC CHARACTERISTICS
(Typical @ 25°C and nominal supply voltages unless otherwise noted)
PARAMETER
MIN.
TYP.
MAX.
DELAY TIME FROM ENABLE MODE TO TRI–STATE MODE
SINGLE–ENDED MODE (RS-232, RS-423)
tPZL; Enable to Output LOW
190
tPZH; Enable to Output HIGH
130
tPLZ; Disable from Output LOW
270
tPHZ; Disable from Output HIGH
400
DIFFERENTIAL MODE (RS-422, RS-485, V.35)
tPZL; Enable to Output LOW
100
tPZH; Enable to Output HIGH
100
tPLZ; Disable from Output LOW
130
tPHZ; Disable from Output HIGH
140
UNITS
CONDITIONS
ns
ns
ns
ns
3kΩ pull–up to output
3kΩ pull–down to output
5V to input
GND to input
ns
ns
ns
ns
3kΩ pull–up to output
3kΩ pull–down to output
5V to input
GND to input
Notes:
1.
Measured from 2.5V of RIN to 2.5V of ROUT.
2.
Measured from one–half of RIN to 2.5V of ROUT.
3.
Measured from 1.5V of TIN to one–half of TOUT.
4.
Measured from 2.5V of RO to 0V of A and B.
Pin 20 — RxC — Receive Clock; TTL output
sourced from RT(a) and RT(b) inputs.
61 SD(a)
62 VCC
63 TT(a)
64 GND
65 TT(b)
66 CS(a)
67 CS(b)
68 DM(a)
69 DM(b)
70 RD(a)
71 RD(b)
73 VCC
72 GND
74 VCC
75 GND
76 SCT(a)
77 SCT(b)
78 DSR
79 SCT
80 CTS
PINOUT…
RxD 1
Pin 22 — ST — Send Timing; TTL input; source
for ST(a) and ST(b) outputs.
60 GND
RDEC0 2
59 SD(b)
RDEC1 3
58 TR(a)
RDEC2 4
57 GND
RDEC3 5
56 TR(b)
TTEN 6
Pin 37 — RT(a) — Receive Timing; analog
input, inverted; source for RxC.
55 VCC
54 RS(a)
SCTEN 7
VCC 8
53 GND
TDEC3 9
TDEC1 11
Pin 38 — RT(b) — Receive Timing; analog
input, non-inverted; source for RxC.
52 RS(b)
SP503
TDEC2 10
51 LL(a)
50 GND
TDEC0 12
49 LL(b)
DTR 13
48 VCC
TxD 14
47 RL(a)
TxC 15
46 GND
RTS 16
45 RL(b)
RL 17
44 ST(b)
Pin 44 — ST(b) — Send Timing; analog output,
non-inverted; sourced from ST.
IC(b) 40
IC(a) 39
RT(b) 38
RT(a) 37
RR(b) 36
RR(a) 35
GND 34
VCC 33
2
VSS 32
GND 29
C1– 30
C – 31
VDD 27
C2+ 28
VCC 25
C1+ 26
LL 24
41 VCC
RI 21
42 ST(a)
ST 22
43 GND
RxC 20
STEN 23
NC 18
DCD 19
Pin 42 — ST(a) — Send Timing; analog output,
inverted; sourced from ST.
Pin 59 — SD(b) — Analog Out — Send data,
non-inverted; sourced from TxD.
Pin 61 — SD(a) — Analog Out — Send data,
inverted; sourced from TxD.
PIN ASSIGNMENTS…
CLOCK AND DATA GROUP
Pin 1 — RxD — Receive Data; TTL output,
sourced from RD(a) and RD(b) inputs.
Pin 63 — TT(a) — Analog Out — Terminal
Timing, inverted; sourced from TxC
Pin 14 — TxD — TTL input ; transmit data
source for SD(a) and SD(b) outputs.
Pin 65 — TT(b) — Analog Out — Terminal
Timing, non–inverted; sourced from TxC.
Pin 15 — TxC — Transmit Clock; TTL input for
TT driver outputs.
Pin 70 — RD(a) — Receive Data, analog input;
inverted; source for RxD.
Date: 7/29/04
SP503 Multiprotocol Transceiver
6
© Copyright 2004 Sipex Corporation
Pin 71 — RD(b) — Receive Data; analog input;
non-inverted; source for RxD.
Pin 54 — RS(a) — Ready To Send; analog
output, inverted; sourced from RTS.
Pin 76 — SCT(a) — Serial Clock Transmit;
analog input, inverted; source for SCT.
Pin 56 — TR(b) — Terminal Ready; analog
output, non-inverted; sourced from DTR.
Pin 77 — SCT(b) — Serial Clock Transmit:
analog input, non–inverted; source for SCT
Pin 58 — TR(a) — Terminal Ready; analog
output, inverted; sourced from DTR.
Pin 79 — SCT — Serial Clock Transmit; TTL
output; sources from SCT(a) and SCT(b) inputs.
Pin 66 — CS(a)— Clear To Send; analog input,
inverted; source for CTS.
Pin 67 — CS(b)— Clear To Send; analog input,
non-inverted; source for CTS.
CONTROL LINE GROUP
Pin 13 — DTR — Data Terminal Ready; TTL
input; source for TR(a) and TR(b) outputs.
Pin 68 — DM(a)— Data Mode; analog input,
inverted; source for DSR.
Pin 16 — RTS — Ready To Send; TTL input;
source for RS(a) and RS(b) outputs.
Pin 69 — DM(b)— Data Mode; analog input,
non-inverted; source for DSR
Pin 17 — RL — Remote Loopback; TTL input;
source for RL(a) and RL(b) outputs.
Pin 78 — DSR— Data Set Ready; TTL output;
sourced from DM(a), DM(b) inputs.
Pin 19 — DCD— Data Carrier Detect; TTL
output; sourced from RR(a) and RR(b) inputs.
Pin 80 — CTS— Clear To Send; TTL output;
sourced from CS(a) and CS(b) inputs.
Pin 21 — RI — Ring In; TTL output; sourced
from IC(a) and IC(b) inputs.
CONTROL REGISTERS
Pins 2–5 — RDEC0 – RDEC3 — Receiver
decode register; configures receiver modes; TTL
inputs.
Pin 24 — LL — Local Loopback; TTL input;
source for LL(a) and LL(b) outputs.
Pin 35 — RR(a)— Receiver Ready; analog
input, inverted; source for DCD.
Pin 6 — TTEN — Enables TT driver, active
low; TTL input.
Pin 36 — RR(b)— Receiver Ready; analog
input, non-inverted; source for DCD.
Pin 7 — SCTEN — Enables SCT receiver;
active high; TTL input.
Pin 39 — IC(a)— Incoming Call; analog input,
inverted; source for RI.
Pin 40 — IC(b)— Incoming Call; analog input,
non-inverted; source for RI.
Pins 12–9 — TDEC0 – TDEC3 — Transmitter
decode register; configures transmitter modes;
TTL inputs.
Pin 45 — RL(b) — Remote Loopback; analog
output, non-inverted; sourced from RL.
Pin 23 — STEN — Enables ST driver; active
low; TTL input.
Pin 47 — RL(a) — Remote Loopback; analog
output inverted; sourced from RL.
POWER SUPPLIES
Pins 8, 25, 33, 41, 48, 55, 62, 73, 74 — VCC —
+5V input.
Pin 49— LL(b) — Local Loopback; analog
output, non-inverted; sourced from LL.
Pins 29, 34, 43, 46, 50, 53, 57, 60, 64, 72, 75 —
GND — Ground.
Pin 51 — LL(a) — Local Loopback; analog
output, inverted; sourced from LL.
Pin 27 — VDD +10V Charge Pump Capacitor —
Connects from VDD to VCC. Suggested capacitor size is 22µF, 16V.
Pin 52 — RS(b) — Ready To Send; analog
output, non-inverted; sourced from RTS.
Date: 7/29/04
SP503 Multiprotocol Transceiver
7
© Copyright 2004 Sipex Corporation
Pin 32 — VSS –10V Charge Pump Capacitor —
Connects from ground to VSS. Suggested capacitor size is 22µF, 16V.
pared to older less–efficient designs. The charge
pump still requires four external capacitors, but
uses a four–phase voltage shifting technique to
attain symmetrical 10V power supplies. Figure
3(a) shows the waveform found on the positive
side of capcitor C2, and Figure 3(b) shows the
negative side of capcitor C2. There is a free–
running oscillator that controls the four phases
of the voltage shifting. A description of each
phase follows.
Pins 26 and 30 — C1+ and C1– — Charge Pump
Capacitor — Connects from C1+ to C1–. Suggested capacitor size is 22µF, 16V.
Pins 28 and 31 — C2+ and C2– — Charge Pump
Capacitor — Connects from C2+ to C2–. Suggested capacitor size is 22µF, 16V.
Phase 1
— VSS charge storage —During this phase of
the clock cycle, the positive side of capacitors
C1 and C2 are initially charged to +5V. Cl+ is
then switched to ground and the charge on C1– is
transferred to C2–. Since C2+ is connected to
+5V, the voltage potential across capacitor C2
is now 10V.
NOTE: NC pins should be left floating; internal
signals may be present.
FEATURES…
The SP503 is a highly integrated serial transceiver that allows software control of its interface modes. The SP503 offers hardware interface modes for RS-232 (V.28), RS-422A (V.11),
RS-449, RS-485, V.35, and EIA-530. The interface mode selection is done via an 8–bit switch;
four (4) bits control the drivers and four (4) bits
control the receivers. The SP503 is fabricated
using low–power BiCMOS process technology,
and incorporates a Sipex patented (5,306,954)
charge pump allowing +5V only operation. Each
device is packaged in an 80–pin Quad FlatPack
package.
Phase 2
— VSS transfer — Phase two of the clock connects the negative terminal of C2 to the VSS
storage capacitor and the positive terminal of C2
to ground, and transfers the generated –l0V to
C3. Simultaneously, the positive side of capacitor C 1 is switched to +5V and the negative side
is connected to ground.
Phase 3
— VDD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C1 produces –5V in the negative
terminal of C1, which is applied to the negative
side of capacitor C2. Since C2+ is at +5V, the
voltage potential across C2 is l0V.
The SP503 is ideally suited for wide area network connectivity based on the interface modes
offered and the driver and receiver
configurations. The SP503 has seven (7)
independent drivers and seven (7) independent
receivers. The seventh driver of the SP503
allows it to support applications which require
two separate clock outputs making it ideal for
DCE applications.
Phase 4
— VDD transfer — The fourth phase of the
clock connects the negative terminal of C2 to
ground and transfers the generated l0V across
C2 to C4, the VDD storage capacitor. Again,
THEORY OF OPERATION
The SP503 is made up of four separate circuit
blocks — the charge pump, drivers, receivers,
and decoder. Each of these circuit blocks is
described in more detail below.
VCC = +5V
C4
+5V
C1
Charge–Pump
The charge pump is a Sipex patented design
(5,306,954) and uses a unique approach com-
+
–
–5V
C2
+
–
–
+
+
–
VDD Storage Capacitor
VSS Storage Capacitor
C3
–5V
Figure 1. Charge Pump Phase 1.
Date: 7/29/04
SP503 Multiprotocol Transceiver
8
© Copyright 2004 Sipex Corporation
and RS-423 drivers. For the RS-232 driver, the
current requirement will be 3.5mA per driver,
and for the RS-423 driver, the worst case current
drain will be 11mA per driver. The external
power supplies should provide a power supply
sequence of : +l0V, then +5V, followed by –l0V.
VCC = +5V
C4
C1
+
–
C2
+
–
–
+
+
–
VDD Storage Capacitor
VSS Storage Capacitor
C3
–10V
Drivers
The SP503 has seven (7) independent drivers,
two of which have separate active–low tri–state
controls. If a half-duplex channel is required,
this can be achieved with external connections.
Figure 2. Charge Pump Phase 2.
simultaneously with this, the positive side of
capacitor C1 is switched to +5V and the negative
side is connected to ground, and the cycle begins
again.
Control for the mode selection is done via a
four–bit control word. The SP503 does not have
a latch; the control word must be externally
latched either high or low to write the appropriate code into the SP503. The drivers are prearranged such that for each mode of operation
the relative position and functionality of the
drivers are set up to accommodate the selected
interface mode. As the mode of the drivers is
changed, the electrical characteristics will change
to support the requirements of clock, data, and
control line signal levels. Table 1 shows a summary of the electrical characteristics of the drivers in the different interface modes. Unused
driver inputs can be left floating; however, to
ensure a desired state with no input signal, pull–
up resistors to +5V or pull–down resistors to
ground are suggested. Since the driver inputs
are both TTL or CMOS compatible, any value
resistor less than 100kΩ will suffice.
Since both V+ and V– are separately generated
from VCC in a no–load condition, V+ and V– will
be symmetrical. Older charge pump approaches
that generate V– from V+ will show a decrease
in the magnitude of V– compared to V+ due to
the inherent inefficiencies in the design.
The clock rate for the charge pump typically
operates at 15kHz. The external capacitors must
be 22µF with a 16V breakdown rating.
External Power Supplies
For applications that do not require +5V only,
external supplies can be applied at the V+ and
V– pins. The value of the external supply voltages must be no greater than ±l0V. The current
drain for the ±10V supplies is used for RS-232,
+10V
C2 +
a)
GND
GND
C2–
b)
–10V
Figure 3. Charge Pump Waveforms
Date: 7/29/04
SP503 Multiprotocol Transceiver
9
© Copyright 2004 Sipex Corporation
VCC = +5V
VCC = +5V
C4
+5V
C1
+
–
C2
–5V
+
–
–
+
+
–
VDD Storage Capacitor
C1
C3
–5V
C4
+10V
VSS Storage Capacitor
+
C2
–
+
–
–
+
+
–
VDD Storage Capacitor
VSS Storage Capacitor
C3
Figure 4. Charge Pump Phase 3.
Figure 5. Charge Pump Phase 4.
There are three basic types of driver circuits —
RS-232, RS-423, and RS-485. The RS-232 drivers output a minimum of ±5V level single–
ended signals (with 3kΩ and 2500pF loading),
and can operate up to 120kbps. The RS-232
drivers are used in RS-232 mode for all signals,
and also in V.35 mode where they are used as the
control line signals.
the RS-485 drivers allow the drivers to also
support RS-422 requirements of ±2V differential output levels with 100Ω loads. The RS-422
drivers are used in RS-449 and EIA-530 modes
as clock, data, and some control line signals.
The RS-485–type drivers are also used in the
V.35 mode. V.35 levels require ±0.55V signals
with a load of 100Ω. In order to meet the voltage
requirements of V.35, external series resistors
with source impedance termination resistors
must be implemented to voltage divide the driver
outputs from 0 to +5V to 0 to +0.55V. Figure 6
shows the values of the resistor network and
how to connect them. The termination network
also achieves the 50Ω to 150Ω source impedance for V.35. For applications that require
V.11 signals for clock and data instead of V.35
levels, omit the external termination networks.
All of the differential drivers, RS-485, RS-422,
and V.35 can operate up to 5Mbps.
The RS-423 drivers output a minimum of ±3.6V
level single–ended signals (with 450Ω loading)
and can operate up to 120kbps. Open circuit VOL
and VOH measurements may exceed the ±6V
limitation of RS-423. The RS-423 drivers are
used in RS-449 and EIA-530 modes as RL and
LL outputs.
The third type of driver supports RS-485, which
is a differential signal that can maintain ±1.5V
differential output levels with a worst case load
of 54Ω. The signal levels and drive capability of
Pin Label
Mode:
RS-232
V.35
RS-422
RS-485
RS-449
TDEC3–TDEC0
0000
0010
1110
0100
0101
1100
1101
tri–state
RS-232
V.35–
RS-422–
RS-485–
RS-422–
RS-422–
SD(b)
tri–state
tri–state
V.35+
RS-422+
RS-485+
RS-422+
RS-422+
TR(a)
tri–state
RS-232
RS-232
RS-422–
RS-485–
RS-422–
RS-422–
TR(b)
tri–state
tri–state
tri–state
RS-422+
RS-485+
RS-422+
RS-422+
RS(a)
tri–state
RS-232
RS-232
RS-422–
RS-485–
RS-422–
RS-422–
RS(b)
tri–state
tri–state
tri–state
RS-422+
RS-485+
RS-422+
RS-422+
RL(a)
tri–state
RS-232
RS-232
RS-422–
RS-485–
RS-423
RS-423
RL(b)
tri–state
tri–state
tri–state
RS-422+
RS-485+
tri–state
tri–state
LL(a)
tri–state
RS-232
RS-232
RS-422–
RS-485–
RS-423
RS-423
LL(b)
tri–state
tri–state
tri–state
RS-422+
RS-485+
tri–state
tri–state
ST(a)
tri–state
RS-232
V.35–
RS-422–
RS-485–
RS-422–
RS-422–
ST(b)
tri–state
tri–state
V.35+
RS-422+
RS-485+
RS-422+
RS-422+
TT(a)
tri–state
RS-232
V.35–
RS-422–
RS-485–
RS-422–
RS-422–
TT(b)
tri–state
tri–state
V.35+
RS-422+
RS-485+
RS-422+
RS-422+
SD(a)
EIA-530
Table 1. SP503 Drivers
Date: 7/29/04
SP503 Multiprotocol Transceiver
10
© Copyright 2004 Sipex Corporation
+5V, ±5%
IN5819
22µF (VCC decoupling)
All VCC connections can be tied
+
+
27
22µF, 16V
VDD
26
22µF +
16V
200Ω
232Ω
+
C1
32
C1–
Charge
Pump
C2+
V.35 External
Driver Output
Termination Resistors
200Ω
232Ω
C2–
VSS
107Ω
232Ω
200Ω
-5V
31
+
22µF, 16V
VCC
together. Charge pump capacitors must
be placed as close to the package as
possible.
-5V
30
28
22µF +
16V
25
107Ω
232Ω
200Ω
GND
SP503
200Ω
232Ω
-5V
107Ω
232Ω
200Ω
1
50Ω
V.35 MODE Control Word
1
Driver
Decode
1
120Ω
50Ω
V.35 External
Receiver Input
Termination Resistors
0
50Ω
Ext.
Latch
120Ω
50Ω
1
1
Receiver
Decode
1
0
50Ω
120Ω
50Ω
Note: An external voltage of -5V, ±5% is needed for the driver output termination resistors.
These V.35 termination resistors comply with all the parameters specified in CCITT
Recommendation V.35. For other termination configurations, please consult factory.
Figure 6. Typical Operating Circuit
Date: 7/29/04
SP503 Multiprotocol Transceiver
11
© Copyright 2004 Sipex Corporation
There are three basic types of receivers —
RS-232, RS-423, and RS-485. The RS-232
receiver is a single–ended input with a threshold
of 0.8V to 2.4V. The RS-232 receiver has an
operating voltage range of ±15V and can receive signals up to 120kbps. RS-232 receivers
are used in RS-232 mode for all signal types, and
in V.35 mode for control line signals.
Receivers
The SP503 has seven (7) independent receivers
which can be programmed for six (6) different
interface modes. One of the seven (7) receivers
(SCT) has an active–high enable control, as
shown in the Mode Diagrams.
Control for the mode selection is done via a 4–
bit control word that is independent from the
driver control word. The coding for the drivers
and receivers is identical. Therefore, if the modes
for the drivers and receivers are supposed to be
identical in the application, the control lines can
be tied together.
The RS-423 receivers are also single–ended but
have an input threshold as low as ±200mV. The
input impedance is guaranteed to be greater than
4kΩ, with an operating voltage range of ±7V.
The RS-423 receivers can operate up to 120kbps.
RS-423 receivers are used for the IC signal in
RS-449 and EIA-530 modes, as shown in Table 2.
Like the drivers, the receivers are pre-arranged
for the specific requirements of the interface. As
the operating mode of the receivers is changed,
the electrical characteristics will change to support the requirements of clock, data, and control
line receivers. Table 2 shows a summary of the
electrical characteristics of the receivers in the
different interface modes. Unused receiver inputs can be left floating without causing oscillation. To ensure a desired state of the receiver
output, a pull–up resistor of 100kΩ to +5V
should be connected to the inverting input for a
logic low, or the non–inverting input for a logic
high. For single-ended receivers, a pull–down
resistor to ground of 5kΩ is internally connected, which will ensure a logic high output.
Pin Label
The third type of receiver supports RS-485,
which is a differential interface mode. The
RS-485 receiver has an input impedance of
15kΩ and a differential threshold of ±200mV.
Since the characteristics of an RS-422 receiver
are actually subsets of RS-485, the receivers for
RS-422 requirements are identical to the
RS-485 receivers. RS-422 receivers are used in
RS-449 and EIA-530 for receiving clock, data,
and some control line signals. The RS-485
receivers are also used for the V.35 mode. V.35
levels require the ±0.55V signals with a load of
100Ω. In order to meet the V.35 input impedance of 100Ω, the external termination network
of Figure 6 must be applied. The threshold of the
V.35 receiver is ±200mV. The V.35 receivers
Mode:
RS-232
V.35
RS-422
RS-485
RS-449
0000
0010
1110
0100
0101
1100
1101
Undefined
RS-232
V.35–
RS-422–
RS-485–
RS-422–
RS-422–
RD(b)
Undefined
15kΩ to GND
V.35+
RS-422+
RS-485+
RS-422+
RS-422+
RT(a)
Undefined
RS-232
V.35–
RS-422–
RS-485–
RS-422–
RS-422–
RT(b)
Undefined
15kΩ to GND
V.35+
RS-422+
RS-485+
RS-422+
RS-422+
RDEC3–RDEC0
RD(a)
EIA-530
CS(a)
Undefined
RS-232
RS-232
RS-422–
RS-485–
RS-422–
RS-422–
CS(b)
Undefined
15kΩ to GND
15KΩ to GND
RS-422+
RS-485+
RS-422+
RS-422+
DM(a)
Undefined
RS-232
RS-232
RS-422–
RS-485–
RS-422–
RS-422–
DM(b)
Undefined
15kΩ to GND
15KΩ to GND
RS-422+
RS-485+
RS-422+
RS-422+
RR(a)
Undefined
RS-232
RS-232
RS-422–
RS-485–
RS-422–
RS-422–
RR(b)
Undefined
15kΩ to GND
15KΩ to GND
RS-422+
RS-485+
RS-422+
RS-422+
IC(a)
Undefined
RS-232
RS-232
RS-422–
RS-485–
RS-423
RS-423
IC(b)
Undefined
15kΩ to GND
15KΩ to GND
RS-422+
RS-485+
15KΩ to GND
15KΩ to GND
SCT(a)
Undefined
RS-232
V.35–
RS-422–
RS-485–
RS-422–
RS-422–
SCT(b)
Undefined
15kΩ to GND
V.35+
RS-422+
RS-485+
RS-422+
RS-422+
Table 2. SP503 Receivers
Date: 7/29/04
SP503 Multiprotocol Transceiver
12
© Copyright 2004 Sipex Corporation
can operate up to 5Mbps. All of the differential
receivers can receive data up to 5Mbps.
Decoder
The SP503 has the ability to change the interface mode of the drivers or receivers via an 8–bit
switch. The decoder for the drivers and receivers is not latched; it is merely a combinational
logic switch. The codes shown in Tables 1 and
2 are the only specified, valid modes for the
SP503. Undefined codes may represent other
interface modes not specified or random outputs
(consult the factory for more information). The
drivers are controlled with the data bits labeled
TDEC3–TDEC0. The drivers can be put into tristate mode by writing 0000 to the driver decode
switch. The receivers are controlled with data
bits RDEC3–RDEC0; the code 0000 written to
the receivers will place the outputs in an undetermined state. All receivers, with the exception
of SCT, do not have tri-state capability; the
outputs will either be HIGH or LOWdepending
upon the state of the receiver input.
Date: 7/29/04
SP503 Multiprotocol Transceiver
13
© Copyright 2004 Sipex Corporation
MODE: RS-232
DRIVER
RECEIVER
TDEC3 TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC0
0
0
1
0
0
0
1
0
RD(a) 70
14 TxD
RxD 1
61 SD(a)
RT(a) 37
13 DTR
RxC 20
58 TR(a)
CS(a) 66
16 RTS
CTS 80
54 RS(a)
DM(a) 68
17 RL
DSR 78
47 RL(a)
RR(a) 35
24 LL
DCD 19
51 LL(a)
IC(a) 39
22 ST
RI 21
42 ST(a)
SCT(a) 76
23 STEN
15 TxC
SCT 79
63 TT(a)
SCTEN 7
6 TTEN
RECEIVERS
STEN
1
0
ST
Disabled
Enabled
DRIVERS
TTEN
TT
SCTEN
1
Disabled
1
0
Enabled
0
SCT
Enabled
Disabled
Figure 7. Mode Diagram — RS-232
Date: 7/29/04
SP503 Multiprotocol Transceiver
14
© Copyright 2004 Sipex Corporation
MODE: V.35
DRIVER
RECEIVER
TDEC3 TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC0
1
1
1
0
1
1
1
0
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
RxC 20
16 RTS
RT(b) 38
CS(a) 66
54 RS(a)
CTS 80
17 RL
DM(a) 68
47 RL(a)
DSR 78
24 LL
RR(a) 35
51 LL(a)
DCD 19
22 ST
IC(a) 39
42 ST(a)
RI 21
44 ST(b)
23 STEN
SCT(a) 76
15 TxC
SCT 79
63 TT(a)
SCTEN 7
SCT(b) 77
65 TT(b)
6
RECEIVERS
STEN
1
0
ST
Disabled
Enabled
TTEN
DRIVERS
TTEN
TT
SCTEN
1
Disabled
1
0
Enabled
0
SCT
Enabled
Disabled
Figure 8. Mode Diagram — V.35
Date: 7/29/04
SP503 Multiprotocol Transceiver
15
© Copyright 2004 Sipex Corporation
MODE: RS-422
DRIVER
RECEIVER
TDEC3 TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC0
0
1
0
0
0
1
0
0
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
RxC 20
56 TR(b)
RT(b) 38
CS(a) 66
16 RTS
54 RS(a)
CTS 80
52 RS(b)
CS(b) 67
17 RL
DM(a) 68
47 RL(a)
DSR 78
45 RL(b)
DM (b) 69
24 LL
RR(a) 35
51 LL(a)
DCD 19
49 LL(b)
RR(b) 36
22 ST
IC(a) 39
42 ST(a)
RI 21
44 ST(b)
IC(b) 40
23 STEN
SCT(a) 76
15 TxC
SCT 79
63 TT(a)
65 TT(b)
SCTEN 7
SCT(b) 77
6
RECEIVERS
STEN
1
0
ST
Disabled
Enabled
TTEN
DRIVERS
TTEN
TT
SCTEN
1
Disabled
1
0
Enabled
0
SCT
Enabled
Disabled
Figure 9. Mode Diagram — RS-422
Date: 7/29/04
SP503 Multiprotocol Transceiver
16
© Copyright 2004 Sipex Corporation
MODE: RS-449
DRIVER
RECEIVER
TDEC3 TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC0
1
1
0
0
1
1
0
0
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
RxC 20
56 TR(b)
RT(b) 38
CS(a) 66
16 RTS
54 RS(a)
CTS 80
52 RS(b)
CS(b) 67
17 RL
DM(a) 68
47 RL(a)
DSR 78
24 LL
DM (b) 69
RR(a) 35
51 LL(a)
DCD 19
22 ST
RR(b) 36
42 ST(a)
IC(a) 39
44 ST(b)
RI 21
23 STEN
SCT(a) 76
15 TxC
SCT 79
63 TT(a)
65 TT(b)
SCTEN 7
SCT(b) 77
6
RECEIVERS
STEN
1
0
ST
Disabled
Enabled
TTEN
DRIVERS
TTEN
TT
SCTEN
1
Disabled
1
0
Enabled
0
SCT
Enabled
Disabled
Figure 10. Mode Diagram — RS-449
Date: 7/29/04
SP503 Multiprotocol Transceiver
17
© Copyright 2004 Sipex Corporation
MODE: RS-485
DRIVER
RECEIVER
TDEC3 TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC0
0
1
0
1
0
1
0
1
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
RxC 20
56 TR(b)
RT(b) 38
CS(a) 66
16 RTS
54 RS(a)
CTS 80
52 RS(b)
CS(b) 67
17 RL
DM(a) 68
47 RL(a)
DSR 78
45 RL(b)
DM (b) 69
24 LL
RR(a) 35
51 LL(a)
DCD 19
49 LL(b)
RR(b) 36
22 ST
IC(a) 39
42 ST(a)
RI 21
44 ST(b)
IC(b) 40
23 STEN
SCT(a) 76
15 TxC
SCT 79
63 TT(a)
65 TT(b)
SCTEN 7
SCT(b) 77
6
RECEIVERS
STEN
1
0
ST
Disabled
Enabled
TTEN
DRIVERS
TTEN
TT
SCTEN
1
Disabled
1
0
Enabled
0
SCT
Enabled
Disabled
Figure 11. Mode Diagram — RS-485
Date: 7/29/04
SP503 Multiprotocol Transceiver
18
© Copyright 2004 Sipex Corporation
MODE: EIA-530
DRIVER
RECEIVER
TDEC3 TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC0
1
1
0
1
1
1
0
1
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
RxC 20
56 TR(b)
RT(b) 38
CS(a) 66
16 RTS
54 RS(a)
CTS 80
52 RS(b)
CS(b) 67
17 RL
DM(a) 68
47 RL(a)
DSR 78
24 LL
DM (b) 69
RR(a) 35
51 LL(a)
DCD 19
22 ST
RR(b) 36
42 ST(a)
IC(a) 39
44 ST(b)
RI 21
23 STEN
SCT(a) 76
15 TxC
SCT 79
63 TT(a)
65 TT(b)
SCTEN 7
SCT(b) 77
6
RECEIVERS
STEN
1
0
ST
Disabled
Enabled
TTEN
DRIVERS
TTEN
TT
SCTEN
1
Disabled
1
0
Enabled
0
SCT
Enabled
Disabled
Figure 12. Mode Diagram — EIA-530
Date: 7/29/04
SP503 Multiprotocol Transceiver
19
© Copyright 2004 Sipex Corporation
to the SP503. If a logic one is asserted, the
corresponding red LED will be lit. If a zero is
asserted, the corresponding red LED will not
be lit.
SP502/SP503 EVALUATION BOARD
The SP502/SP503 Evaluation Board (EB) Is
designed to offer as much flexibility to the user
as possible. Each board comes equipped with an
80-pin QFP Zero-Insertion Force socket to
allow for testing of multiple devices. The control lines and inputs and outputs of the device
can be controlled either manually or via a data
bus under software control. There is a 50-pin
connector to allow for easy connection to an
existing system via a ribbon cable. There are
also open areas on the PC board to add additional circuitry to support application-specific
requirements.
Software Control
A 50-pin connector brings all the analog and
digital I/O lines, VCC, and GND to the edge of the
card. This can be wired to the user’s existing
design via a ribbon cable. The pinout for the
connector is described in the following section.
When the evaluation board is operated under
software control, the DlP switch should be set
up so that all bits are LOW (all LEDs off). This
will tie 20kΩ pulldown resistors from the inputs
to ground and let the external system control the
state of the control inputs.
Manual Control
The SP502/SP503EB will support both the
SP502 or SP503 multi-mode serial transceivers. When used for the SP502, disregard all
notation on the board that is in [brackets] . The
SP502 has a half-duplex connection between
the RxT receiver and the TT driver. Due to this
internal connection, the RxT receiver inputs can
be accessed via the TT(a) and TT(b) pins. If the
user needs separate receiver input test pins,
jumpers JP1 and JP2 can be inserted to allow for
separate receiver inputs located at SCT(a) and
SCT(b). The corresponding TTL output for this
receiver is labeled as SCT. This test point is tied
to pin 79 of the SP502 or SP503. Pin 7 of the
evaluation board is connected to the DIP switch,
and is labeled as (SCTEN). When used with the
SP502, this pin should be switched to a low
state. When the evaluation board is used with
the SP503, pin 7 is a tri-state control pin for the
SCT receiver.
Power and Ground Requirements
The evaluation board layout has been optimized
for performance by using basic analog circuit
techniques, The four charge-pump capacitors
must be 22µF (16V) and be placed as close to the
unit as possible; tantalum capacitors are suggested. The decoupling capacitor must be a
minimum of 1µF; depending upon the operating
environment, 10µF should be enough for worst
case situations. The ground plane for the part
must be solid, extending completely under the
package. The power supplies for the device
should be as accurate as possible; for rated
performance ±5% is necessary. The power supply current will vary depending upon the selected mode, the amount of loading and the data
rate. As a maximum, the user should reserve
200mA for ICC. The worst-case operating mode
is RS-485 under full load of six (6) drivers
supplying 1.6V to 54Ω loads. The power and
ground inputs can be supplied through either the
banana jacks on the evaluation board (Red = VCC
= +5V±5%; Black = GND) or through the connector.
The transceiver I/O lines are brought out to test
pins arranged in the same configuration as shown
elsewhere in this data sheet. A top layer
silk-screen shows the drivers and receivers to
allow direct correlation to the data sheet. The
transmitter and receiver decode bits are tied
together and are brought out to a DIP switch for
manual control of both the driver and receiver
interface modes. Since the coding for the drivers
and receivers is identical, the bits have been tied
together. The DIP switch has 7 positions, four of
which are reserved for the TDEC/RDEC control
and the other three are used as tri-state control
pins. The labels that are in [brackets] apply only
Date: 7/29/04
For reference, the 80-pin QFP Socket is a
TESCO part number FPQ-80-65-09A. The
50-pin connector is an AMP part number
749075-5.
SP503 Multiprotocol Transceiver
20
© Copyright 2004 Sipex Corporation
Figure 13. SP502/503 Evaluation Board Schematic
Date: 7/29/04
SP503 Multiprotocol Transceiver
21
© Copyright 2004 Sipex Corporation
Figure 14a. Evaluation Board — Top Layers
Date: 7/29/04
SP503 Multiprotocol Transceiver
22
© Copyright 2004 Sipex Corporation
Figure 14b. Evaluation Board — Bottom Layers
Date: 7/29/04
SP503 Multiprotocol Transceiver
23
© Copyright 2004 Sipex Corporation
Figure 15. External Transient Suppressors
Date: 7/29/04
SP503 Multiprotocol Transceiver
24
© Copyright 2004 Sipex Corporation
1
2
3
4
5
6
7
26 27 28 29 30 31 32
EDGE
CONNECTOR
01
02
03
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TxD (pin 14) –TTL Input – Transmit
data; source for SD(a) and SD(b) outputs.
DTR (pin 13) – TTL Input – Data
terminal ready: source for TR(a) and
TR(b) outputs.
ST/TT (pin 6) –TTL Input – ST/TT
select pin; enables ST drivers and disables TT drivers when high. Disables
ST drivers and enables TT drivers when
low.
04
DEC3/RDEC3 (pin 5) – TTL Input –
Transmitter/Receiver decode register.
05
TDEC2/RDEC2 (pin 4) – TTL Input –
Transmitter/Receiver decode register.
06
TDEC1/RDEC1 (pin 3) – TTL Input –
Transmitter/Receiver decode register.
07
TDEC0/RDEC0 (pin 2) – TTL Input –
Transmitter/Receiver decode register.
08
RxD (pin 1 ) – TTL Output – Receive
data; sourced from RD(a) and RD)b)
inputs.
09
CTS (pin 80) – TTL Output – Clear to
send; sourced from CS(a) and CS(b)
inputs.
10
11
12
Date: 7/29/04
EDGE
CONNECTOR
DUT PIN
DESCRIPTIONS
RxT (pin 79) – TTL Output – RxT;
sourced from TT(a), TT(b) inputs.
DSR (pin 78) – TTL Output – Data set
ready; sourced from DM(a) and DM(b)
inputs.
RD(b) (pin 71) – Analog In – Receive
data, non–inverted; source for RxD.
13
RD(a) (pin 70) – Analog In – Receive
data, inverted: source for RxD.
14
DM(b) (pin 69) – Analog In – Data
mode, non–inverted; source for DSR.
l5
DM(a) (pin 68) – Analog In – Data
mode, inverted; source for DSR.
16
CS(b) (pin 67) – Analog In – Clear to
send; non–inverted; source for CTS.
17
CS(a) (pin 66) – Analog In – Clear to
send, inverted; source for CTS.
18
TT(b) (pin 65) – Analog Out –
Terminal timing, non–inverted:
sourced from TxC input.
19
TT(a) (pin 63) – Analog Out –
Terminal timing; inverted: sourced
from TxC input.
20
TR(a) (pin 58) – Analog Out – Terminal ready, inverted; sourced from DTR.
21
TR(b) (pin 56) – Analog Out – Terminal ready; non–inverted; sourced from
DTR.
22
SD(a) (pin 61) – Analog Out – Send
data, inverted; sourced from TxD.
23
SD(b) (pin 59) – Analog Out – Send
data; non–inverted; sourced from TxD.
24
RS(a) (pin 54) – Analog Out – Ready to
send; inverted; sourced from RTS.
25
RS(b) (pin 52) – Analog Out – Ready
to send, non–inverted; sourced from
RTS.
SP503 Multiprotocol Transceiver
25
DUT PIN
DESCRIPTIONS
© Copyright 2004 Sipex Corporation
1
2
3
4
5
6
7
26 27 28 29 30 31 32
EDGE
CONNECTOR
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DUT PIN
DESCRIPTIONS
26
ST (pin 22) – TTL Input – Send Timing; source for ST(a) and ST(b) outputs. SP503 only.
27
STEN (pin 23) – TTL Input — Driver
enable control pin; active low. SP503
only,
28
SCT(a) (pin 76) – Analog Input – Inverting; input for SCT receiver; SP503
only.
29
SCT(b) (pin 77) – Analog Input – Non–
inverting; input for SCT receiver.
SP503 only.
30
VCC — +5V for all circuitry.
31
GND — signal and power ground.
EDGE
CONNECTOR
DUT PIN
DESCRIPTIONS
39
IC(a) (pin 39) – Analog In – Incoming
call; inverted; source for Rl.
40
RT(b) (pin 38) – Analog In – Receive
timing, non–inverted; source for RxC.
41
RT(a) (pin 37) – Analog In – Receive
timing; inverted; source from RxC.
42
RR(b) (pin 36) – Analog In – Receiver
ready; non–inverted; source for DCD.
43
RR(a) (pin 35) – Analog In – Receiver
ready; inverted; source for DCD.
44
LL (pin 24) – TTL Input – Local
loopback; source for LL(a) and LL(b)
outputs.
45
Rl (pin 21) – TTL Output – Ring
indicator; sourced from IC(a) and IC(b)
inputs.
32 LL(a) (pin 51) – Analog Out – Local
loopback, inverted; sourced from LL.
33
LL(b) (pin 49) – Analog Out – Local
loopback, non–inverted sourced from
LL.
46
RxC (pin 20) – TTL Output – Receive
clock; sourced from RT(a) and RT(b)
inputs.
34
RL(a) (pin 47) – Analog Out – Remote
loopback; inverted; sourced from RL.
47
35
RL(b) (pin 45) – Analog Out – Remote
loopback; non–inverted; sourced from
RL.
DCD (pin 19) – TTL Output – Data
carrier detect; sourced from RR(a) and
RR(b) inputs.
48
ST(b) (pin 44) – Analog Out – Send
timing, non–inverted; sourced from
TxC.
RL (pin 17) – Analog Out – Remote
loopback; source for RL(a) and RL(b)
outputs.
49
RTS (pin 16) – TTL Input – Ready to
send; source for RS(a) and RS(b) outputs.
50
TxC (pin 15) – TTL Input – Transmit
clock; source for TT(A) and TT(B)
outputs.
36
37
38
Date: 7/29/04
ST(a) (pin 42) – Analog Output –Send
timing, inverted; sourced from TxC.
IC(b) (pin 40) – Analog In – Incoming
call; non–inverted; source for Rl.
SP503 Multiprotocol Transceiver
26
© Copyright 2004 Sipex Corporation
PACKAGE: 80 PIN MQFP
D
D1
D2
0.30" RAD. TYP.
PIN 1
c
0.20" RAD. TYP.
E1
E
E2
CL
5°-16°
0° MIN.
0°–7°
5°-16°
CL
L
L1
A2
A
b
A1
e
DIMENSIONS
Minimum/Maximum
(mm)
SYMBOL
Seating
Plane
80–PIN MQFP
JEDEC MS-22
(BEC) Variation
MIN
NOM
A
COMMON DIMENTIONS
MAX
SYMBL MIN
2.45
A1
0.00
A2
1.80
b
0.22
2.00
c
0.11
0.25
L
0.73
2.20
L1
NOM
MAX
23.00
0.88
1.03
1.60 BASIC
0.40
D
17.20 BSC
D1
14.00 BSC
D2
12.35 REF
E
17.20 BSC
E1
14.00 BSC
E2
12.35 REF
e
0.65 BSC
N
80
80 PIN MQFP (MS-022 BC)
Date: 7/29/04
SP503 Multiprotocol Transceiver
27
© Copyright 2004 Sipex Corporation
PACKAGE: 80 PIN LQFP
D
D1
R2
PIN 1
R1
ø2
E1
CL
E
ø1
ø
ø3
CL
L
L1
A1
A
b
e
A1
Seating
Plane
DIMENSIONS
Minimum/Maximum
(mm)
SYMBOL
A
A1
A2
b
80–PIN LQFP
JEDEC MS-026
(BEC) Variation
MIN
MAX
NOM
1.40
0.05
1.35
0.22
1.60
0.15
1.40
0.32
D
16.00 BSC
D1
e
14.00 BSC
0.65 BSC
E
16.00 BSC
14.00 BSC
E1
L
1.45
0.38
0.45
0.75
1.00 REF
L1
ø
0º
3.5º
7º
ø1
0º
-
-
ø2
11º
12º
13º
ø3
11º
12º
13º
R1
0.08
-
-
R2
0.08
-
0.20
80 PIN LQFP
Date: 7/29/04
SP503 Multiprotocol Transceiver
28
© Copyright 2004 Sipex Corporation
ORDERING INFORMATION
Part Number
Top Mark
Temperature Range
Package Types
SP503CF ............. SP503CFYYWW......0°C to +70°C ............................ 80–pin JEDEC (MS-022 BC) MQFP
SP503EF.............SP503EFYYWW......-40°C to +85°C .......................... 80–pin JEDEC (MS-022 BC) MQFP
SP503EM.............SP503EMYYWW......-40°C to +85°C .......................... 80–pin JEDEC (MS-022 BC) LQFP
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP503EF = standard; SP503EF-L = lead free
REVISION HISTORY
DATE
1/27/04
5/6/04
7/29/04
REVISION
A
B
C
DESCRIPTION
Implemented tracking revision.
Added Top Mark to ordering information.
Included LQFP package option.
Corporation
ANALOG EXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.
Date: 7/29/04
SP503 Multiprotocol Transceiver
29
© Copyright 2004 Sipex Corporation