SIPEX SP504MCF

®
SP504
WAN Multi-Mode Serial Transceiver
■ +5V Only
■ Seven (7) Drivers and Seven (7) Receivers
■ Driver and Receiver Tri-State Control
■ Reduced V.35 Termination Network
■ Pin Compatible with the SP503
■ Software Selectable Interface Modes:
-RS-232E (V.28)
-RS-422A (V.11, X.21)
-RS-449 (V.11 & V.10)
-RS-485
-V.35
-EIA-530 (V.11 & V.10)
-EIA-530A (V.11 & V.10)
-V.36
DESCRIPTION...
The SP504 is a single chip device that supports eight (8) physical serial interface standards
for Wide Area Network Connectivity. The SP504 is fabricated using a low power BiCMOS
process technology, and incorporates a Sipex patented (5,306,954) charge pump allowing
+5V only operation. Seven (7) drivers and seven (7) receivers can be configured via software
for any of the above interface modes at any time. The SP504 is suited for DTE–DCE
applications. The SP504 requires only one external resistor per V.35 driver for compliant V.35
operation.
Vcc
SWITCHABLE V.35
TERMINATION RESISTOR
NETWORKS
22µF, 16V
22µF, 16V
RxD
RXC
CTS
DSR
DCD
RI
SCT
Vdd
C1C2+
Programmable Charge Pump
Vss
22µF, 16V
C2-
RxD
TxD
TxD
DTR
DTR
RTS
RTS
RL
RL
LL
LL
ST
ST
TT
TT
RxC
CTS
SP504
DSR
DCD
RI
SCT
Receiver Decode
Rev: A Date:1/27/04
22µF, 16V
C1+
Driver Decode
SP504 Multi–Mode Serial Transceivers
1
© Copyright 2004 Sipex Corporation
SPECIFICATIONS
TA = +25°C and VCC = +5.0V unless otherwise noted.
MIN.
LOGIC INPUTS
VIL
VIH
LOGIC OUTPUTS
VOL
VOH
RS-485 DRIVER
TTL Input Levels
VIL
VIH
Outputs
HIGH Level Output
LOW Level Output
Differential Output
Balance
Offset
Open Circuit Voltage
Output Current
Short Circuit Current
Transition Time
Max. Transmission Rate
Propagation Delay
tPHL
tPLH
Differential Driver Skew
RS-485 RECEIVER
TTL Output Levels
VOL
VOH
Input
HIGH Threshold
LOW Threshold
Common Mode Range
HIGH Input Current
LOW Input Current
Receiver Sensitivity
Input Impedance
Max. Transmission Rate
Propagation Delay
tPHL
tPLH
Differential Receiver Skew
V.35 DRIVER
TTL Input Levels
VIL
VIH
Outputs
Differential Output
Source Impedance
Short-Circuit Impedance
Voltage Output Offset
Transition Time
Max. Transmission Rate
Rev: A Date:1/27/04
TYP.
MAX.
UNITS
0.8
Volts
Volts
0.4
Volts
Volts
0.8
Volts
Volts
+6.0
Volts
Volts
Volts
Volts
Volts
Volts
mA
mA
ns
Mbps
2.0
2.4
2.0
–0.3
±1.5
±5.0
±0.2
+2.5
±6.0
28.0
±250
20
40
80
80
20
100
100
40
ns
ns
ns
0.4
Volts
Volts
+12
–0.2
+12.0
Volts
Volts
Volts
10
50
50
2.4
+0.2
–7.0
–7.0
±0.2
12
10
80
80
kΩ
Mbps
110
110
30
100
150
35
IOUT= +3.2mA
IOUT= –1.0mA
RL=54Ω, CL=50pF
|VT| - |VT|
RL=54Ω
Terminated in –7V to +10V
Rise/fall time, 10%–90%
RL=54Ω; Figure 3a
TA @ 25°C & VCC = +5V only
Figures 3a and 5; RL=54Ω
CL=50pF
| tPHL – tPLH |; TA @ +25°C
(a)-(b)
(a)-(b)
Refer to Rec. input graph
Refer to Rec. input graph
Over –7V to +12V common
mode range
Figure 3a
TA = 25°C & VCC = +5V only
Figures 3a and 7; A is inverting and B is non-inverting.
| tPHL – tPLH |; TA @ +25°C
180
180
ns
ns
ns
0.8
Volts
Volts
±0.66
150
165
+0.6
60
Volts
Ω
Ω
VOUT = –2V to +2V; A = B
ns
Mbps
48kbps data rate.; TA@ 25°C
RL=100Ω
2.0
±0.44
50
135
–0.6
Volts
CONDITIONS
10
SP504 Multi–Mode Serial Transceivers
2
All outputs measured w/
150Ω termination resistor
connected to the noninverting outputs as shown
in Figure 18.
RL=100Ω
© Copyright 2004 Sipex Corporation
SPECIFICATIONS (Continued)
TA = +25°C and VCC = +5.0V unless otherwise noted.
V.35 DRIVER
Propagation Delay
tPHL
tPLH
Differential Driver Skew
V.35 RECEIVER
TTL Output Levels
VOL
VOH
Input
Differential Threshold
Input Impedance
Short-Circuit Impedance
Max. Transmission Rate
Propagation Delay
tPHL
tPLH
Differential Receiver Skew
RS-422 DRIVER (V.11)
TTL Input Levels
VIL
VIH
Outputs
Open Circuit Voltage,VO
Differential Output, VT
Balance
Offset
Short Circuit Current
Power Off Current
Transition Time
Max. Transmission Rate
Propagation Delay
tPHL
tPLH
Differential Driver Skew
RS-422 RECEIVER (V.11)
TTL Output Levels
VOL
VOH
Input
HIGH Threshold
LOW Threshold
Common Mode Range
HIGH Input Current
LOW Input Current
Receiver Sensitivity
Input Impedance
Max. Transmission Rate
Propagation Delay
tPHL
tPLH
Differential Receiver Skew
RS-232 DRIVER (V.28)
TTL Input Level
VIL
VIH
Rev: A Date:1/27/04
MIN.
TYP.
MAX.
50
50
80
80
30
100
100
40
ns
ns
ns
0.4
Volts
Volts
2.4
90
135
10
100
100
±80
100
150
130
130
30
110
165
ns
ns
ns
0.8
Volts
Volts
20
±6.0
±5.0
0.67VO
±0.4
+3.0
±150
±100
40
Volts
Volts
Volts
Volts
Volts
mA
µA
ns
Mbps
80
80
20
100
100
40
ns
ns
ns
0.4
Volts
Volts
+6.0
–0.2
+7.0
Volts
Volts
Volts
±2.0
0.5VO
10
2.4
+0.2
–6.0
–7.0
±0.3
Volts
kΩ
Mbps
180
180
ns
ns
ns
0.8
Volts
Volts
4
10
80
80
mV
Ω
Ω
Mbps
200
200
2.0
50
50
UNITS
110
110
30
2.0
SP504 Multi–Mode Serial Transceivers
3
CONDITIONS
TA @ 25°C & VCC = +5V only
Figures 3b and 5
| tPHL – tPLH |; TA @ +25°C
VIN = +2V to –2V
TA @ 25°C & VCC = +5V only
Figure 3b and 7; A is inverting and B is non-inverting.
| tPHL – tPLH |; TA @ +25°C
RL=3.9kΩ
RL=100Ω
TA @ +25°C
|VT| – |VT|
Vout = 0V
Vcc = 0V, Vout = ±0.25V
Rise/fall time, 10%-90%
RL=100Ω; Figure 3a
TA @ 25°C & VCC = +5V only
Figure 3a and 5;
RDIFF=100Ω
| tPHL – tPLH |; TA @ +25°C
(a)-(b)
(a)-(b)
Refer to Rec. input graph
Refer to Rec. input graph
VCM = +7V to –7V
VIN = +10V to –10V
TA @ 25°C & VCC = +5V only
Figure 3a and 7; A is inverting and B is non-inverting.
| tPHL – tPLH |; TA @ +25°C
© Copyright 2004 Sipex Corporation
SPECIFICATIONS (Continued)
TA = +25°C and VCC = +5.0V unless otherwise noted.
MIN.
RS-232 DRIVER (V.28)
Outputs
HIGH Level Output
LOW Level Output
Open Circuit Voltage
Short Circuit Current
Power Off Impedance
Slew Rate
TYP.
+5.0
–15.0
–15
Short Circuit Current
Power Off Current
Transition Time
Max. Transmission Rate
Propagation Delay
tPHL
tPLH
RS-423 RECEIVER (V.10)
TTL Output Levels
VOL
VOH
Input
HIGH Threshold
LOW Threshold
HIGH Input Current
LOW Input Current
Receiver Sensitivity
Input Impedance
Max. Transmission Rate
Rev: A Date:1/27/04
UNITS
CONDITIONS
+15
–5.0
+15
±100
Volts
Volts
Volts
mA
Ω
V/µs
RL=3kΩ, VIN=0.8V
RL=3kΩ, VIN=2.0V
300
30
Transition Time
Max. Transmission Rate
Propagation Delay
tPHL
tPLH
RS-232 RECEIVER (V.28)
TTL Output Levels
VOL
VOH
Input
HIGH Threshold
LOW Threshold
Receiver Open Circuit Bias
Input Impedance
Max. Transmission Rate
Propagation Delay
tPHL
tPLH
RS-423 DRIVER (V.10)
TTL Input Levels
VIL
VIH
Output
Open Circuit Voltage, VO
HIGH Level Output, VT
LOW Level Output, VT
MAX.
1.56
120
230.4
0.5
0.5
1
1
kbps
4
4
1.7
1.2
3
120
5
230.4
0.05
0.05
0.25
0.25
Volts
Volts
3.0
Volts
Volts
Volts
kΩ
kbps
+2.0
7
1
1
Volts
Volts
±6.0
+6.0
–3.6
Volts
Volts
Volts
Volts
mA
µA
ns
kbps
±150
±100
100
120
0.05
0.05
0.5
0.5
2
2
µs
µs
0.4
Volts
Volts
+7.0
–0.3
Volts
Volts
2.4
+0.3
–7.0
µs
µs
0.8
2.0
±4.0
+3.6
–6.0
0.9VOC
µs
µs
0.4
2.4
0.8
µs
±0.3
4
120
Volts
kΩ
kbps
SP504 Multi–Mode Serial Transceivers
4
VOUT = 0V
Vcc = 0V, Vout = ±2.0V
RL=3kΩ, CL= 50pF
VCC = +5.0V, TA @ +25°C
RL=3kΩ, CL=2500pF ;
between ±3V, TA @ +25°C
RL=3kΩ, CL=2500pF
TA @ 25°C & VCC = +5V only
Measured from 1.5V of VIN
to 50% of VOUT; RL=3kΩ
VIN = +15V to –15V
TA @ 25°C & VCC = +5V only
Measured from 50% of VIN
to 1.5V of VOUT.
RL=3.9kΩ
RL=450Ω; VOUT ≥ 0.9VOC
RL=450Ω; VOUT ≥ 0.9VOC
TA =+25˚C,, VCC = +5.0V
VOUT = 0V, VCC = +5.0V
VCC = 0V, VOUT= ±0.25V
Rise/fall time, between ±3V
RL=450Ω
TA @ 25°C & VCC = +5V only
Measured from 1.5V of VIN
to 50% of VOUT; RL=450Ω
Refer to Rec. input graph
Refer to Rec. input graph
VCM = +7V to –7V
VIN = +10V to –10V
© Copyright 2004 Sipex Corporation
SPECIFICATIONS (Continued)
TA = +25°C and VCC = +5.0V unless otherwise noted.
RS-423 RECEIVER (V.10)
Propagation Delay
tPHL
tPLH
POWER REQUIREMENTS
VCC
ICC (no interface selected)
(RS-232 Mode)
(RS-422 Mode)
(RS-449 Mode)
(EIA-530 Mode)
(EIA-530A Mode)
(RS-485 Mode)
(V.35 Mode)
(V.36 Mode)
MIN.
TYP.
MAX.
0.05
0.05
0.2
0.2
1
1
4.75
5.00
30
140
320
320
320
320
370
210
310
5.25
UNITS
µs
µs
Volts
mA
mA
mA
mA
mA
mA
mA
mA
mA
ENVIRONMENTAL AND MECHANICAL
Operating Temperature Range
0
+70
Storage Temperature Range
–65
+150
Package
80–pin QFP
CONDITIONS
TA @ 25°C & VCC = +5V only
Measured from 50% of VIN
to 1.5V of VOUT
VCC =5.0V
fIN = 120kbps. Drivers loaded.
fIN = 2Mbps. Drivers loaded.
fIN = 2Mbps. Drivers loaded.
fIN = 2Mbps. Drivers loaded.
fIN = 2Mbps. Drivers loaded.
fIN = 2Mbps. Drivers loaded.
fIN = 2Mbps. Drivers loaded.
fIN = 2Mbps. Drivers loaded.
°C
°C
RECEIVER INPUT GRAPHS
RS-423 RECEIVER
RS-422 RECEIVER
+3.25mA
+3.25mA
–10V
–10V
–3V
+3V
–3V
+3V
+10V
+10V
Maximum Input Current
versus Voltage
Maximum Input Current
versus Voltage
–3.25mA
–3.25mA
RS-485 RECEIVER
+1.0mA
–7V
–3V
+6V
1 Unit Load
Maximum Input Current
versus Voltage
–0.6mA
Rev: A Date:1/27/04
+12V
SP504 Multi–Mode Serial Transceivers
5
© Copyright 2004 Sipex Corporation
ABSOLUTE MAXIMUM RATINGS
Package Derating:
øJA....................................................46 °C/W
øJC...................................................16 °C/W
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may
affect reliability.
STORAGE CONSIDERATIONS
Due to the relatively large package size of the 80-pin
quad flat-pack, storage in a low humidity environment
is preferred. Large high density plastic packages are
moisture sensitive and should be stored in Dry Vapor
Barrier Bags. Prior to usage, the parts should remain
bagged and stored below 40°C and 60%RH. If the
parts are removed from the bag, they should be used
within 48 hours or stored in an environment at or below
20%RH. If the above conditions cannot be followed,
the parts should be baked for four hours at 125°C in
order remove moisture prior to soldering. Sipex ships
the 80-pin QFP in Dry Vapor Barrier Bags with a
humidity indicator card and desiccant pack. The humidity indicator should be below 30%RH.
VCC............................................................................+7V
Input Voltages:
Logic...............................-0.3V to (VCC+0.5V)
Drivers............................-0.3V to (VCC+0.5V)
Receivers...........................................±15V
Output Voltages:
Logic................................-0.3V to (VCC+0.5V)
Drivers................................................±14V
Receivers........................-0.3V to (VCC+0.5V)
Storage Temperature..........................-65˚C to +150˚C
Power Dissipation.........................................2000mW
OTHER AC CHARACTERISTICS
TA = +70°C to 0°C and VCC = +4.75V to +5.25V unless otherwise noted.
PARAMETER
MIN.
TYP.
MAX.
UNITS
DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE
RS-232 MODE
tPZL; Tri-state to Output LOW
0.70
5.0
µs
tPZH; Tri-state to Output HIGH
0.40
2.0
µs
tPLZ; Output LOW to Tri-state
0.20
2.0
µs
tPHZ; Output HIGH to Tri-state
0.40
2.0
µs
RS-423 MODE
tPZL; Tri-state to Output LOW
0.15
2.0
µs
tPZH; Tri-state to Output HIGH
0.20
2.0
µs
tPLZ; Output LOW to Tri-state
0.20
2.0
µs
tPHZ; Output HIGH to Tri-state
0.15
2.0
µs
RS-422, RS-485 MODES
tPZL; Tri-state to Output LOW
2.80
10.0
µs
tPZH; Tri-state to Output HIGH
0.10
2.0
µs
tPLZ; Output LOW to Tri-state
0.10
2.0
µs
tPHZ; Output HIGH to Tri-state
0.10
2.0
µs
V.35 MODE
tPZL; Tri-state to Output LOW
2.60
10.0
µs
tPZH; Tri-state to Output HIGH
0.10
2.0
µs
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
6
CONDITIONS
CL = 100pF, Fig. 4 ; S2
closed
CL = 100pF, Fig. 4 ; S2
closed
CL = 100pF, Fig. 4 ; S2
closed
CL = 100pF, Fig. 4 ; S2
closed
CL = 100pF, Fig. 4 ; S2
closed
CL = 100pF, Fig. 4 ; S2
closed
CL = 100pF, Fig. 4 ; S2
closed
CL = 100pF, Fig. 4 ; S2
closed
CL = 100pF, Fig. 4 & 6; S1
closed
CL = 100pF, Fig. 4 & 6; S2
closed
CL = 15pF, Fig. 4 & 6; S1
closed
CL = 15pF, Fig. 4 & 6; S2
closed
CL = 100pF, Fig. 4 & 6; S1
closed
CL = 100pF, Fig. 4 & 6; S2
closed
© Copyright 2004 Sipex Corporation
OTHER AC CHARACTERISTICS (Continued)
TA = +70°C to 0°C and VCC = +4.75V to +5.25V unless otherwise noted.
PARAMETER
V.35 MODE
tPLZ; Output LOW to Tri-state
MIN.
tPHZ; Output HIGH to Tri-state
TYP.
MAX.
UNITS
CONDITIONS
0.10
2.0
µs
2.0
µs
CL = 15pF, Fig. 4 & 6; S1
closed
CL = 15pF, Fig. 4 & 6; S2
closed
0.15
RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE
RS-232 MODE
tPZL; Tri-state to Output LOW
0.12
2.0
µs
CL = 100pF, Fig. 2 ; S1
closed
tPZH; Tri-state to Output HIGH
0.10
2.0
µs
CL = 100pF, Fig. 2 ; S2
closed
tPLZ; Output LOW to Tri-state
0.10
2.0
µs
CL = 100pF, Fig. 2 ; S1
closed
tPHZ; Output HIGH to Tri-state
0.10
2.0
µs
CL = 100pF, Fig. 2 ; S2
closed
RS-423 MODE
tPZL; Tri-state to Output LOW
0.10
2.0
µs
CL = 100pF, Fig. 2 ; S1
closed
tPZH; Tri-state to Output HIGH
0.10
2.0
µs
CL = 100pF, Fig. 2 ; S2
closed
tPLZ; Output LOW to Tri-state
0.10
2.0
µs
CL = 100pF, Fig. 2 ; S1
closed
tPHZ; Output HIGH to Tri-state
0.10
2.0
µs
CL = 100pF, Fig. 2 ; S2
closed
RS-422/RS-485 MODES
tPZL; Tri-state to Output LOW
0.10
2.0
µs
CL = 100pF, Fig. 2 & 8 ; S1
closed
tPZH; Tri-state to Output HIGH
0.10
2.0
µs
CL = 100pF, Fig. 2 & 8 ; S2
closed
tPLZ; Output LOW to Tri-state
0.10
2.0
µs
CL = 15pF, Fig. 2 & 8 ; S1
closed
tPHZ; Output HIGH to Tri-state
0.10
2.0
µs
CL = 15pF, Fig. 2 & 8; S2
closed
V.35 MODE
tPZL; Tri-state to Output LOW
0.10
2.0
µs
CL = 100pF, Fig. 2 & 8; S1
closed
tPZH; Tri-state to Output HIGH
0.10
2.0
µs
CL = 100pF, Fig. 2 & 8; S2
closed
tPLZ; Output LOW to Tri-state
0.10
2.0
µs
CL = 15pF, Fig. 2 & 8; S1
closed
tPHZ; Output HIGH to Tri-state
0.10
2.0
µs
CL = 15pF, Fig. 2 & 8; S2
closed
TRANSCEIVER TO TRANSCEIVER SKEW
RS-232 Driver
RS-232 Receiver
RS-422 Driver
RS-422 Receiver
RS-423 Driver
RS-423 Receiver
V.35 Driver
V.35 Receiver
Rev: A Date:1/27/04
[ (tphl – tplh)Trcvr1 – (tphl – tplh)TrcvrX ]
20
50
ns
VCC = +5.0V, TA @ +25°C
20
ns
20
50
ns
VCC = +5.0V, TA @ +25°C
20
ns
20
50
ns
VCC = +5.0V, TA @ +25°C
20
ns
20
50
ns
VCC = +5.0V, TA @ +25°C
20
ns
SP504 Multi–Mode Serial Transceivers
7
© Copyright 2004 Sipex Corporation
A
VOD
VCC
S1
CRL
R
1KΩ
Test Point
Receiver
Output
R
1KΩ
VOC
S2
B
Figure 1. Driver DC Test Load Circuit
CL1
DI
A
RL
Figure 2. Receiver Timing Test Load Circuit
A
DI
RO
B
A
B
B
RO
B
CL2
A
15pF
15pF
Figure 3b. Timing Test Ckt. (V.35 mode only for SP504)
Figure 3a. Driver/Receiver Timing Test Circuit
Output
Under
Test
500Ω
S1
VCC
CL
S2
Figure 4. Driver Timing Test Load #2 Circuit
Note : Figures 3a and 3b shown above are used for evaluating maximum transmission rate. For 10Mbps transmission rate, an input signal of 5MHz is applied
to the driver input. In order for a valid transmission rate, the driver output must adhere to the output electrical specifications (VOH & VOL) and an
acceptable duty cycle for the protocol tested. The receiver outputs are checked for proper TTL/CMOS VOH & VOL levels and an acceptable output
duty cycle.
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
8
© Copyright 2004 Sipex Corporation
f = 1MHz; tR < 10ns; tF < 10ns
+3V
1.5V
DRIVER INPUT
1.5V
0V
A
DRIVER
OUTPUT
tPLH
tPHL
VO 1/2VO
1/2VO
B
DIFFERENTIAL VO+
OUTPUT 0V
VA – VB VO–
tSKEW
tSKEW
tF
tR
Figure 5. Driver Propagation Delays
f = 1MHz; tR < 10ns; tF < 10ns
+3V
TDECX
0V
1.5V
1.5V
tZL
tLZ
5V
2.3V
A, B
VOL
VOH
A, B
2.3V
0V
Output normally LOW
0.5V
Output normally HIGH
0.5V
tZH
tHZ
Figure 6. Driver Enable and Disable Times
f = 1MHz; tR ≤ 10ns; tF ≤ 10ns
VOD2+
0V
A–B
VOD2–
VOH
RECEIVER OUT
VOL
0V
INPUT
1.5V
1.5V
OUTPUT
tPHL
tPLH
Figure 7. Receiver Propagation Delays
Note : Figures 5 and 7 shown above are corrected from the original SP504 datahseet. Both figures were incorrect on the original datasheet where the
driver output from Figure 5 and the receiver output from Figure 7 are inverted signals.
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
9
© Copyright 2004 Sipex Corporation
+3V
RDECX
0V
5V
RECEIVER OUT
VIL
1.5V
f = 1MHz; tR < 10ns; tF < 10ns
tZL
1.5V
1.5V
tLZ
Output normally LOW
0.5V
Output normally HIGH
0.5V
VIH
RECEIVER OUT
0V
1.5V
tZH
tHZ
Figure 8. Receiver Enable and Disable Times
- 0V
DRIVER INPUT
- 0V
DRIVER INPUT
- 0V
- 0V
DRIVER OUTPUT
DRIVER OUTPUT
Figure 10. Typical RS-423 Driver Output Waveform
Figure 9. Typical RS-232 Driver Output Waveform
DRIVER INPUT
- 0V
- 0V
DRIVER INPUT
DRIVER OUTPUT
- 0V
- 0V
DRIVER OUTPUT
Figure 11. Typical RS-422/485 Driver Output Waveform
Rev: A Date:1/27/04
Figure 12. Typical V.35 Driver Output Waveform
SP504 Multi–Mode Serial Transceivers
10
© Copyright 2004 Sipex Corporation
Pin 61 — SD(a) — Analog Out — Send data,
inverted; sourced from TxD.
Pin 63 — TT(a) — Analog Out — Terminal
Timing, inverted; sourced from TxC
61 SD(a)
62 VCC
63 TT(a)
64 GND
65 TT(b)
66 CS(a)
67 CS(b)
68 DM(a)
69 DM(b)
70 RD(a)
71 RD(b)
72 GND
73 VCC
74 VCC
75 GND
76 SCT(a)
77 SCT(b)
78 DSR
79 SCT
80 CTS
PINOUT…
RxD 1
Pin 65 — TT(b) — Analog Out — Terminal
Timing, non–inverted; sourced from TxC.
60 GND
RDEC0 2
59 SD(b)
RDEC1 3
58 TR(a)
RDEC2 4
57 GND
RDEC3 5
56 TR(b)
Pin 70 — RD(a) — Receive Data, analog input;
inverted; source for RxD.
55 VCC
TTEN 6
SCTEN 7
54 RS(a)
53 GND
N/C 8
TDEC3 9
52 RS(b)
SP504
TDEC2 10
TDEC1 11
50 GND
49 LL(b)
DTR 13
TxD 14
48 VCC
47 RL(a)
Pin 76 — SCT(a) — Serial Clock Transmit;
analog input, inverted; source for SCT.
Pin 77 — SCT(b) — Serial Clock Transmit:
analog input, non–inverted; source for SCT
IC(b) 40
IC(a) 39
RT(b) 38
RT(a) 37
RR(b) 36
RR(a) 35
GND 34
VCC 33
41 VCC
VSS 32
42 ST(a)
RxC 20
GND 29
C1– 30
C2– 31
DCD 19
VDD 27
C2+ 28
43 GND
VCC 25
C1+ 26
44 ST(b)
LL 24
45 RL(b)
V35_STAT 18
RI 21
46 GND
RL 17
ST 22
TxC 15
RTS 16
STEN 23
Pin 71 — RD(b) — Receive Data; analog input;
non-inverted; source for RxD.
51 LL(a)
TDEC0 12
Pin 79 — SCT — Serial Clock Transmit; TTL
output; sources from SCT(a) and SCT(b) inputs.
PIN ASSIGNMENTS…
CLOCK AND DATA GROUP
Pin 1 — RxD — Receive Data; TTL output,
sourced from RD(a) and RD(b) inputs.
CONTROL LINE GROUP
Pin 13 — DTR — Data Terminal Ready; TTL
input; source for TR(a) and TR(b) outputs.
Pin 16 — RTS — Ready To Send; TTL input;
source for RS(a) and RS(b) outputs.
Pin 14 — TxD — TTL input ; transmit data
source for SD(a) and SD(b) outputs.
Pin 17 — RL — Remote Loopback; TTL input;
source for RL(a) and RL(b) outputs.
Pin 15 — TxC — Transmit Clock; TTL input for
TT driver outputs.
Pin 18 — V35_STAT — V.35 Status; TTL
output; outputs logic high when in V.35 mode.
Pin 20 — RxC — Receive Clock; TTL output
sourced from RT(a) and RT(b) inputs.
Pin 19 — DCD— Data Carrier Detect; TTL
output; sourced from RR(a) and RR(b) inputs.
Pin 22 — ST — Send Timing; TTL input; source
for ST(a) and ST(b) outputs.
Pin 21 — RI — Ring Indicate; TTL output;
sourced from IC(a) and IC(b) inputs.
Pin 37 — RT(a) — Receive Timing; analog
input, inverted; source for RxC.
Pin 24 — LL — Local Loopback; TTL input;
source for LL(a) and LL(b) outputs.
Pin 38 — RT(b) — Receive Timing; analog
input, non-inverted; source for RxC.
Pin 35 — RR(a)— Receiver Ready; analog
input, inverted; source for DCD.
Pin 42 — ST(a) — Send Timing; analog output,
inverted; sourced from ST.
Pin 36 — RR(b)— Receiver Ready; analog
input, non-inverted; source for DCD.
Pin 44 — ST(b) — Send Timing; analog output,
non-inverted; sourced from ST.
Pin 39 — IC(a)— Incoming Call; analog input,
inverted; source for RI.
Pin 59 — SD(b) — Analog Out — Send data,
non-inverted; sourced from TxD.
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
11
© Copyright 2004 Sipex Corporation
Pin 40 — IC(b)— Incoming Call; analog
input,non-inverted; source for RI.
Pins 12–9 — TDEC0 – TDEC3 — Transmitter
decode register; configures transmitter modes;
TTL inputs.
Pin 45 — RL(b) — Remote Loopback; analog
output, non-inverted; sourced from RL.
Pin 23 — STEN — Enables ST driver; active
low; TTL input.
Pin 47 — RL(a) — Remote Loopback; analog
output inverted; sourced from RL.
POWER SUPPLIES
Pins 25, 33, 41, 48, 55, 62, 73, 74 — VCC — +5V
input.
Pin 49— LL(b) — Local Loopback; analog
output, non-inverted; sourced from LL.
Pin 51 — LL(a) — Local Loopback; analog
output, inverted; sourced from LL.
Pins 29, 34, 43, 46, 50, 53, 57, 60, 64, 72, 75 —
GND — Ground.
Pin 52 — RS(b) — Ready To Send; analog
output, non-inverted; sourced from RTS.
Pin 27 — VDD +10V Charge Pump Capacitor —
Connects from VDD to VCC. Suggested capacitor size is 22µF, 16V.
Pin 54 — RS(a) — Ready To Send; analog
output, inverted; sourced from RTS.
Pin 32 — VSS –10V Charge Pump Capacitor —
Connects from ground to VSS. Suggested capacitor size is 22µF, 16V.
Pin 56 — TR(b) — Terminal Ready; analog
output, non-inverted; sourced from DTR.
Pin 58 — TR(a) — Terminal Ready; analog
output, inverted; sourced from DTR.
Pins 26 and 30 — C1+ and C1– — Charge Pump
Capacitor — Connects from C1+ to C1–. Suggested capacitor size is 22µF, 16V.
Pin 66 — CS(a)— Clear To Send; analog input,
inverted; source for CTS.
Pins 28 and 31 — C2+ and C2– — Charge Pump
Capacitor — Connects from C2+ to C2–. Suggested capacitor size is 22µF, 16V.
Pin 67 — CS(b)— Clear To Send; analog input,
non-inverted; source for CTS.
Pin 68 — DM(a)— Data Mode; analog input,
inverted; source for DSR.
NOTE: NC pins should be left floating; internal
signals may be present.
Pin 69 — DM(b)— Data Mode; analog input,
non-inverted; source for DSR
Pin 78 — DSR— Data Set Ready; TTL output;
sourced from DM(a), DM(b) inputs.
Pin 80 — CTS— Clear To Send; TTL output;
sourced from CS(a) and CS(b) inputs.
CONTROL REGISTERS
Pins 2–5 — RDEC0 – RDEC3 — Receiver
decode register; configures receiver modes; TTL
inputs.
Pin 6 — TTEN — Enables TT driver, active
low; TTL input.
Pin 7 — SCTEN — Enables SCT receiver;
active high; TTL input.
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
12
© Copyright 2004 Sipex Corporation
FEATURES…
The SP504 is a highly integrated serial transceiver that allows software control of its interface modes. Similar to the SP503, the SP504
offers the same hardware interface modes for
RS-232 (V.28), RS-422A (V.11), RS-449, RS485, V.35, EIA-530 and includes V.36 and
EIA-530A. The interface mode selection is done
via an 8–bit switch; four (4) bits control the
drivers and four (4) bits control the receivers.
The SP504 is fabricated using low power
BiCMOS process technology, and incorporates
a Sipex patented (5,306,954) charge pump
allowing +5V only operation. Each device is
packaged in an 80–pin JEDEC Quad FlatPack
package.
423 requires the voltage swing on the driver
output be between ±4V to ±6V during an open
circuit (no load). The charge pump would need
to be regulated down from ±10V to ±5V. A
typical ±10V charge pump would require external clamping such as 5V zener diodes on VDD
and VSS to ground. The ±5V output has symmetrical levels as in the ±10V output. The ±5V
is used in the following modes where RS-423
levels are used: RS-449, EIA-530, EIA-530A
and V.36.
Phase 1 (±10V)
— VSS charge storage — During this phase of
the clock cycle, the positive side of capacitors
C1 and C2 are initially charged to +5V. The Cl+
is then switched to ground and the charge on C1–
is transferred to C2–. Since C2+ is connected to
+5V, the voltage potential across capacitor C2 is
now 10V.
The SP504 is ideally suited for wide area network connectivity based on the interface modes
offered and the driver and receiver configurations. The SP504 has seven (7) independent
drivers and seven (7) independent receivers. In
V.35 mode, the SP504 includes the necessary
components and termination resistors internal
within the device for compliant V.35 operation.
Phase 1 (±5V)
— VSS & VDD charge storage and transfer —
With the C1 and C2 capacitors initially charged
to +5V, Cl+ is then switched to ground and the
charge on C1– is transferred to the VSS storage
capacitor. Simultaneously the C2– is switched to
ground and the 5V charge on C2+ is transferred
to the VDD storage capacitor.
THEORY OF OPERATION
The SP504 is made up of five separate circuit
blocks — the charge pump, drivers, receivers,
decoder and switching array. Each of these
circuit blocks is described in more detail below.
VCC = +5V
Charge–Pump
The SP504's charge pump design is based on the
SP503 where Sipex's patented charge pump
design (5,306,954) uses a four–phase voltage
shifting technique to attain symmetrical ±10V
power supplies. In addition, the SP504 charge
pump incorporates a "programmable" feature
that produces an output of ±10V or ±5V for VSS
and VDD depending on the mode of operation.
The charge pump still requires external capacitors to store the charge. Figure 17a shows the
waveform found on the positive side of capacitor C2, and Figure 17b shows the negative side
of capcitor C2. There is a free–running oscillator that controls the four phases of the voltage
shifting. A description of each phase follows.
+
C1
C2
–
–
+
VDD Storage Capacitor
–
–5V
+
–
VSS Storage Capacitor
C3
–5V
Figure 13a. Charge Pump Phase 1 for ±10V.
VCC = +5V
+5V
C4
+
C1
+
–
C2
–
+
VDD Storage Capacitor
–
–5V
–
+
VSS Storage Capacitor
C3
The SP504 charge pump is used for RS-232
where the output voltage swing is typically
±10V and also used for RS-423. However, RS-
Rev: A Date:1/27/04
C4
+5V
+
Figure 13b. Charge Pump Phase 1 for ±5V.
SP504 Multi–Mode Serial Transceivers
13
© Copyright 2004 Sipex Corporation
VCC = +5V
VCC = +5V
C4
C4
+
C1
+
C2
–
–
+
+
VDD Storage Capacitor
C1
–
–10V
+
–
+
C2
–
Figure 14b. Charge Pump Phase 2 for ±5V.
VCC = +5V
VCC = +5V
+5V
C4
+
C2
–
VSS Storage Capacitor
C3
Figure 14a. Charge Pump Phase 2 for ±10V.
C1
+
–
C3
+
VDD Storage Capacitor
–
–5V
VSS Storage Capacitor
–
+
C4
+10V
–
+
+
VDD Storage Capacitor
C1
–
+
–
C2
–
+
VDD Storage Capacitor
–
–5V
+
–
–5V
–
VSS Storage Capacitor
+
VSS Storage Capacitor
C3
C3
Figure 15. Charge Pump Phase 3.
Figure 16. Charge Pump Phase 4.
Phase 2 (±10V)
— VSS transfer — Phase two of the clock connects the negative terminal of C2 to the VSS
storage capacitor and the positive terminal of C2
to ground, and transfers the generated –l0V or
the generated –5V to C3. Simultaneously, the
positive side of capacitor C 1 is switched to +5V
and the negative side is connected to ground.
to the VSS storage capacitor. VSS receives a
continuous charge from either C1 or C2. With
the C1 capacitor charged to 5V, the cycle begins
again.
Phase 3
— VDD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C1 produces –5V in the negative
terminal of C1, which is applied to the negative
side of capacitor C2. Since C2+ is at +5V, the
voltage potential across C2 is l0V. For the 5V
output, C2+ is connected to ground so that the
potential on C2 is only +5V.
Phase 2 (±5V)
— VSS & VDD charge storage — C1+ is reconnected to VCC to recharge the C1 capacitor. C2+
is switched to ground and C2– is connected to C3.
The 5V charge from Phase 1 is now transferred
(a)
+5V
C2+
GND
(b)
GND
C2–
–5V
+10V
C2+
GND
GND
C2–
–10V
Figure 17. Charge Pump Waveforms
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
14
© Copyright 2004 Sipex Corporation
The RS-232 drivers are used in RS-232 mode
for all signals, and also in V.35 mode where they
are used as the control line signals such as DTR
and RTS.
Since both VDD and VSS are separately generated from VCC in a no–load condition, VDD and
VSS will be symmetrical. Older charge pump
approaches that generate V– from V+ will show
a decrease in the magnitude of V– compared to
V+ due to the inherent inefficiencies in the
design.
The RS-423 drivers are also single–ended signals with a minimum voltage output of ±3.6V
(with 450Ω loading) and can operate up to
120kbps. Open circuit VOL and VOH measurements are ±4.0V to ±6.0V. The RS-423 drivers
are used in RS-449, EIA-530, EIA-530A and
V.36 modes as Category II signals from each of
their corresponding specifications.
The clock rate for the charge pump typically
operates at 15kHz. The external capacitors must
be a minimum of 22µF with a 16V breakdown
rating.
External Power Supplies
For applications that do not require +5V only,
external supplies can be applied at the V+ and
V– pins. The value of the external supply voltages must be no greater than ±l0.5V. The tolerance should be ±5% from ±10V. The current
drain for the supplies is used for RS-232 and
RS-423 drivers. For the RS-232 driver, the current requirement will be 3.5mA per driver. The
RS-423 driver worst case current drain will be
11mA per driver. Power sequencing is required
for the SP504. The supplies must be sequenced
accordingly: +10V, +5V and –10V. An external
circuit would be needed for proper power supply sequencing. Consult factory for application
circuitry.
The third type of driver produces a differential
signal that can maintain RS-485, ±1.5V differential output levels with a worst case load of
54Ω. The signal levels and drive capability of
the RS-485 drivers allow the drivers to also
support RS-422 (V.11) requirements of ±2V
differential output levels with 100Ω loads. The
RS-422 drivers are used in RS-449, EIA-530,
EIA-530A and V.36 modes as Category I signals which are used for clock and data.
The fourth type of driver is the V.35 driver.
V.35 levels require ±0.55V driver output signals with a load of 100Ω. The SP504 drivers
simplify existing V.35 implementations that use
external termination schemes. The drivers were
specifically designed to comply with the requirements of V.35 as well as the driver output
impedance values of V.35. The drivers achieve
the 50Ω to 150Ω source impedance. However,
an external 150Ω resistor to ground must be
connected to the non-inverting outputs; SD(b),
ST(b), and TT(b), in order to comply with the
135Ω to 165Ω short-circuit impedance for V.35.
The V.35 driver itself is disabled and transparent when the decoder is in all other modes. All
of the differential drivers; RS-485, RS-422, and
V.35, can operate up to 10Mbps.
Drivers
The SP504 has seven (7) enhanced independent
drivers. Control for the mode selection is done
via a four–bit control word. The drivers are prearranged such that for each mode of operation,
the relative position and functionality of the
drivers are set up to accommodate the selected
interface mode. As the mode of the drivers is
changed, the electrical characteristics will change
to support the requirements of clock, data, and
control line signal levels. Table 1 shows the
mode of each driver in the different interface
modes that can be selected.
The driver inputs are both TTL or CMOS compatible. Since there are no pull-up or pull-down
resistors on the driver inputs, they should be tied
to a known logic state in order to define the
driver output.
There are four basic types of driver circuits —
RS-232, RS-423, RS-485 and V.35.
The RS-232 drivers output single–ended signals
with a minimum of ±5V (with 3kΩ and 2500pF
loading), and can operate up to 120kbps.
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
15
© Copyright 2004 Sipex Corporation
Receivers
The SP504 has seven (7) independent receivers
which can be programmed for the different
interface modes. Control for the mode selection
is done via a 4–bit control word that is independent from the driver control word. The coding
for the drivers and receivers is identical. Therefore, if the modes for the drivers and receivers
are supposed to be identical in the application,
the control lines can be tied together.
RS-422 receivers are used in RS-449,
EIA-530, EIA-530A and V.36 as Category I
signals for receiving clock, data, and some control line signals. The differential receivers can
receive data up to 10Mbps.
The RS-485 receivers are also used for the V.35
mode. Unlike the older implementations of
differential or V.35 receivers, the SP504 contains an internal resistor termination network
that ensures a V.35 input impedance of 100Ω
(±10Ω) and a short-circuit impedance of 150Ω
(±15Ω). The traditional V.35 implementations
required external termination resistors to acheive
the proper V.35 impedances. The internal network is connected via low on-resistance FET
switches when the decoder is changed to V.35
mode. The termination network is transparent
when all other modes are selected. The V.35
receivers can operate up to 10Mbps.
Like the drivers, the receivers are pre-arranged
for the specific requirements of the interface. As
the operating mode of the receivers is changed,
the electrical characteristics will change to support the requirements of clock, data, and control
line receivers. Table 2 shows the mode of each
receiver in the different interface modes that can
be selected.
There are three basic types of receiver circuits
— RS-232, RS-423, and RS-485.
All receivers include a fail-safe feature that
outputs a logic HIGH when the receiver inputs
are open. For single-ended RS-232 receivers,
there are internal 5kΩ pull-down resistors on the
inputs which produces a logic HIGH ("1") at the
receiver outputs. The single-ended RS-423 receivers produce a logic LOW ("0") on the output
when the inputs are open. This is due to a pullup device connected to the input. The differential receivers have the same internal pull-up
device on the non-inverting input which produces a logic HIGH ("1") at the receiver output.
The three differential receivers when configured in V.35 mode (RxD, RxC & SCT) do not
have fail-safe because the internal termination
resistor network is connected.
The RS-232 receiver is a single–ended input
with a threshold of 0.8V to 2.4V. The RS-232
receiver has an operating voltage range of ±15V
and can receive signals up to 120kbps. The
input sensitivity complies with EIA-RS-232 and
V.28 at +3V to -3V. The input impedance is
3kΩ to 7kΩ. RS-232 receivers are used in RS232 mode for all data, clock and control signals.
They are also used in V.35 mode for control line
signals such as CTS and DSR.
The RS-423 receivers are also single–ended but
have an input threshold as low as ±200mV. The
input impedance is guaranteed to be greater than
4kΩ, with an operating voltage range of ±7V.
The RS-423 receivers can operate up to 120kbps.
RS-423 receivers are used in RS-449, EIA-530,
EIA-530A and V.36 modes as Category II signals as indicated by their corresponding specifications.
Decoder
The SP504 has the ability to change the interface mode of the drivers or receivers via an 8–bit
switch. The decoder for the drivers and receivers is not latched; it is merely a combinational
logic switch.
The third type of receiver is a differential which
supports RS-485. The RS-485 receiver has an
input impedance of 15kΩ and a differential
threshold of ±200mV. Since the characteristics
of an RS-422 (V.11) receiver are actually
subsets of RS-485, the receivers for RS-422
requirements are covered by the RS-485 receivers.
Rev: A Date:1/27/04
The control word can be externally latched
either HIGH or LOW to write the appropriate
code into the SP504. The codes shown in Tables
1 and 2 are the only specified, valid modes for
the SP504. Undefined codes may represent other
interface modes not specified (consult the fac-
SP504 Multi–Mode Serial Transceivers
16
© Copyright 2004 Sipex Corporation
tory for more information). The drivers are
controlled with the data bits labeled TDEC3–
TDEC0. All of the drivers can be put into tristate mode by writing 0000 to the driver decode
switch. The three drivers TxD, ST and TxC,
have a 150Ω pull-down resistor to ground connected at the (b) output. This resistor is part of
the V.35 driver circuitry and should be connected when in V.35 mode. Tri-state is possible
for all drivers in RS-232 mode. The receivers
are controlled with data bits RDEC3–RDEC0;
the code 0000 written to the receivers will place
the outputs into tri-state mode. The 0000 decoder word will override the enable control line
for the one receiver (SCT).
Using the V.35_STAT Pin
The SP504 includes a V.35 status pin where the
V35_STAT pin (pin 18) is a logic HIGH ("1")
when the decoder is set to V.35 mode. The pin
is a logic LOW ("0") when in all other modes
including tri-state (decoder set at "0000"). Pin
18 allows the user to easily add FET switches or
solid state relays to connect the external 150Ω
resistor for V.35 operation. V35_STAT can be
connected to the gate of the FET switches or the
control of the relays so that the 150Ω resistors
are connected to the non-inverting output of the
three V.35 drivers. The output current of the
V35_STAT pin is that of a typical TTL load of
–3.2mA. The electrical specifications are similar to the SP504 receiver outputs. This feature
would reduce additional logic required by older
traditional methods.
NET1/NET2 Testing and Compliancy
Many system designers are required to certify
their system for use in the European public
network. Electrical testing is performed in adherence to the NET (Norme Européenne de
Télécommunication) which specifies the ITU
Series V specifications. The SP504 adheres to
all the required physical layer testing for NET1
and NET2. Consult factory for details.
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
17
© Copyright 2004 Sipex Corporation
SP504 Driver Mode Selection
Pin Label
Mode:
RS232
V.35
RS422
RS485
RS449
EIA530
EIA-530A
TDEC 3–TDEC0
0000
0010
1110
0100
0101
1100
1101
1111
0110
SD(a)
tri-state
V.28
V.35–
V.11–
RS485–
V.11–
V.11–
V.11–
V.11–
SD(b)
tri-state
tri-state
V.35+
V.11+
RS485+
V.11+
V.11+
V.11+
V.11+
TR(a)
tri-state
V.28
V.28
V.11–
RS485–
V.11–
V.11–
V.10
V.10
TR(b)
tri-state
tri-state
tri-state
V.11+
RS485+
V.11+
V.11+
tri-state
tri-state
V.36
RS(a)
tri-state
V.28
V.28
V.11–
RS485–
V.11–
V.11–
V.11–
V.10
RS(b)
tri-state
tri-state
tri-state
V.11+
RS485+
V.11+
V.11+
V.11+
tri-state
RL(a)
tri-state
V.28
V.28
V.11–
RS485–
V.10
V.11–
V.10
RL(b)
tri-state
tri-state
tri-state
V.11+
RS485+
V.11+
tri-state
V.10
tri-state
tri-state
LL(a)
tri-state
V.28
V.28
V.11–
RS485–
V.10
V.10
V.10
V.10
LL(b)
tri-state
tri-state
tri-state
V.11+
RS485+
tri-state
tri-state
tri-state
tri-state
ST(a)
tri-state
V.28
V.35–
V.11–
RS485–
V.11–
V.11–
V.11–
V.11–
ST(b)
tri-state
tri-state
V.35+
V.11+
RS485+
V.11+
V.11+
V.11+
V.11+
TT(a)
tri-state
V.28
V.35–
V.11–
RS485–
V.11–
V.11–
V.11–
V.11–
TT(b)
tri-state
tri-state
V.35+
V.11+
RS485+
V.11+
V.11+
V.11+
V.11+
Table 1. Driver Mode Selection
SP504 Receiver Mode Selection
Mode:
RS232
V.35
RS422
RS485
RS449
EIA530
EIA-530A
V.36
0000
0010
1110
0100
0101
1100
1101
1111
0110
RD(a)
>12kΩ to GND
V.28
RD(b)
>12kΩ to GND >12kΩ to GND
RT(a)
>12kΩ to GND
RT(b)
>12kΩ to GND >12kΩ to GND
CS(a)
>12kΩ to GND
CS(b)
>12kΩ to GND >12kΩ to GND >12kΩ to GND
DM(a)
>12kΩ to GND
DM(b)
>12kΩ to GND >12kΩ to GND >12kΩ to GND
RR(a)
>12kΩ to GND
RR(b)
>12kΩ to GND >12kΩ to GND >12kΩ to GND
IC(a)
>12kΩ to GND
IC(b)
>12kΩ to GND >12kΩ to GND
Pin Label
RDEC3–RDEC 0
V.28
V.28
V.28
V.28
V.28
SCT(a)
>12kΩ to GND
SCT(b)
>12kΩ to GND >12kΩ to GND
V.28
V.35–
V.11–
RS485–
V.11–
V.11–
V.11–
V.11–
V.35+
V.11+
RS485+
V.11+
V.11+
V.11+
V.11+
V.35–
V.11–
RS485–
V.11–
V.11–
V.11–
V.11–
V.35+
V.11+
RS485+
V.11+
V.11+
V.11+
V.11+
V.28
V.11–
RS485–
V.11–
V.11–
V.11–
V.11+
RS485+
V.11+
V.11+
V.11+
>12kΩ to GND
V.11–
RS485–
V.11–
V.11–
V.10
V.10
V.11+
RS485+
V.11+
V.11+
V.11–
RS485–
V.11–
V.11–
V.11–
V.10
V.11+
RS485+
V.11+
V.11+
V.11+
>12kΩ to GND
V.28
V.11–
RS485–
V.10
V.10
V.10
V.10
>12kΩ to GND
V.11+
RS485+
>12kΩ to GND
>12kΩ to GND
>12kΩ to GND
>12kΩ to GND
V.28
V.28
V.10
>12kΩ to GND >12kΩ to GND
V.35–
V.11–
RS485–
V.11–
V.11–
V.11–
V.11–
V.35+
V.11+
RS485+
V.11+
V.11+
V.11+
V.11+
Table 2. Receiver Mode Selection
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
18
© Copyright 2004 Sipex Corporation
1N5819
22µF
22µF
22µF
+5V
27
25
10µF
VCC
26
VDD C1+
31
30 28
C1- C2+
Charge Pump
C2VSS
22µF
32
B
A
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
150Ω
13 DTR
①
58 TR(a)
RxC 20
56 TR(b)
RT(b) 38
CS(a) 66
16 RTS
54 RS(a)
CTS 80
52 RS(b)
CS(b) 67
17 RL
DM(a) 68
47 RL(a)
DSR 78
45 RL(b)
DM (b) 69
24 LL
RR(a) 35
51 LL(a)
DCD 19
A — Receiver Tri-State circuitry & V.35
termination resistor circuitry for
RxD, RxC & SCT.
B — Driver Tri-State circuitry & V.35
termination circuitry for TxD,
TxC & ST.
49 LL(b)
RR(b) 36
22 ST
IC(a) 39
42 ST(a)
RI 21
44 ST(b)
IC(b) 40
23 STEN
①
SCT(a) 76
15 TxC
SCT 79
63 TT(a)
65 TT(b)
SCTEN 7
SCT(b) 77
6
TTEN
150Ω
RDEC
X
TDEC
External
Latch
5
4
3
2
9
10
11
12
X
①
RS-422 Mode
Input Word
0
1
0
0
0
1
0
0
150Ω
SP504
(SEE PAGE 12 FOR GROUND PINS)
① ☛ For V.35 Termination, needs to be connected
for proper V.35 operation. A low onresistance (≤1Ω) FET or switch can be used
to connect and disconnect the resistor from
the non-inverting output.
Figure 18. Typical Operation Circuit
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
19
© Copyright 2004 Sipex Corporation
MODE: RS-232
DRIVER
RECEIVER
TDEC3 TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC0
0
0
1
0
0
0
1
0
RD(a) 70
14 TxD
RxD 1
61 SD(a)
RT(a) 37
13 DTR
RxC 20
58 TR(a)
CS(a) 66
16 RTS
CTS 80
54 RS(a)
DM(a) 68
17 RL
DSR 78
47 RL(a)
RR(a) 35
24 LL
DCD 19
51 LL(a)
IC(a) 39
22 ST
RI 21
42 ST(a)
SCT(a) 76
23 STEN
15 TxC
SCT 79
63 TT(a)
SCTEN 7
6 TTEN
RECEIVERS
STEN
1
0
ST
Disabled
Enabled
DRIVERS
TTEN
TT
SCTEN
1
Disabled
1
0
Enabled
0
SCT
Enabled
Disabled
Figure 19. Mode Diagram — RS-232
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
20
© Copyright 2004 Sipex Corporation
MODE: V.35
DRIVER
RECEIVER
TDEC3 TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC0
1
1
1
0
1
1
1
0
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
RxC 20
16 RTS
RT(b) 38
CS(a) 66
54 RS(a)
CTS 80
17 RL
DM(a) 68
47 RL(a)
DSR 78
24 LL
RR(a) 35
51 LL(a)
DCD 19
22 ST
IC(a) 39
42 ST(a)
RI 21
44 ST(b)
23 STEN
SCT(a) 76
15 TxC
SCT 79
63 TT(a)
SCTEN 7
SCT(b) 77
65 TT(b)
6
RECEIVERS
STEN
1
0
ST
Disabled
Enabled
TTEN
DRIVERS
TTEN
TT
SCTEN
1
Disabled
1
0
Enabled
0
SCT
Enabled
Disabled
Figure 20. Mode Diagram — V.35
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
21
© Copyright 2004 Sipex Corporation
MODE: RS-422
DRIVER
RECEIVER
TDEC3 TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC0
0
1
0
0
0
1
0
0
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
RxC 20
56 TR(b)
RT(b) 38
CS(a) 66
16 RTS
54 RS(a)
CTS 80
52 RS(b)
CS(b) 67
17 RL
DM(a) 68
47 RL(a)
DSR 78
45 RL(b)
DM (b) 69
24 LL
RR(a) 35
51 LL(a)
DCD 19
49 LL(b)
RR(b) 36
22 ST
IC(a) 39
42 ST(a)
RI 21
44 ST(b)
IC(b) 40
23 STEN
SCT(a) 76
15 TxC
SCT 79
63 TT(a)
65 TT(b)
SCTEN 7
SCT(b) 77
6
RECEIVERS
STEN
1
0
ST
Disabled
Enabled
TTEN
DRIVERS
TTEN
TT
SCTEN
1
Disabled
1
0
Enabled
0
SCT
Enabled
Disabled
Figure 21. Mode Diagram — RS-422
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
22
© Copyright 2004 Sipex Corporation
MODE: RS-449
DRIVER
RECEIVER
TDEC3 TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC0
1
1
0
0
1
1
0
0
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
RxC 20
56 TR(b)
RT(b) 38
CS(a) 66
16 RTS
54 RS(a)
CTS 80
52 RS(b)
CS(b) 67
17 RL
DM(a) 68
47 RL(a)
DSR 78
24 LL
DM (b) 69
RR(a) 35
51 LL(a)
DCD 19
22 ST
RR(b) 36
42 ST(a)
IC(a) 39
44 ST(b)
RI 21
23 STEN
SCT(a) 76
15 TxC
SCT 79
63 TT(a)
65 TT(b)
SCTEN 7
SCT(b) 77
6
RECEIVERS
STEN
1
0
ST
Disabled
Enabled
TTEN
DRIVERS
TTEN
TT
SCTEN
1
Disabled
1
0
Enabled
0
SCT
Enabled
Disabled
Figure 22. Mode Diagram — RS-449
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
23
© Copyright 2004 Sipex Corporation
MODE: RS-485
DRIVER
RECEIVER
TDEC3 TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC0
0
1
0
1
0
1
0
1
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
RxC 20
56 TR(b)
RT(b) 38
CS(a) 66
16 RTS
54 RS(a)
CTS 80
52 RS(b)
CS(b) 67
17 RL
DM(a) 68
47 RL(a)
DSR 78
45 RL(b)
DM (b) 69
24 LL
RR(a) 35
51 LL(a)
DCD 19
49 LL(b)
RR(b) 36
22 ST
IC(a) 39
42 ST(a)
RI 21
44 ST(b)
IC(b) 40
23 STEN
SCT(a) 76
15 TxC
SCT 79
63 TT(a)
65 TT(b)
SCTEN 7
SCT(b) 77
6
RECEIVERS
STEN
1
0
ST
Disabled
Enabled
TTEN
DRIVERS
TTEN
TT
SCTEN
1
Disabled
1
0
Enabled
0
SCT
Enabled
Disabled
Figure 23. Mode Diagram — RS-485
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
24
© Copyright 2004 Sipex Corporation
MODE: EIA-530
DRIVER
RECEIVER
TDEC3 TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC0
1
1
0
1
1
1
0
1
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
RxC 20
56 TR(b)
RT(b) 38
CS(a) 66
16 RTS
54 RS(a)
CTS 80
52 RS(b)
CS(b) 67
17 RL
DM(a) 68
47 RL(a)
DSR 78
24 LL
DM (b) 69
RR(a) 35
51 LL(a)
DCD 19
22 ST
RR(b) 36
42 ST(a)
IC(a) 39
44 ST(b)
RI 21
23 STEN
SCT(a) 76
15 TxC
SCT 79
63 TT(a)
65 TT(b)
SCTEN 7
SCT(b) 77
6
RECEIVERS
STEN
1
0
ST
Disabled
Enabled
TTEN
DRIVERS
TTEN
TT
SCTEN
1
Disabled
1
0
Enabled
0
SCT
Enabled
Disabled
Figure 24. Mode Diagram — EIA-530
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
25
© Copyright 2004 Sipex Corporation
MODE: EIA-530A
DRIVER
RECEIVER
TDEC3 TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC0
1
1
1
1
1
1
1
1
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
RxC 20
16 RTS
RT(b) 38
CS(a) 66
54 RS(a)
52 RS(b)
CTS 80
17 RL
CS(b) 67
DM(a) 68
47 RL(a)
45 RL(b)
DSR 78
24 LL
RR(a) 35
51 LL(a)
DCD 19
22 ST
RR(b) 36
IC(a) 39
42 ST(a)
44 ST(b)
RI 21
23 STEN
SCT(a) 76
15 TxC
63 TT(a)
SCT 79
SCTEN 7
SCT(b) 77
65 TT(b)
6
RECEIVERS
TTEN
DRIVERS
STEN
ST
TTEN
TT
SCTEN
SCT
STEN
ST
TTEN
TT
SCTEN
SCT
1
Disabled
1
Disabled
1
•Enabled
1
Disabled
1
Disabled
1
Enabled
Enabled 0 0 Enabled
Enabled 0 0 Disabled
•Disabled
0 0 Enabled
Figure 25. Mode Diagram — EIA-530A
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
26
© Copyright 2004 Sipex Corporation
MODE: V.36
DRIVER
RECEIVER
TDEC3 TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC0
0
1
1
0
0
1
1
0
14 TxD
RD(a) 70
61 SD(a)
RxD 1
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
RxC 20
58 TR(a)
16 RTS
RT(b) 38
CS(a) 66
54 RS(a)
CTS 80
17 RL
DM(a) 68
47 RL(a)
DSR 78
24 LL
RR(a) 35
51 LL(a)
DCD 19
22 ST
IC(a) 39
42 ST(a)
RI 21
44 ST(b)
23 STEN
SCT(a) 76
15 TxC
SCT 79
63 TT(a)
SCTEN 7
SCT(b) 77
65 TT(b)
6
RECEIVERS
TTEN
DRIVERS
STEN
ST
TTEN
TT
SCT
STEN
ST
TTEN
SCTEN
SCT
Disabled 1 1 Disabled
Disabled 1 1 Enabled
•Enabled
11
Disabled
Enabled 0 0 Enabled
Enabled 0 0 Disabled
•Disabled
00
Enabled
Figure 26. Mode Diagram — V.36
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
27
© Copyright 2004 Sipex Corporation
used for RS-423 by connecting a zener clamping diode to ground on the two driver outputs.
The diodes will limit the voltage swing on the
outputs so that the VOC = ±4V to ±6V adheres to
the RS-423 specification. The differential receiver can be easily configured to RS-423 by
grounding the non-inverting input. The receiver
will adhere to the RS-423 specifications.
A programmable transceiver such as the SP332
is a convenient solution in a design that requires
extra single ended or differential drivers/receivers. As shown in Figure 28, the SP332 can be
configured to four different variations.
The SP332 in Figure 29 is configured for two
single-ended drivers and one diffferential receiver. For a DTE design, the two drivers are
used for LL and RL signals and the receiver is
used for the TM signal. This configuration was
selected because the two RS-232 drivers can be
SEL A
SEL B
LOOPBACK
SHUTDOWN
0
0
1
0
26 TI1
27 TI2
28 TI3
T1
T2
T3
19 RX1
T4
R1
20 RX2
R2
21 RX3
R3
TX1 6
26 TI1
TX2 7
27 TI2
R4
--------------
SC
RC
IS
IC
TR
DM
SD
RD
TT
ST
RT
RS
CS
RR
SQ
NS
SF
SR
SI
SSD
SRD
SRS
SCS
SRR
LL
RL
TM
SS
SB
SEND COMMON
RECEIVE COMMON
TERMINAL IN SERVICE
INCOMING CALL
TERMINAL READY
DATA MODE
SEND DATA
RECEIVE DATA
TERMINAL TIMING
SEND TIMING
RECEIVE TIMING
REQUEST TO SEND
CLEAR TO SEND
RECEIVER READY
SIGNAL QUALITY
NEW SIGNAL
SELECT FREQUENCY
SIGNAL RATE SELECTOR
SIGNAL RATE INDICATOR
SECONDARY SEND DATA
SECONDARY RD
SECONDARY RS
SECONDARY CS
SECONDARY RR
LOCAL LOOPBACK
REMOTE LOOPBACK
TEST MODE
SELECT STANDBY
STANDBY INDICATOR
TO DCE
FROM DCE
TO DCE
FROM DCE
TO DCE
FROM DCE
TO DCE
FROM DCE
TO DCE
FROM DCE
FROM DCE
TO DCE
FROM DCE
FROM DCE
FROM DCE
TO DCE
TO DCE
TO DCE
FROM DCE
TO DCE
FROM DCE
TO DCE
FROM DCE
FROM DCE
TO DCE
TO DCE
FROM DCE
TO DCE
FROM DCE
1
0
1
0
26 TI1
T2
28 TI3
RI2 16
19 RX1
20 RX2
TX3 4
T3
TX4 3
R1
CONTROL
DATA
TIMING
CONTROL
DATA
CONTROL
CONTROL
CONTROL
1
1
1
0
TX1 6
T1
R2
TX2 7
26 TI1
TX1 6
T1
T4
19 RX1
TX3 4
T3
TX4 3
RI1 15
R1
TX2 7
TX3 4
28 TI3
1 TI4
RI2 16
19 RX1
TX4 3
RI1 15
R1
RI2 16
RI2 16
21 RX3
RI3 17
R3
T3
RI1 15
RI3 17
RI4 18
COMMON
TX2 7
TX4 3
RI1 15
TYPE
SIGNAL GROUND
TX1 6
T1
CIRCUIT
RS-449 Interchange Circuits Table
TX3 4
21 RX3
22 RX4
1
CIRCUIT
DIRECTION
SG
0
1
1
0
28 TI3
1 TI4
CIRCUIT NAME
PRIMARY CHANNEL
CIRCUIT
MNEMONIC
SECONDARY
CHANNEL
ADDITIONAL TRANSCEIVERS
WITH THE SP504
Serial ports usually can have two data signals
(SD, RD), three clock signals (TT, ST, RT), and
at least eight control signals (CS, RS, etc.). EIARS-449 contains twenty six signal types for a
DB-37 connector. A DB-37 serial port design
may require thirteen drivers and fourteen receivers1. Although many applications do not
use all these signals, some applications may
need to support extra functions such as diagnostics. The SP504 supports enough transceivers
for the primary channels of data, clock and
control signals. Configuring LL, RL and TM
would require two additional drivers and one
receiver if designing for a DTE (one driver and
two receivers for a DCE).
RI4 18
R3
RI3 17
21 RX3
22 RX4
R4
RI4 18
RI3 17
R3
RI4 18
Figure 28. Mode selection for the SP332
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
28
© Copyright 2004 Sipex Corporation
1N5819
22µF
+5V
22µF
25
10µF
27
VCC
Drivers
Receivers
26
VDD
22µF
30
C1+
28
31
DB-37 Connector
61
TxD
14
59
DTR
13
56
RTS
16
52
TxC
15
65
ST
22
44
RL
17
45
LL
24
49
RxD
1
71
RxC
20
38
4
22
12
30
7
25
17
35
58
54
63
42
47
16
51
34
70
6
24
8
26
9
27
11
29
13
31
15
37
66
CTS
80
67
68
DSR
78
69
35
DCD
19
"1100" for RS-449 mode
22µF
32
C1V
C2+ C2- SS
36
39
RI
21
40
SCT
79
77
76
5
23
see pinout diagram for various ground pins
TDEC3—TDEC0 (pins 9-12)
SP504CF
RDEC3—RDEC0 (pins 5-2)
+5V
5
9
C1+
12
C111
C2+
0.1µF
0.1µF
13
C2-
26
VCC
V+
10µF
0.1µF
V- 14
0.1µF
SP332
T1
27
10
T2
6
LL
10
7
RL
14
TM
18
3
28
Note: The SP332 will require clamping diodes on the driver outputs to limit the voltage to ±6V and comply with the RS-423
driver output specification of VOC = ±4V to
±6V and VOUT ≥ ±3.6V with a 450Ω load.
T3
19
R1
15
20
R2
16
R3
17
18
21
0
1
4
24
2
SEL A
SEL B
23
LOOPBACK
1
8
Figure 29. Adding extra differential and single-ended transceivers using the SP332
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
29
© Copyright 2004 Sipex Corporation
PACKAGE: 80 Pin MQFP
D
D1
D2
0.30" RAD. TYP.
PIN 1
c
0.20" RAD. TYP.
E1
E
E2
CL
5°-16°
0° MIN.
0°–7°
5°-16°
CL
L
L1
A2
A
b
A1
e
DIMENSIONS
Minimum/Maximum
(mm)
SYMBOL
80–PIN MQFP
JEDEC MS-22
(BEC) Variation
MIN
NOM
COMMON DIMENTIONS
MAX
SYMBL MIN
2.45
A
A1
0.00
A2
1.80
b
0.22
2.00
Seating
Plane
c
0.11
0.25
L
0.73
2.20
L1
NOM
MAX
23.00
0.88
1.03
1.60 BASIC
0.40
D
17.20 BSC
D1
14.00 BSC
D2
12.35 REF
E
17.20 BSC
E1
14.00 BSC
E2
12.35 REF
e
0.65 BSC
N
80
80 PIN MQFP (MS-022 BC)
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
30
© Copyright 2004 Sipex Corporation
ORDERING INFORMATION
Model
Temperature Range
Package Types
SP504MCF ........................................................................ 0°C to +70°C ...................................................... 80–pin JEDEC (BE-2 Outline) MQFP
REVISION HISTORY
DATE
1/27/04
REVISION
A
DESCRIPTION
Implemented tracking revision.
Corporation
ANALOG EXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sales Office
22 Linnell Circle
Billerica, MA 01821
TEL: (978) 667-8700
FAX: (978) 670-9001
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
31
© Copyright 2004 Sipex Corporation