TPD2E001-Q1 www.ti.com SLLS993 – NOVEMBER 2009 LOW-CAPACITANCE 2-CHANNEL ±15-kV ESD-PROTECTION ARRAY FOR HIGH-SPEED DATA INTERFACES Check for Samples: TPD2E001-Q1 FEATURES APPLICATIONS • • • • • • • • • 1 2 • • • • • • Qualified for Automotive Applications ESD Protection Exceeds – ±15-kV Human-Body Model (HBM) – ±8-kV IEC 61000-4-2 Contact Discharge – ±15-kV IEC 61000-4-2 Air-Gap Discharge Low 1.5-pF Input Capacitance Low 1-nA (Max) Leakage Current 0.9-V to 5.5-V Supply-Voltage Range Two-Channel Device Space-Saving DRL Package Alternate 3-, 4-, 6-Channel Options Available: TPD3E001, TPD4E001, and TPD6E001 USB 2.0 Ethernet FireWire™ Video Cell Phones SVGA Video Connections Glucose Meters DRL PACKAGE (TOP VIEW) VCC 1 NC 2 IO1 3 5 IO2 4 GND NC – No internal connection DESCRIPTION/ORDERING INFORMATION The TPD2E001 is a low-capacitance ±15-kV ESD-protection diode array designed to protect sensitive electronics attached to communication lines. Each channel consists of a pair of diodes that steer ESD current pulses to VCC or GND. The TPD2E001 protects against ESD pulses up to ±15-kV Human-Body Model (HBM), ±8-kV Contact Discharge, and ±15-kV Air-Gap Discharge, as specified in IEC 61000-4-2. This device has a 1.5-pF capacitance per channel, making it ideal for use in high-speed data IO interfaces. The TPD2E001 is a two-channel device intended for USB and USB 2.0 applications. The TPD2E001 is available in the DRL package and is specified for –40°C to 85°C operation. ORDERING INFORMATION (1) TA –40°C to 85°C (1) (2) PACKAGE SOT-533 – DRL (2) Reel of 4000 ORDERABLE PART NUMBER TPD2E001IDRLRQ1 TOP-SIDE MARKING OEQ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FireWire is a trademark of Apple Computer, Inc. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TPD2E001-Q1 SLLS993 – NOVEMBER 2009 www.ti.com LOGIC BLOCK DIAGRAM VCC IO2 IO1 GND PIN DESCRIPTION NO. NAME 3, 5 IOx 4 GND Ground 1 VCC Power-supply input. Bypass VCC to GND with a 0.1-μF ceramic capacitor. 2 N.C. No connection. Not internally connected. EP 2 FUNCTION ESD-protected channel Exposed pad. Connect to GND. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPD2E001-Q1 TPD2E001-Q1 www.ti.com SLLS993 – NOVEMBER 2009 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC VIO Tstg Storage temperature range TJ Junction temperature Bump temperature (soldering) MIN MAX –0.3 7 –0.3 VCC + 0.3 V –65 150 °C 150 °C Infrared (15 s) 220 Vapor phase (60 s) 215 Lead temperature (soldering, 10 s) (1) UNIT V °C 300 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute-maximum-rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS VCC = 5 V ± 10%, TA = -40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VCC Supply voltage ICC Supply current VF Diode forward voltage IF = 10 mA 0.65 VBR Breakdown Voltage IBR = 10mA 11 Channel clamp voltage (2) VC (1) MAX 0.9 1 TA = 25°C, ±15-kV HBM, IF = 10 A Positive transients TA = 25°C, ±8-kV Contact Discharge (IEC 61000-4-2), IF = 24 A Positive transients TA = 25°C, ±15-kV Air-Gap Discharge (IEC 61000-4-2), IF = 45 A Positive transients Ii/o Channel leakage current (2) Vi/o = GND to VCC Ci/o Channel input capacitance VCC = 5 V, Bias of VCC/2 (1) (2) TYP UNIT 5.5 V 120 nA 0.95 V V VCC + 25 Negative transients –25 VCC + 60 Negative transients –60 V VCC + 100 Negative transients –100 ±1 1.5 nA pF Typical values are at VCC = 5 V and TA = 25°C Not production tested ESD PROTECTION PARAMETER TYP UNIT ±15 kV IEC 61000-4-2 Contact Discharge ±8 kV IEC 61000-4-2 Air-Gap Discharge ±15 kV HBM Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPD2E001-Q1 3 TPD2E001-Q1 SLLS993 – NOVEMBER 2009 www.ti.com TYPICAL OPERATING CHARACTERISTICS IO CAPACITANCE vs IO VOLTAGE (VCC = 5.0 V) 2.20 IO Capacitance (pF) 2.00 1.80 1.60 1.40 1.20 1.00 0.00 1.00 2.00 2.50 3.00 4.00 5.00 IO Voltage (V) IO LEAKAGE CURRENT vs TEMPERATURE (VCC = 5.5 V) IO Leakage Current (pA) 1000 100 10 1 –40 25 45 65 85 Temperature (°C) 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPD2E001-Q1 TPD2E001-Q1 www.ti.com SLLS993 – NOVEMBER 2009 APPLICATION INFORMATION VCC 0.1 µF VBUS RT IO1 D+ USB Controller RT D1 D– IO2 GND GND Detailed Description When placed near the connector, the TPD2E001 ESD solution offers little or no signal distortion during normal operation due to low IO capacitance and ultra-low leakage current specifications. The TPD2E001 ensures that the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For proper operation, the following layout/ design guidelines should be followed: 1. Place the TPD2E001 solution close to the connector. This allows the TPD2E001 to take away the energy associated with ESD strike before it reaches the internal circuitry of the system board. 2. Place a 0.1-μF capacitor very close to the VCC pin. This limits any momentary voltage surge at the IO pin during the ESD strike event. 3. Make sure that there is enough metallization for the VCC and GND loop. During normal operation, the TPD2E001 consumes nA leakage current. But during the ESD event, VCC and GND may see 15 A to 30 A of current, depending on the ESD level. Sufficient current path enables safe discharge of all the energy associated with the ESD strike. 4. Leave the unused IO pins floating. 5. The VCC pin can be connected in two different ways: (a) If the VCC pin is connected to the system power supply, the TPD2E001 works as a transient suppressor for any signal swing above VCC + VF. A 0.1-μF capacitor on the device VCC pin is recommended for ESD bypass. (b) If the VCC pin is not connected to the system power supply, the TPD2E001 can tolerate higher signal swing in the range up to 10 V. Please note that a 0.1-μF capacitor is still recommended at the VCC pin for ESD bypass. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPD2E001-Q1 5 PACKAGE OPTION ADDENDUM www.ti.com 5-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TPD2E001IDRLRQ1 ACTIVE SOT DRL Pins Package Eco Plan (2) Qty 5 4000 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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