www.ti.com TPD6E004 LOW-CAPACITANCE 6-CHANNEL ±15-kV ESD PROTECTION ARRAY FOR HIGH-SPEED DATA INTERFACES SLLS799A – FEBRUARY 2008 – REVISED FEBRUARY 2008 FEATURES 1 • • • • • • • IO2 IO3 2 3 GND 4 7 6 5 IO4 8 IO5 APPLICATIONS 1 IO6 VCC IO1 RSE PACKAGE (BOTTOM VIEW) • ESD Protection Exceeds JESD – ±15-kV Human-Body Model (HBM) – ±8-kV IEC 61000-4-2 Contact Discharge – ±12-kV IEC 61000-4-2 Air-Gap Discharge • Low 1.6-pF IO Capacitance • 0.9-V to 5.5-V Supply-Voltage Range • 6-Channel Device • Space-Saving QFN (RSE) Package 2 USB Ethernet FireWire Video Cell Phones SVGA Video Connections Glucose Meters abc abc DESCRIPTION/ORDERING INFORMATION The TPD6E004 is a low-capacitance ±15-kV ESD-protection diode array designed to protect sensitive electronics attached to communication lines. Each channel consists of a pair of diodes that steers ESD current pulses to VCC or GND. The TPD6E004 protects against ESD pulses up to ±15-kV Human-Body Model (HBM), ±8-kV Contact Discharge, and ±12-kV Air-Gap Discharge, as specified in IEC 61000-4-2. This device has a typical 1.6-pF capacitance per channel, making it ideal for use in high-speed data IO interfaces. The TPD6E004 is a six-channel ESD structure designed for wthernet and FireWire applications. The TPD6E004 is available in the RSE package and is specified for –40°C to 85°C operation. ORDERING INFORMATION TA –40°C to 85°C (1) (2) PACKAGE (1) (2) QFN – RSE 1.5 mm × 1.5 mm, Pitch = 0.5 mm, Height = 0.55 mm ORDERABLE PART NUMBER Reel of 3000 TPD6E004RSER TOP-SIDE MARKING 2V Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated TPD6E004 LOW-CAPACITANCE 6-CHANNEL ±15-kV ESD PROTECTION ARRAY FOR HIGH-SPEED DATA INTERFACES www.ti.com SLLS799A – FEBRUARY 2008 – REVISED FEBRUARY 2008 LOGIC BLOCK DIAGRAM VCC IO1 IO2 IO3 IO4 IO5 IO6 GND PIN DESCRIPTION RSE NO. NAME 1-3, 5-7 IOx FUNCTION 4 GND Ground 8 VCC Power-supply input. Bypass VCC to GND with a 0.1-µF ceramic capacitor. ESD-protected channel ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC –0.3 5.5 VIO –0.3 VCC + 0.3 V –65 150 °C 150 °C Tstg Storage temperature range TJ Junction temperature Bump temperature (soldering) Infrared (15 s) 220 Vapor phase (60 s) 215 Lead temperature (soldering, 10 s) (1) 2 300 UNIT V °C °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPD6E004 www.ti.com TPD6E004 LOW-CAPACITANCE 6-CHANNEL ±15-kV ESD PROTECTION ARRAY FOR HIGH-SPEED DATA INTERFACES SLLS799A – FEBRUARY 2008 – REVISED FEBRUARY 2008 ELECTRICAL CHARACTERISTICS VCC = 5 V ± 10%, TA = TMIN to TMAX (unless otherwise noted) PARAMETER TEST CONDITIONS VCC Supply voltage ICC Supply current VF Diode forward voltage II Channel leakage current VBR Break-down Voltage II = 10µA CI/O Channel input capacitance VCC = 5 V, Bias of VCC/2, f = 10MHz (1) MIN TYP (1) 0.9 IF = 1 mA MAX UNIT 5.5 V 500 nA 0.8 V ±1 nA 6 1.6 8 V 2 pF Typical values are at VCC = 5 V and TA = 25°C. ESD PROTECTION PARAMETER HBM TYP UNIT ±15 kV IEC 61000-4-2 Contact Discharge ±8 kV IEC 61000-4-2 Air-Gap Discharge ±12 kV Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPD6E004 3 TPD6E004 LOW-CAPACITANCE 6-CHANNEL ±15-kV ESD PROTECTION ARRAY FOR HIGH-SPEED DATA INTERFACES www.ti.com SLLS799A – FEBRUARY 2008 – REVISED FEBRUARY 2008 TYPICAL OPERATING CHARACTERISTICS 160 70 140 60 120 Leakage Current (pA) IO Current (mA) 50 100 80 60 40 20 40 30 20 10 0 1.05 1.15 1.25 1.35 1.45 0 1.55 –40 55 25 IO Voltage (V) 85 Temperature (°C) Figure 1. Forward Diode Voltage (Upper Clamp Diode) (VCC = 0 V, DC Sweep Across the IO Pin) Figure 2. Leakage Current vs Temperature (VIO = 2.5 V) 5.0 16.0 14.0 4.0 IO Capacitance (pF) 12.0 IO Current (µA) 10.0 8.0 6.0 4.0 3.0 2.0 1.0 2.0 0.0 0.0 0.0 4 1.0 2.0 3.0 4.0 5.0 6.0 7.0 1 2 3 4 IO Voltage (V) IO Voltage (V) Figure 3. Reverse Diode Curve Current IO to GND (VCC = Open) Figure 4. IO Capacitance vs Input Voltage (VCC = 5 V) Submit Documentation Feedback 5 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPD6E004 TPD6E004 LOW-CAPACITANCE 6-CHANNEL ±15-kV ESD PROTECTION ARRAY FOR HIGH-SPEED DATA INTERFACES www.ti.com SLLS799A – FEBRUARY 2008 – REVISED FEBRUARY 2008 TYPICAL OPERATING CHARACTERISTICS (continued) 220 200 180 160 Amplitude (V) 140 120 100 80 60 40 20 0 –20 0 25 50 75 100 125 150 Time (ns) 175 200 225 250 Figure 5. IEC ESD Clamping Waveforms +8-kV Contact, Average of 10 Waveforms Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPD6E004 5 TPD6E004 LOW-CAPACITANCE 6-CHANNEL ±15-kV ESD PROTECTION ARRAY FOR HIGH-SPEED DATA INTERFACES www.ti.com SLLS799A – FEBRUARY 2008 – REVISED FEBRUARY 2008 APPLICATION INFORMATION VBUS 0.1 µF VCC D+ D– RT GND IO5 USB Controller IO3 Open IO1 Open D1 IO6 IO2 IO4 VBUS D+ D– GND GND Detailed Description When placed near the connector, the TPD6E004 ESD solution offers little or no signal distortion during normal operation due to low IO capacitance and ultra-low leakage current specifications. The TPD6E004 ensures that the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For proper operation, the following layout/design guidelines should be followed: 1. Place the TPD6E004 solution close to the connector. This allows the TPD6E004 to take away the energy associated with ESD strike before it reaches the internal circuitry of the system board. 2. Place a 0.1-µF capacitor very close to the VCC pin. This limits any momentary voltage surge at the IO pin during the ESD strike event. 3. Make sure that there is enough metallization for the VCC and GND loop. During normal operation, the TPD6E004 consumes nA leakage current. But during the ESD event, VCC and GND may see 15 A to 30 A of current, depending on the ESD level. Sufficient current path enables safe discharge of all the energy associated with the ESD strike. 4. Leave the unused IO pins floating. 5. The VCC pin can be connected in two different ways: a. If the VCC pin is connected to the system power supply (a 0.1-µF capacitor at VCC is recommended for ESD bypass), the TPD6E004 works as a transient voltage suppressor for any signal swing above VCC + Vd. b. If the VCC pin is not connected to system power supply (a 0.1-µF capacitor is still recommended at the VCC pin for ESD bypass), the TPD6E004 can tolerate higher signal swing in the range up to VBR. Note that initially the bypass capacitor is charged by the signals through clamp diode. 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPD6E004 PACKAGE OPTION ADDENDUM www.ti.com 8-Feb-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TPD6E004RSER ACTIVE QFN RSE Pins Package Eco Plan (2) Qty 8 3000 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPD6E004RSER Package Package Pins Type Drawing QFN RSE 8 SPQ Reel Reel Diameter Width (mm) W1 (mm) 3000 179.0 8.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 1.7 1.7 0.76 4.0 W Pin1 (mm) Quadrant 8.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD6E004RSER QFN RSE 8 3000 220.0 205.0 50.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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