TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com Ultralow-Power NTSC/PAL/SECAM Video Decoder Check for Samples: TVP5151 1 Introduction 1.1 Features 1 • Accepts NTSC (J, M, 4.43), PAL (B, D, G, H, I, M, N, Nc), and SECAM (B, D, G, K, K1, L) Video • Supports ITU-R BT.601 Standard Sampling • High-Speed 9-Bit Analog-to-Digital Converter (ADC) • Two Composite Inputs or One S-Video Input • Fully Differential CMOS Analog Preprocessing Channels With Clamping and Automatic Gain Control (AGC) for Best Signal-to-Noise (S/N) Performance • Ultralow Power Consumption • 48-Terminal PBGA Package (ZQC) or 32-Terminal TQFP Package (PBS) • Power-Down Mode: <1 mW • Brightness, Saturation, Hue, and Sharpness Control Through I2C • Complementary 4-Line (3-H Delay) Adaptive Comb Filters for Both Cross-Luminance and Cross-Chrominance Noise Reduction • Patented Architecture for Locking to Weak, Noisy, or Unstable Signals • Single 27.000-MHz Crystal for All Standards • Internal Phase-Locked Loop (PLL) for Line-Locked Clock and Sampling • Subcarrier Genlock Output for Synchronizing Color Subcarrier of External Encoder • Variable Digital I/O Supply Voltage Range from 1.8 V to 3.3 V 1.2 • Standard Programmable Video Output Formats – ITU-R BT.656, 8-Bit 4:2:2 With Embedded Syncs – 8-Bit 4:2:2 With Discrete Syncs • Macrovision™ Copy Protection Detection • Advanced Programmable Video Output Formats – 2× Oversampled Raw Vertical Blanking Interval (VBI) Data During Active Video – Sliced VBI Data During Horizontal Blanking or Active Video • VBI Modes Supported – Teletext (NABTS, WST) – Closed-Caption Decode With FIFO and Extended Data Services (XDS) – Wide Screen Signaling, Video Program System, CGMS-A, Vertical Interval Time Code – Gemstar 1x/2x Electronic Program Guide Compatible Mode – Custom Configuration Mode That Allows User to Program Slice Engine for Unique VBI Data Signals • Power-On Reset • Industrial Temperature Range (TVP5151I): –40°C to 85°C Description The TVP5151 device is an ultralow-power NTSC/PAL/SECAM video decoder. Available in a space-saving 48-terminal PBGA package or a 32-terminal TQFP package, the TVP5151 decoder converts NTSC, PAL, and SECAM video signals to 8-bit ITU-R BT.656 format. Discrete syncs are also available. The optimized architecture of the TVP5151 decoder allows for ultralow power consumption. The decoder consumes 138-mW power under typical operating conditions and consumes less than 1 mW in power-down mode, considerably increasing battery life in portable applications. The decoder uses just one crystal for all supported standards. The TVP5151 decoder can be programmed using an I2C serial interface. The TVP5151 decoder converts baseband analog video into digital YCbCr 4:2:2 component video. Composite and S-video inputs are supported. The TVP5151 decoder includes one 9-bit analog-to-digital converter (ADC) with 2× sampling. Sampling is ITU-R BT.601 (27.0 MHz, generated from the 27.000-MHz crystal or oscillator input) and is line locked. The output formats can be 8-bit 4:2:2 or 8-bit ITU-R BT.656 with embedded synchronization. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2011, Texas Instruments Incorporated TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com The TVP5151 decoder utilizes Texas Instruments patented technology for locking to weak, noisy, or unstable signals. A Genlock/real-time control (RTC) output is generated for synchronizing downstream video encoders. Complementary four-line adaptive comb filtering is available for both the luminance and chrominance data paths to reduce both cross-luminance and cross-chrominance artifacts; a chrominance trap filter is also available. Video characteristics including hue, brightness, saturation, and sharpness may be programmed using the industry standard I2C serial interface. The TVP5151 decoder generates synchronization, blanking, lock, and clock signals in addition to digital video outputs. The TVP5151 decoder includes methods for advanced vertical blanking interval (VBI) data retrieval. The VBI data processor slices, parses, and performs error checking on teletext, closed caption, and other data in several formats. The TVP5151 decoder detects copy-protected input signals according to the Macrovision™ standard and detects Type 1, 2, 3, and colorstripe processes. The main blocks of the TVP5151 decoder include: • Robust sync detector • ADC with analog processor • Y/C separation using four-line adaptive comb filter • Chrominance processor • Luminance processor • Video clock/timing processor and power-down control • Output formatter • I2C interface • VBI data processor • Macrovision detection for composite and S-video 1.3 Applications The following is a partial list of suggested applications: • Digital televisions • PDAs • Notebook PCs • Cell phones • Video recorder/players • Internet appliances/web pads • Handheld games • Surveillance • Portable navigation • Portable video projectors 2 Introduction Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 1.4 Related Products • • • • • 1.5 TVP5150AM1 TVP5154A TVP5146M2 TVP5147M1 TVP5158 Trademarks TI and MicroStar Junior are trademarks of Texas Instruments. Macrovision is a trademark of Macrovision Corporation. Gemstar is a trademark of Gemstar-TV Guide International. Other trademarks are the property of their respective owners. 1.6 Document Conventions Throughout this data manual, several conventions are used to convey information. These conventions are: • To identify a binary number or field, a lower case b follows the numbers. For example, 000b is a 3-bit binary field. • To identify a hexadecimal number or field, a lower case h follows the numbers. For example, 8AFh is a 12-bit hexadecimal field. • All other numbers that appear in this document that do not have either a b or h following the number are assumed to be decimal format. • If the signal or terminal name has a bar above the name (for example, RESETB), this indicates the logical NOT function. When asserted, this signal is a logic low, 0, or 0b. • RSVD indicates that the referenced item is reserved. 1.7 Ordering Information TA 0°C to 70°C –40°C to 85°C (1) (2) PACKAGED DEVICES (1) (2) PACKAGE OPTION TVP5151PBS Tray TVP5151PBSR Tape and reel TVP5151ZQC Tray TVP5151ZQCR Tape and reel TVP5151IPBS Tray TVP5151IPBSR Tape and reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Introduction Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 3 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 1 2 3 4 www.ti.com .............................................. 1 1.1 Features .............................................. 1 1.2 Description ........................................... 1 1.3 Applications .......................................... 2 1.4 Related Products ..................................... 3 1.5 Trademarks .......................................... 3 1.6 Document Conventions .............................. 3 1.7 Ordering Information ................................. 3 Device Details ............................................ 5 2.1 Functional Block Diagram ............................ 5 2.2 Terminal Assignments ............................... 6 2.3 Terminal Functions ................................... 7 Functional Description ................................. 9 3.1 Analog Front End .................................... 9 3.2 Composite Processing Block Diagram ............... 9 3.3 Adaptive Comb Filtering ............................ 10 3.4 Color Low-Pass Filter ............................... 11 3.5 Luminance Processing ............................. 12 3.6 Chrominance Processing ........................... 12 3.7 Timing Processor ................................... 12 3.8 VBI Data Processor (VDP) ......................... 12 3.9 VBI FIFO and Ancillary Data in Video Stream ..... 13 3.10 Raw Video Data Output ............................ 14 3.11 Output Formatter ................................... 14 3.12 Synchronization Signals ............................ 14 Introduction 4 5 6 7 ...................... ................................... 3.15 I2C Host Interface ................................... 3.16 Clock Circuits ....................................... 3.17 Genlock Control (GLCO) and RTC ................. 3.18 Reset and Power Down ............................ 3.19 Reset Sequence .................................... 3.20 Internal Control Registers .......................... 3.21 Register Definitions ................................. Electrical Specifications ............................. 4.1 Absolute Maximum Ratings ........................ 4.2 Recommended Operating Conditions .............. 4.3 Reference Clock Specifications .................... 4.4 Electrical Characteristics ........................... 4.5 DC Electrical Characteristics ....................... 4.6 Analog Electrical Characteristics ................... 4.7 Clocks, Video Data, Sync Timing ................... 4.8 I2C Host Interface Timing ........................... 4.9 Thermal Specifications ............................. Example Register Settings .......................... 5.1 Example 1 .......................................... 5.2 Example 2 .......................................... Application Information .............................. 6.1 Application Example ................................ Revision History ....................................... 3.13 Active Video (AVID) Cropping 16 3.14 Embedded Syncs 17 Contents 18 21 22 23 25 26 29 71 71 71 71 72 72 72 73 74 74 75 75 76 77 77 78 Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 2 Device Details 2.1 Functional Block Diagram PGA AIP1A AIP1B M U X A/D Luminance Processing Output Formatter Y/C Separation Macrovision Detection Chrominance Processing YOUT[7:0] YCbCr 8-Bit 4:2:2 VBI Data Processor (VDP) SCL SDA Host Interface Embedded Processor PDN SCLK Horizontal and Color PLLs XTAL2 Timing Processor XTAL1/OSC FID/GLCO VSYNC/PALI INTREQ/GPCL/VBLK HSYNC AVID/CLK_IN Figure 2-1. Functional Block Diagram Device Details Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 5 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 2.2 www.ti.com Terminal Assignments The TVP5151 video decoder is packaged in a 48-terminal PBGA package or a 32-terminal TQFP package. Figure 2-2 shows the terminal diagrams for both packages. Table 2-1 gives a description of the terminals. CH_AVDD CH_AGND REFM REFP PDN INTREQ/GPCL/VBLK AVID/CLK_IN HSYNC TQFP (PBS) PACKAGE (TOP VIEW) AIP1A AIP1B PLL_AGND PLL_AVDD XTAL1/OSC XTAL2 AGND RESETB 1 32 31 30 29 28 27 26 25 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 10 11 12 13 14 15 16 PBGA (ZQC) PACKAGE (BOTTOM VIEW) VSYNC/PALI FID/GLCO SDA SCL DVDD DGND YOUT0 YOUT1 G F E D C B A 2 3 4 5 6 7 SCLK IO_DVDD YOUT7/I2CSEL YOUT6 YOUT5 YOUT4 YOUT3 YOUT2 1 Figure 2-2. Terminal Diagrams 6 Device Details Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 2.3 Terminal Functions Table 2-1. Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION ZQC PBS AGND E1 7 G Substrate. Connect to analog ground. AIP1A A1 1 I Analog input. Connect to the video analog input via 0.1-µF capacitor. The maximum input range is 0-0.75 VPP, and may require an attenuator to reduce the input amplitude to the desired level. If not used, connect to AGND via a 0.1-µF capacitor (see Figure 6-1). AIP1B B1 2 I Analog input. Connect to the video analog input via 0.1-µF capacitor. The maximum input range is 0-0.75 VPP, and may require an attenuator to reduce the input amplitude to the desired level. If not used, connect to AGND via a 0.1-µF capacitor (see Figure 6-1). CH_AGND A3 31 G Analog ground Analog Section CH_AVDD A2 32 P Analog supply. Connect to 1.8-V analog supply. B2, B3, B6, C4, C5, D3–D6, E2–E5, F2, F5, F6 – – No connect PLL_AGND C2 3 G PLL ground. Connect to analog ground. PLL_AVDD C1 4 P PLL supply. Connect to 1.8-V analog supply. REFM A4 30 O A/D reference negative output. Connect to analog ground through a 1-µF capacitor. Also, it is recommended to connect directly to REFP through a 1-µF capacitor (see Figure 6-1). REFP B4 29 O A/D reference positive output. Connect to analog ground through a 1-µF capacitor (see Figure 6-1). XTAL1/OSC D2 5 I External clock reference input. Connect to analog ground if an external single-ended oscillator is connected to AVID/CLK_IN pin. XTAL2 D1 6 O External clock reference output. Not connected if XTAL1 or CLK_IN is driven by an external single-ended oscillator. NC Digital Section Active video indicator output/external clk input When XTAL1 is used as a reference clock and this terminal is left unconnected, this terminal is internally pulled down. AVID/CLK_IN A6 26 I/O When XTAL1 is used as a reference clock and AVID output is required, this pin must be low until terminal is configured as an output. This may be dependent on external circuitry connected to this terminal. When XTAL 1 is connected to ground, CLK_IN may be connected to an external single-ended oscillator from a 1.8-V to 3.3-V compatible clock signal depending on IO_DVDD voltage. DGND E6 19 G Digital ground DVDD E7 20 P Digital supply. Connect to 1.8-V digital supply. FID/GLCO C6 23 O FID: Odd/even field indicator or vertical lock indicator. For the odd/even indicator, a 1 indicates the odd field. GLCO: This serial output carries color PLL information. A slave device can decode the information to allow chrominance frequency control from the TVP5151 decoder. Data is transmitted at the SCLK rate in Genlock mode. In RTC mode, SCLK/4 is used. HSYNC A7 25 O Horizontal synchronization signal Device Details Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 7 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com Table 2-1. Terminal Functions (continued) TERMINAL NAME NO. ZQC I/O DESCRIPTION PBS This terminal has three functions selectable by bit 7 of I2C register 03h and bit 1 of I2C register 0Fh: • INTREQ: Interrupt request output • GPCL: General-purpose control logic output. In this mode, the state of terminal 27 is directly programmed via I2C. • VBLK: Vertical blanking output. In this mode, terminal 27 indicates the vertical blanking interval of the output video. The beginning and end times of this signal are programmable via I2C. INTREQ/ GPCL/VBLK B5 27 O IO_DVDD G2 10 P Digital output supply, 1.8 V to 3.3 V SCLK G1 9 O System clock at 2x the frequency of the pixel clock. PDN A5 28 I Power-down terminal (active low). Puts the decoder in standby mode. Preserves the value of the registers. RESETB F1 8 I Active-low reset. RESETB can be used only when PDN = 1. When RESETB is pulled low, it resets all the registers and restarts the internal microprocessor. SCL D7 21 I/O I2C serial clock (open drain) SDA C7 22 I/O I2C serial data (open drain) An external pullup or pulldown resistor is required under certain conditions (see Figure 6-1). VSYNC: Vertical synchronization signal VSYNC/PALI B7 24 O PALI: PAL line indicator or horizontal lock indicator. For the PAL line indicator: 1 = Noninverted line 0 = Inverted line YOUT[6:0] YOUT7/I2CSEL G3 F4 G4 G5 G6 G7 F7 F3 12 13 14 15 16 17 18 11 O I/O ITU-R BT.656 output/YCbCr 4:2:2 output with discrete syncs I2CSEL: Determines address for I2C (sampled during reset). A pullup or pulldown resistor is needed (>1 kΩ) to program the terminal to the desired address. 1 = Address is BAh 0 = Address is B8h YOUT7: Most significant bit (MSB) of ITU-R BT.656 output/YCbCr 4:2:2 output 8 Device Details Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3 Functional Description 3.1 Analog Front End The TVP5151 decoder has an analog input channel that accepts two video inputs that are ac-coupled. The decoder supports a maximum input voltage range of 0.75 V; therefore, an attenuation of one-half is needed for most input signals with a peak-to-peak variation of 1.5 V. The nominal parallel termination before the input to the device is recommended to be 75 Ω. See the application diagram in Figure 6-1 for the recommended configuration. The two analog input ports can be connected as follows: • Two selectable composite video inputs, or • One S-video input An internal clamping circuit restores the sync-tip of the ac-coupled video signal to a fixed dc level. The programmable gain amplifier (PGA) and the automatic gain control (AGC) algorithm work together to make sure that the input signal is amplified sufficiently to ensure the proper input range for the ADC. The ADC has nine bits of resolution and runs at a nominal speed of 27 MHz. The clock input for the ADC comes from the horizontal PLL. 3.2 Composite Processing Block Diagram The composite processing block processes NTSC/PAL/SECAM signals into the YCbCr color space. Figure 3-1 shows the basic architecture of this processing block. Figure 3-1 shows the luminance/chrominance (Y/C) separation process in the TVP5151 decoder. The composite video is multiplied by subcarrier signals in the quadrature modulator to generate the color difference signals Cb and Cr. Cb and Cr are then low pass (LP) filtered to achieve the desired bandwidth and to reduce crosstalk. An adaptive four-line comb filter separates CbCr from Y. Chrominance is remodulated through another quadrature modulator and subtracted from the line-delayed composite video to generate luminance. Brightness, hue, saturation, and sharpness (using the peaking filter) are programmable via I2C. The Y/C separation is bypassed for S-video input. For S-video, the remodulation path is disabled. Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 9 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com Gain Factor Peak Detector Bandpass X Peaking Composite Delay Line Delay + Delay Y Y Quadrature Modulation Brightness Saturation Adjust SECAM Luminance Cr Notch Filter Cb Composite SECAM Color Demodulation Cb Composite Quadrature Modulation Cr Cr Notch Filter Color LPF ↓ 2 Burst Accumulator (Cb) Cb 4-Line Adaptive Comb Filter Color LPF ↓ 2 LP Filter LP Filter Delay Delay Burst Accumulator (Cr) Figure 3-1. Composite Processing Block Diagram (Comb/Trap Filter Bypassed for SECAM) 3.3 Adaptive Comb Filtering The four-line comb filter can be selectively bypassed in the luminance or chrominance path. If the comb filter is bypassed in the luminance path, then chrominance trap filters are used which are shown in Figure 3-2 and Figure 3-3. TI's patented adaptive four-line comb filter algorithm reduces artifacts such as hanging dots at color boundaries and detects and properly handles false colors in high-frequency luminance images such as a multiburst pattern or circle pattern. 10 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com Figure 3-2. Chrominance Trap Filter Frequency Response, NTSC ITU-R BT.601 Sampling 3.4 Figure 3-3. Chrominance Trap Filter Frequency Response, PAL ITU-R BT.601 Sampling Color Low-Pass Filter In some applications, it is desirable to limit the Cb/Cr bandwidth to avoid crosstalk. This is especially true in case of video signals that have asymmetrical Cb/Cr sidebands. The color LP filters provided limit the bandwidth of the Cb/Cr signals. Color LP filters are needed when the comb filtering turns off, due to extreme color transitions in the input image. See Section 3.21.25, Chrominance Control #2 Register, for the response of these filters. The filters have three options that allow three different frequency responses based on the color frequency characteristics of the input video as shown in Figure 3-4. Figure 3-4. Color Low-Pass Filter with Filter Characteristics, NTSC/PAL ITU-R BT.601 Sampling Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 11 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 3.5 www.ti.com Luminance Processing The luminance component is derived from the composite signal by subtracting the remodulated chrominance information. A line delay exists in this path to compensate for the line delay in the adaptive comb filter in the color processing chain. The luminance information is then fed into the peaking circuit, which enhances the high frequency components of the signal, thus improving sharpness. 3.6 Chrominance Processing For NTSC/PAL formats, the color processing begins with a quadrature demodulator. The Cb/Cr signals then pass through the gain control stage for chrominance saturation adjustment. An adaptive comb filter is applied to the demodulated signals to separate chrominance and eliminate cross-chrominance artifacts. An automatic color killer circuit is also included in this block. The color killer suppresses the chrominance processing when the burst amplitude falls below a programmable threshold (see I2C subaddress 06h). The SECAM standard is similar to PAL except for the modulation of color which is FM instead of QAM. 3.7 Timing Processor The timing processor is a combination of hardware and software running in the internal microprocessor that serves to control horizontal lock to the input sync pulse edge, AGC and offset adjustment in the analog front end, vertical sync detection, and Macrovision detection. 3.8 VBI Data Processor (VDP) The TVP5151 VDP slices various data services such as teletext (WST, NABTS), closed captioning (CC), wide screen signaling (WSS), etc. These services are acquired by programming the VDP to enable standards in the VBI. The results are stored in a FIFO and/or registers. The teletext results are stored only in a FIFO. Table 3-1 lists a summary of the types of VBI data supported according to the video standard. It supports ITU-R BT. 601 sampling for each. Table 3-1. Data Types Supported by VDP LINE MODE REGISTER (D0h–FCh) BITS [3:0] 12 NAME DESCRIPTION 0000b WST SECAM Teletext, SECAM 0001b WST PAL B Teletext, PAL, System B 0010b WST PAL C Teletext, PAL, System C 0011b WST, NTSC B Teletext, NTSC, System B 0100b NABTS, NTSC C Teletext, NTSC, System C 0101b NABTS, NTSC D Teletext, NTSC, System D (Japan) 0110b CC, PAL Closed caption PAL 0111b CC, NTSC Closed caption NTSC 1000b WSS/CGMS-A Wide-screen signaling/Copy Generation Management System-Analog, PAL 1001b WSS/CGMS-A Wide-screen signaling/Copy Generation Management System-Analog, NTSC 1010b VITC, PAL Vertical interval timecode, PAL 1011b VITC, NTSC Vertical interval timecode, NTSC 1100b VPS, PAL Video program system, PAL 1101b Gemstar 2x Custom 1 Electronic program guide 1110b Reserved Reserved 1111b Active Video Active video/full field Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com At power-up the host interface is required to program the VDP-configuration RAM (VDP-CRAM) contents with the lookup table (see Section 3.21.64). This is done through port address C3h. Each read from or write to this address auto increments an internal counter to the next RAM location. To access the VDP-CRAM, the line mode registers (D0h to FCh) must be programmed with FFh to avoid a conflict with the internal microprocessor and the VDP in both writing and reading. Full field mode must also be disabled. Available VBI lines are from line 6 to line 27 of both field 1 and field 2. Each line can be any VBI mode. Output data is available either through the VBI-FIFO (B0h) or through dedicated registers at 90h to AFh, both of which are available through the I2C port. 3.9 VBI FIFO and Ancillary Data in Video Stream Sliced VBI data can be output as ancillary data in the video stream in the ITU-R BT.656 mode. VBI data is output during the horizontal blanking period following the line from which the data was retrieved. Table 3-2 shows the header format and sequence of the ancillary data inserted into the video stream. This format is also used to store any VBI data into the FIFO. The size of FIFO is 512 bytes. Therefore, the FIFO can store up to 11 lines of teletext data with the NTSC NABTS standard. Table 3-2. Ancillary Data Format and Sequence BYTE NO. D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 3 NEP EP 0 1 0 DID2 DID1 DID0 4 NEP EP F5 F4 F3 F2 F1 F0 Secondary data ID (SDID) 5 NEP EP N5 N4 N3 N2 N1 N0 Number of 32-bit data (NN) 6 Video line [7:0] 7 Data error 0 0 0 DESCRIPTION Ancillary data preamble Data ID (DID) Internal data ID0 (IDID0) Match 1 Match 2 Video line [9:8] Internal data ID1 (IDID1) 8 1. Data Data byte 9 2. Data Data byte 10 3. Data Data byte 11 4. Data Data byte ... ... ... m–1. Data Data byte m. Data Data byte RSVD 4(N+2)–1 1 CS[5:0] 0 0 0 First word 0 Check sum 0 EP: Even parity for D0–D5 NEP: Negated even parity DID: 91h: Sliced data of VBI lines of first field 0 0 Nth word Fill byte 53h: Sliced data of line 24 to end of first field 55h: Sliced data of VBI lines of second field 97h: Sliced data of line 24 to end of second field SDID: This field holds the data format taken from the line mode register of the corresponding line. NN: Number of Dwords beginning with byte 8 through 4(N+2). This value is the number of Dwords where each Dword is 4 bytes. IDID0: Transaction video line number [7:0] Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 13 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 IDID1: www.ti.com Bit 0/1 = Transaction video line number [9:8] Bit 2 = Match 2 flag Bit 3 = Match 1 flag Bit 4 = 1 if an error was detected in the EDC block; 0 if not CS: Sum of D0–D7 of DID through last data byte. Fill byte: Fill bytes make a multiple of 4 bytes from byte 0 to last fill byte. 3.10 Raw Video Data Output The TVP5151 decoder can output raw A/D video data at 2x sampling rate for external VBI slicing. This is transmitted as an ancillary data block during the active horizontal portion of the line and during vertical blanking. 3.11 Output Formatter The YCbCr digital output can be programmed as 8-bit 4:2:2 or 8-bit ITU-R BT.656 parallel interface standard. Table 3-3. Summary of Line Frequencies, Data Rates, and Pixel Counts STANDARDS (ITU-R BT.601) PIXELS PER LINE ACTIVE PIXELS PER LINE LINES PER FRAME PIXEL FREQUENCY (MHz) COLOR SUB-CARRIER FREQUENCY (MHz) HORIZONTAL LINE RATE (kHz) NTSC-J, M 858 720 525 13.5 3.579545 15.73426 NTSC-4.43 858 720 525 13.5 4.43361875 15.73426 PAL-M 858 720 525 13.5 3.57561149 15.73426 PAL-B, D, G, H, I 864 720 625 13.5 4.43361875 15.625 PAL-N 864 720 625 13.5 4.43361875 15.625 PAL-Nc 864 720 625 13.5 3.58205625 15.625 SECAM 864 720 625 13.5 4.40625/4.25 15.625 3.12 Synchronization Signals External (discrete) syncs are provided via the following signals (see Figure 3-5 and Figure 3-6): • VSYNC (vertical sync) • FID/VLK (field indicator or vertical lock indicator) • INTREQ/GPCL/VBLK (general-purpose output or vertical blanking indicator) • PALI/HLK (PAL switch indicator or horizontal lock indicator) • HSYNC (horizontal sync) • AVID (active video indicator) (if set as output) VSYNC, FID, PALI, and VBLK are software set and programmable to the SCLK pixel count. This allows any possible alignment to the internal pixel count and line count. The default settings for a 525-/625-line video output are given as an example. 14 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 525 Line 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 Composite Video VSYNC FID INTREQ/GPCL/VBLK ↔ VBLK Start 262 263 ↔ VBLK Stop 264 265 266 267 268 269 270 271 272 273 282 283 284 Composite Video VSYNC FID INTREQ/GPCL/VBLK ↔ VBLK Start ↔ VBLK Stop 625 Line 310 311 312 313 314 315 316 317 318 319 320 333 334 335 336 Composite Video VSYNC FID INTREQ/GPCL/VBLK ↔ VBLK Start 622 623 624 ↔ VBLK Stop 625 1 2 3 4 5 6 7 20 21 22 23 Composite Video VSYNC FID INTREQ/GPCL/VBLK ↔ VBLK Start A. ↔ VBLK Stop Line numbering conforms to ITU-R BT.470 and ITU-R BT.1700. Figure 3-5. 8-Bit 4:2:2, Timing With 2× Pixel Clock (SCLK) Reference Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 15 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com ITU-R BT.656 Timing NTSC 601 1436 1437 1438 1439 1440 1441 … 1455 1456 PAL 601 1436 1437 1438 1439 1440 1441 1459 1460 SECAM 1436 1437 1438 1439 1440 1441 … 1479 1480 ITU 656 Cb Datastream 359 Y 718 Cr 359 Y 719 FF 00 10 80 … … 1583 1584 … 1711 1712 1713 1714 1715 0 1 2 3 1587 1588 1723 1724 1725 1726 1727 0 1 2 3 1607 1608 … 1719 1720 1721 1722 1723 17 17 24 25 17 26 17 27 Cb 0 Cr 0 Y 1 10 80 10 FF 00 00 XX Y 0 HSYNC ↔ HSYNC Start AVID ↔ AVID Stop A. ↔ AVID Start AVID rising edge occurs four SCLK cycles early when in the ITU-R BT.656 output mode. Figure 3-6. Horizontal Synchronization Signals 3.13 Active Video (AVID) Cropping The AVID output signal provides a means to qualify and crop active video both horizontally and vertically. The horizontal start and stop position of the AVID signal is controlled using registers 11h-12h and 13h-14h, respectively. These registers also control the horizontal position of the embedded sync SAV/EAV codes. AVID vertical timing is controlled by the VBLK start and stop registers at addresses 18h and 19h. These VBLK registers have no effect on the embedded vertical sync code timing. Figure 3-7 shows an AVID application. NOTE The above settings alter AVID output timing, but the video output data is not forced to black level outside of the AVID interval. 16 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 VBLK Stop www.ti.com Active Video Area VBLK Start AVID Cropped Area AVID Stop VSYNC AVID Start HSYNC Figure 3-7. AVID Application 3.14 Embedded Syncs Standards with embedded syncs insert SAV and EAV codes into the datastream at the beginning and end of horizontal blanking. These codes contain the V and F bits that also define vertical timing. F and V change on EAV. Table 3-4 gives the format of the SAV and EAV codes. H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line and field counter varies depending on the standard. See ITU-R BT.656 for more information on embedded syncs. The P bits are protection bits: P3 = V xor H P2 = F xor H P1 = F xor V P0 = F xor V xor H Table 3-4. EAV and SAV Sequence 8-BIT DATA D7 (MSB) D6 D5 D4 D3 D2 D1 D0 Preamble 1 1 1 1 1 1 1 1 Preamble 0 0 0 0 0 0 0 0 Preamble 0 0 0 0 0 0 0 0 Status word 1 F V H P3 P2 P1 P0 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 17 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.15 I2C Host Interface The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line (SCL), which carry information between the devices connected to the bus. A third signal (I2CSEL) is used for slave address selection. Although the I2C system can be multimastered, the TVP5151 decoder functions only as a slave device. Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. When the bus is free, both lines are high. The slave address select terminal (I2CSEL) enables the use of two TVP5151 decoders tied to the same I2C bus. At power up, the status of the I2CSEL is polled. Depending on the write and read addresses to be used for the TVP5151 decoder, it can either be pulled low or high through a resistor. This terminal is multiplexed with YOUT7 and hence must not be tied directly to ground or IO_DVDD. Table 3-6 summarizes the terminal functions of the I2C-mode host interface. Table 3-5. Write Address Selection I2CSEL WRITE ADDRESS 0 B8h 1 BAh Table 3-6. I2C Terminal Description SIGNAL TYPE DESCRIPTION I2CSEL (YOUT7) I SCL I/O (open drain) Slave address selection Input/output clock line SDA I/O (open drain) Input/output data line Data transfer rate on the bus is up to 400 kbit/s. The number of interfaces connected to the bus is dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the high period of the SCL except for start and stop conditions. The high or low state of the data line can only change with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while the SCL is high indicates an I2C start condition. A low-to-high transition on the SDA line while the SCL is high indicates an I2C stop condition. Every byte placed on the SDA must be eight bits long. The number of bytes which can be transferred is unrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by the I2C master. 18 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.15.1 I2C Write Operation Data transfers occur utilizing the following illustrated formats. An I2C master initiates a write operation to the TVP5151 decoder by generating a start condition (S) followed by the TVP5151 I2C slave address (see the following illustration), in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving an acknowledge from the TVP5151 decoder, the master presents the subaddress of the register, or the first of a block of registers it wants to write, followed by one or more bytes of data, MSB first. The TVP5151 decoder acknowledges each byte after completion of each transfer. The I2C master terminates the write operation by generating a stop condition (P). Step 1 0 2 I C Start (master) S Step 2 7 6 5 4 3 2 1 0 I2C slave address (master) 1 0 1 1 1 0 X 0 Step 3 9 I2C Acknowledge (slave) A Step 4 I2C Write register address (master) 6 5 4 3 2 1 0 Addr Addr Addr Addr Addr Addr Addr Step 5 9 I2C Acknowledge (slave) A Step 6 7 6 5 4 3 2 1 0 Data Data Data Data Data Data Data Data 2 I C Write data (master) Step 7 (1) 9 2 I C Acknowledge (slave) (1) 7 Addr A Step 8 0 I2C Stop (master) P Repeat steps 6 and 7 until all data have been written. 3.15.2 I2C Read Operation The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master initiates a write operation to the TVP5151 decoder by generating a start condition (S) followed by the TVP5151 I2C slave address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving an acknowledge from the TVP5151 decoder, the master presents the subaddress of the register or the first of a block of registers it wants to read. After the cycle is acknowledged, the master terminates the cycle immediately by generating a stop condition (P). Table 3-7. Read Address Selection I2CSEL READ ADDRESS 0 B9h 1 BBh The second phase is the data phase. In this phase, an I2C master initiates a read operation to the TVP5151 decoder by generating a start condition followed by the TVP5151 I2C slave address (see the following illustration of a read operation), in MSB first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the TVP5151 decoder, the I2C master receives one or more bytes of data from the TVP5151 decoder. The I2C master acknowledges the transfer at the end of each byte. After the last data byte desired has been transferred from the TVP5151 decoder to the master, the master generates a not acknowledge followed by a stop. Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 19 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.15.2.1 Read Phase 1 Step 1 0 I2C Start (master) S Step 2 7 6 5 4 3 2 1 0 I2C slave address (master) 1 0 1 1 1 0 X 0 Step 3 9 2 I C Acknowledge (slave) Step 4 I2C Write register address (master) A 7 6 5 4 3 2 1 0 Addr Addr Addr Addr Addr Addr Addr Addr Step 5 9 I2C Acknowledge (slave) A Step 6 0 2 I C Stop (master) P 3.15.2.2 Read Phase 2 Step 7 0 I2C Start (master) S Step 8 7 6 5 4 3 2 1 0 I2C slave address (master) 1 0 1 1 1 0 X 1 Step 9 9 2 I C Acknowledge (slave) Step 10 I2C Read data (slave) 6 5 4 3 2 1 0 Data Data Data Data Data Data Data 9 I2C Not Acknowledge (master) A Step 12 0 I C Stop (master) 20 7 Data Step 11 (1) 2 (1) A P Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received. Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.15.2.3 I2C Timing Requirements The TVP5151 decoder requires delays in the I2C accesses to accommodate its internal processor's timing. In accordance with I2C specifications, the TVP5151 decoder holds the I2C clock line (SCL) low to indicate the wait period to the I2C master. If the I2C master is not designed to check for the I2C clock line held-low condition, then the maximum delays must always be inserted where required. These delays are of variable length; maximum delays are indicated in the following diagram: Normal register writing addresses 00h to 8Fh (addresses 90h to FFh do not require delays). Slave address (B8h) Start Ack Subaddress Ack Data (XXh) Wait 64 µs Ack Stop The 64-µs delay is for all registers that do not require a reinitialization. Delays may be more for some registers. 3.16 Clock Circuits An internal line-locked PLL generates the system and pixel clocks. A 27.000-MHz clock is required to drive the PLL. This may be input to the TVP5151 decoder on terminal 5 (XTAL1), or a crystal of 27.000-MHz fundamental resonant frequency may be connected across terminals 5 and 6 (XTAL2). Figure 3-8 shows the reference clock configurations. For the example crystal circuit shown (a parallel-resonant crystal with 27.000-MHz fundamental frequency), the external capacitors must have the following relationship: CL1 = CL2 = 2CL – CSTRAY where CSTRAY is the terminal capacitance with respect to ground, and CL is the crystal load capacitance specified by the crystal manufacturer. Figure 3-8 shows the reference clock configurations. TVP5151 TVP5151 IO_DVDD CLK_IN XTAL1/OSC 10 26 5 IO_DVDD 1.8 V to 3.3 V CLK_IN NC 27.000-MHz 1.8-V Clock XTAL1/OSC TVP5151 10 26 5 1.8 V to 3.3 V IO_DVDD 27.000-MHz 1.8-V to 3.3-V Clock CLK_IN XTAL1/OSC 10 26 1.8 V to 3.3 V NC 5 CL1 R XTAL2 6 XTAL2 NC 6 NC XTAL2 6 27.000-MHz Crystal CL2 NOTE: The resistor (R) in parallel with the crystal is recommended to support a wide range of crystal types. A 100-kΩ resistor may be used for most crystal types. Figure 3-8. Reference Clock Configurations An alternate method to supply an external source with a 1.8-V to 3.3-V peak-to-peak level is to pull pin 5 (XTAL1/OSC) low and connect a 1.8-V to 3.3-V external oscillator clock source to pin 26, AVID/CLK_IN, depending on what IO_DVDD supply voltage is used. Clock source frequency should have an accuracy of ±50 ppm (max). Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 21 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.17 Genlock Control (GLCO) and RTC A Genlock control function is provided to support a standard video encoder to synchronize its internal color oscillator for properly reproduced color with unstable timebase sources such as VCRs. The frequency control word of the internal color subcarrier digitally tuned oscillator (DTO) and the subcarrier phase reset bit are transmitted via terminal 23 (GLCO). The frequency control word is a 23-bit binary number. The frequency of the DTO can be calculated from the following equation: fdto = (fctrl/223) × fsclk where fdto is the frequency of the DTO, fctrl is the 23-bit DTO frequency control, and fsclk is the frequency of the SCLK. 3.17.1 GLCO Interface A write of 1 to bit 4 of the chrominance control register at I2C subaddress 1Ah causes the subcarrier DTO phase reset bit to be sent on the next scan line on GLCO. The active-low reset bit occurs seven SCLKs after the transmission of the last bit of DTO frequency control. Upon the transmission of the reset bit, the phase of the TVP5151 internal subcarrier DTO is reset to zero. A Genlock slave device can be connected to the GLCO terminal and uses the information on GLCO to synchronize its internal color phase DTO to achieve clean line and color lock. Figure 3-9 shows the timing diagram of the GLCO mode. SCLK GLCO 22 MSB LSB 21 0 >128 SCLK 23 SCLK 23-Bit Frequency Control 1 SCLK 7 SCLK 1 SCLK Start Bit DTO Reset Bit Figure 3-9. GLCO Timing 22 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.17.2 RTC Mode Figure 3-10 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is four times slower than the GLCO clock rate. For Color PLL frequency control, the upper 22 bits are used. Each frequency control bit is two clock cycles long. The active-low reset bit occurs six CLKs after the transmission of the last bit of PLL frequency control. RTC 128 CLK 16 CLK M S B L S B 21 0 44 CLK 22-Bit fsc Frequency Control 2 CLK 1 CLK PAL Switch 2 CLK Start Bit 3 CLK 1 CLK Reset Bit Figure 3-10. RTC Timing 3.18 Reset and Power Down The RESETB and PDN terminals work together to put the TVP5151 decoder into one of the two modes. Table 3-8 shows the configuration. After power-up, the device is in an unknown state with its outputs undefined, until it receives a RESETB signal as depicted in Figure 3-11. After RESETB is released, outputs SCLK and YOUT0 to YOUT7 are in high-impedance state until TVP5151 is initialized and the outputs are activated. NOTE I2C SCL and SDA signals must not change state until the TVP5151 reset sequence has been completed. Table 3-8. Reset and Power-Down Modes PDN RESETB 0 0 Reserved (unknown state) CONFIGURATION 0 1 Powers down the decoder 1 0 Resets the decoder 1 1 Normal operation Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 23 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com After RESETB is released, outputs SCLK and YOUT0 to YOUT7 are high-impedance until the chip is initialized and the outputs are activated. PLL_AVDD DVDD IO_DVDD t1 Normal Operation RESETB Reset t2 PDN t3 SDA Data SCL Figure 3-11. Power-On Reset Timing Table 3-9. Power-On Reset Timing NO. 24 PARAMETER MIN UNIT Delay time between power supplies active and reset t2 RESETB pulse duration 500 ns t3 Delay time between end of reset to I2C active 200 µs Functional Description 20 MAX t1 ms Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.19 Reset Sequence Table 3-10 shows the reset sequence of the TVP5151 pins status during reset time and immediately after reset time. Table 3-10. Reset Sequence PIN DESCRIPTION FID/GLCO, HSYNC, INTREQ/GPCL/VBLK, SCLK, VSYNC/PALI, YOUT[6:0] AIP1A, AIP1B, AVID/CLK_IN, RESETB, PDN, SDA, SCL, XTAL1/OSC XTAL2 YOUT7/I2CSEL DURING RESETB IMMEDIATELY AFTER RESETB High-impedance High-impedance Input Input Output Output Input High-impedance TVP5151 is pin compatible with TVP5150/A/AM1, and the following differences should be considered when an upgrade is planned. • IO_DVDD supply can be any voltage from 1.8 V to 3.3 V. • AVID/CLK_IN is input during RESETB. If this input is used as the clock source, XTAL1/OSC pin must be grounded. Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 25 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.20 Internal Control Registers The TVP5151 decoder is initialized and controlled by a set of internal registers that set all device operating parameters. Communication between the external controller and the TVP5151 decoder is through I2C. Table 3-11 shows the summary of these registers. The reserved registers must not be written. Reserved bits in the defined registers must be written with zeros, unless otherwise noted. The detailed programming information of each register is described in the following sections. Table 3-11. Register Summary ADDRESS DEFAULT R/W (1) Video input source selection #1 00h 00h R/W Analog channel controls 01h 15h R/W Operation mode controls 02h 00h R/W Miscellaneous controls 03h 00h R/W Autoswitch mask 04h DCh R/W Miscellaneous output controls 05h 00h R/W Color killer threshold control 06h 10h R/W Luminance processing control #1 07h 60h R/W Luminance processing control #2 08h 00h R/W Brightness control 09h 80h R/W Color saturation control 0Ah 80h R/W Hue control 0Bh 00h R/W Reserved 0Ch Outputs and data rates select 0Dh 47h R/W Luminance processing control #3 0Eh 00h R/W Configuration shared pins 0Fh 00h R/W Reserved 10h Active video cropping start pixel MSB 11h 00h R/W Active video cropping start pixel LSB 12h 00h R/W Active video cropping stop pixel MSB 13h 00h R/W Active video cropping stop pixel LSB 14h 00h R/W Genlock and RTC 15h 01h R/W Horizontal sync start 16h 80h R/W Reserved 17h Vertical blanking start 18h 00h R/W REGISTER Vertical blanking stop 19h 00h R/W Chrominance control #1 1Ah 0Ch R/W Chrominance control #2 1Bh 14h R/W Interrupt reset register B 1Ch 00h R/W Interrupt enable register B 1Dh 00h R/W Interrupt configuration register B 1Eh 00h R/W Reserved 1Fh-20h Indirect Register Data 21h-22h 00h R/W Indirect Register Address 23h 00h R/W Indirect Register Read/Write Strobe 24h 00h R/W 00h R/W Reserved 25h-27h Video standard Reserved 28h 29h–2Bh Cb gain factor (1) 26 2Ch R R = Read only, W = Write only, R/W = Read and write Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com Table 3-11. Register Summary (continued) REGISTER ADDRESS DEFAULT R/W (1) Cr gain factor 2Dh Macrovision on counter 2Eh 0Fh R/W Macrovision off counter 2Fh 01h R/W 656 revision select 30h 00h R/W Reserved R 31h–7Dh Patch Write Address 7Eh 00h R/W (2) Patch Code Execute 7Fh 00h R/W(2) Device ID MSB 80h 51h R Device ID LSB 81h 51h R ROM version 82h 04h R RAM version 83h 00h R Vertical line count MSB 84h R Vertical line count LSB 85h R Interrupt status register B 86h R Interrupt active register B 87h R Status register #1 88h R Status register #2 89h R Status register #3 8Ah R Status register #4 8Bh R Status register #5 8Ch R Reserved 8Dh Patch Read Address 8Eh Reserved 00h R/W(2) 8Fh Closed caption data 90h–93h R WSS data 94h–99h R VPS data 9Ah–A6h R VITC data A7h–AFh R VBI FIFO read data B0h R Teletext filter and mask 1 B1h–B5h 00h R/W Teletext filter and mask 2 B6h–BAh 00h R/W BBh 00h R/W Teletext filter control Reserved BCh–BFh Interrupt status register A C0h 00h R/W Interrupt enable register A C1h 00h R/W Interrupt configuration register A C2h 04h R/W VDP configuration RAM data C3h DCh R/W VDP configuration RAM address low byte C4h 0Fh R/W VDP configuration RAM address high byte C5h 00h R/W VDP status C6h FIFO word count C7h FIFO interrupt threshold C8h 80h FIFO reset C9h 00h W Line number interrupt CAh 00h R/W Pixel alignment LSB CBh 4Eh R/W Pixel alignment HSB CCh 00h R/W FIFO output control CDh 01h R/W (2) R R R/W These registers are used for firmware patch code and should not be written to or read from during normal operation. Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 27 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com Table 3-11. Register Summary (continued) REGISTER DEFAULT R/W (1) Reserved CEh Full field enable CFh 00h R/W D0h D1h–FBh 00h FFh R/W FCh 7Fh R/W Line mode Full field mode Reserved 28 ADDRESS FDh–FFh Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21 Register Definitions 3.21.1 Video Input Source Selection #1 Register Address Default 00h 00h 7 6 5 4 3 Black output Reserved 2 Reserved 1 Channel 1 source selection 0 S-video selection Channel 1 source selection 0 = AIP1A selected (default) 1 = AIP1B selected Table 3-12. Analog Channel and Video Mode Selection ADDRESS 00 INPUT(S) SELECTED Composite S-Video BIT 1 BIT 0 AIP1A (default) 0 0 AIP1B 1 0 AIP1A (luminance), AIP1B (chrominance) x 1 Black output 0 = Normal operation (default) 1 = Force black screen output (outputs synchronized) a. Forced to 10h in normal mode b. Forced to 01h in extended mode 3.21.2 Analog Channel Controls Register Address Default 7 01h 15h 6 Reserved 5 4 1 3 0 2 1 1 0 Automatic gain control Automatic gain control (AGC) 00 = AGC disabled (fixed gain value) 01 = AGC enabled (default) 10 = Reserved 11 = AGC frozen to the previously set value Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 29 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.3 Operation Mode Controls Register Address Default 7 Reserved 02h 00h 6 Color burst reference enable 5 4 TV/VCR mode 3 Composite peak disable 2 Color subcarrier PLL frozen 1 Luminance peak disable 0 Power-down mode Color burst reference enable 0 = Color burst reference for AGC disabled (default) 1 = Color burst reference for AGC enabled (not recommended) TV/VCR mode 00 = Automatic mode determined by the internal detection circuit (default) 01 = Reserved 10 = VCR (nonstandard video) mode 11 = TV (standard video) mode With automatic detection enabled, unstable or nonstandard syncs on the input video forces the detector into the VCR mode. This turns off the comb filters and turns on the chrominance trap filter. Composite peak disable 0 = Composite peak protection enabled (default) 1 = Composite peak protection disabled Color subcarrier PLL frozen 0 = Color subcarrier PLL increments by the internally generated phase increment (default). GLCO pin outputs the frequency increment. 1 = Color subcarrier PLL stops operating. GLCO pin outputs the frozen frequency increment. Luminance peak disable 0 = Luminance peak processing enabled (default) 1 = Luminance peak processing disabled Power-down mode 0 = Normal operation (default) 1 = Power-down mode. A/Ds are turned off and internal clocks are reduced to minimum. 30 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.4 Miscellaneous Controls Register Address Default 7 VBLK/GPCL select 03h 00h 6 GPCL logic level 5 INTREQ/GPCL/ VBLK output enable 4 Lock status (HVLK) 3 YCbCr output enable (TVPOE) 2 HSYNC, VSYNC/PALI, AVID, FID/GLCO output enable 1 Vertical blanking on/off 0 Clock output enable VBLK/GPCL function select (affects INTREQ/GPCL/VBLK output only if bit 1 of I2C register 0Fh is set to 1) 0 = GPCL (default) 1 = VBLK GPCL logic level (affects INTREQ/GPCL/VBLK output only if bit 7 is set to 0 and bit 5 is set to 1) 0 = GPCL is set to logic 0 (default) 1 = GPCL is set to logic 1 INTREQ/GPCL/VBLK output enable 0 = Output disabled (default) 1 = Output enabled (recommended) Note: The INTREQ/GPCL/VBLK output (pin 27) must never be left floating. An external 10-kΩ pulldown resistor is required when the INTREQ/GPCL/VBLK output is disabled (bit 5 of I2C register 03h is set to 0). Lock status (HVLK) (configured along with register 0Fh, see Figure 3-12 for the relationship between the configuration shared pins) 0 = Terminal VSYNC/PALI outputs the PAL indicator (PALI) signal and terminal FID/GLCO outputs the field ID (FID) signal (default) (if terminals are configured to output PALI and FID in register 0Fh). 1 = Terminal VSYNC/PALI outputs the horizontal lock indicator (HLK) and terminal FID outputs the vertical lock indicator (VLK) (if terminals are configured to output PALI and FID in register 0Fh). These are additional functions that are provided for ease of use. YCbCr output enable 0 = YOUT[7:0] high impedance (default) 1 = YOUT[7:0] active Note: YOUT7 must be pulled high or low for device I2C address select. HSYNC, VSYNC/PALI, active video indicator (AVID), and FID/GLCO output enables 0 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high-impedance (default). 1 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are active. Note: This control bit has no effect on the FID/GLCO output when it is programmed to output the GLCO signal (see bit 3 of address 0Fh). When the GLCO signal is selected, the FID/GLCO output is always active. Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 31 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com Vertical blanking on/off 0 = Vertical blanking (VBLK) off (default) 1 = Vertical blanking (VBLK) on Clock output enable 0 = SCLK output is high impedance (default) 1 = SCLK output is enabled Note: To achieve lowest power consumption, outputs placed in the high-impedance state should not be left floating. A 10-kΩ pulldown resistor is recommended if not driven externally. Note: When enabling the outputs, ensure the clock output is not accidently disabled. Table 3-13. Digital Output Control (1) REGISTER 03h, BIT 3 (TVPOE) REGISTER C2h, BIT 2 (VDPOE) YCbCr OUTPUT (1) 32 NOTES 0 X High impedance After both YCbCr output enable bits are programmed X 0 High impedance After both YCbCr output enable bits are programmed 1 1 Active After both YCbCr output enable bits are programmed VDPOE default is 1, and TVPOE default is 0. Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 0F(Bit 2) VSYNC/PALI 0F(Bit 4) LOCK24B VSYNC PALI HLK 0 HVLK 1 HVLK 1 VLK 0 0 M U X HLK/HVLK 1 M U X VLK/HVLK 1 FID 0 0 M U X PALI/HLK/HVLK 1 M U X FID/VLK/HVLK 0 GLCO 1 M U X VSYNC/PALI/HLK/HVLK M U X FID/GLCO/VLK/HVLK Pin 24 Pin 23 0F(Bit 6) LOCK23 0F(Bit 3) FID/GLCO 03(Bit 4) HVLK VBLK 1 GPCL 0 M U X VBLK/GPCL INTREQ 03(Bit 7) VBKO 1 0 M U X INTREQ/GPCL/VBLK 0F(Bit 1) INTREQ/GPCL/VBLK Pin 27 03(Bit 5) GPCL Ouput Enable Figure 3-12. Configuration Shared Pins NOTE Also see the configuration shared pins register at subaddress 0Fh. Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 33 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.5 Autoswitch Mask Register Address Default 04h DCh 7 6 Reserved 5 SEC_OFF 4 N4.43_OFF 3 PALN_OFF 2 PALM_OFF 1 0 Reserved N4.43_OFF 0 = NTSC4.43 is unmasked from the autoswitch process. Autoswitch does switch to NTSC4.43. 1 = NTSC4.43 is masked from the autoswitch process. Autoswitch does not switch to NTSC4.43 (default). PALN_OFF 0 = PAL-N is unmasked from the autoswitch process. Autoswitch does switch to PAL-N. 1 = PAL-N is masked from the autoswitch process. Autoswitch does not switch to PAL-N (default). PALM_OFF 0 = PAL-M is unmasked from the autoswitch process. Autoswitch does switch to PAL-M. 1 = PAL-M is masked from the autoswitch process. Autoswitch does not switch to PAL-M (default). SEC_OFF 0 = SECAM is unmasked from the autoswitch process. Autoswitch does switch to SECAM (default). 1 = SECAM is masked from the autoswitch process. Autoswitch does not switch to SECAM. 3.21.6 Miscellaneous Output Controls Register Address Default 05h 00h 7 6 5 4 3 2 1 AVID/CLK_IN function select 0 Reserved 3 2 Color killer threshold 1 0 Reserved AVID/CLK_IN function select 0 = CLK_IN (default) 1 = AVID 3.21.7 Color Killer Threshold Control Register Address Default 7 Reserved 06h 10h 6 5 Automatic color killer 4 Automatic color killer 00 = Automatic mode (default) 01 = Reserved 10 = Color killer enabled, CbCr terminals forced to a zero color state 11 = Color killer disabled Color killer threshold 11111 = –30 dB (minimum) 10000 = –24 dB (default) 00000 = –18 dB (maximum) 34 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.8 Luminance Processing Control #1 Register Address Default 7 2× luminance output enable 07h 60h 6 Pedestal not present 5 Disable raw header 4 Luminance bypass enabled during vertical blanking 3 2 1 0 Luminance signal delay with respect to chrominance signal 2× luminance output enable 0 = Output depends on bit 4, luminance bypass enabled during vertical blanking (default). 1 = Outputs 2x luminance samples during the entire frame. This bit takes precedence over bit 4. Pedestal not present 0 = 7.5 IRE pedestal is present on the analog video input signal. 1 = Pedestal is not present on the analog video input signal (default). Disable raw header 0 = Insert 656 ancillary headers for raw data 1 = Disable 656 ancillary headers and instead force dummy ones (40h) (default) Luminance bypass enabled during vertical blanking 0 = Disabled. If bit 7, 2× luminance output enable, is 0, normal luminance processing occurs and YCbCr samples are output during the entire frame (default). 1 = Enabled. If bit 7, 2× luminance output enable, is 0, normal luminance processing occurs and YCbCr samples are output during VACTIVE and 2× luminance samples are output during VBLK. Luminance bypass occurs for the duration of the vertical blanking as defined by registers 18h and 19h. Luminance bypass occurs for the duration of the vertical blanking as defined by registers 18h and 19h. Luminance signal delay with respect to chrominance signal in pixel clock increments (range –8 to +7 pixel clocks) 1111 = –8 pixel clocks delay 1011 = –4 pixel clocks delay 1000 = –1 pixel clocks delay 0000 = 0 pixel clocks delay (default) 0011 = +3 pixel clocks delay 0111 = +7 pixel clocks delay Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 35 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.9 Luminance Processing Control #2 Register Address Default 7 Reserved 08h 00h 6 Luminance filter select 5 4 3 Reserved 2 1 0 Mac AGC control 2 1 Peaking gain Luminance filter select 0 = Luminance comb filter enabled (default) 1 = Luminance chrominance trap filter enabled Peaking gain (sharpness) 00 = 0 (default) 01 = 0.5 10 = 1 11 = 2 Information on peaking frequency: ITU-R BT.601 sampling rate: all standards Peaking center frequency is 2.6 MHz. Mac AGC control 00 = Auto mode 01 = Auto mode 10 = Force Macrovision AGC pulse detection off 11 = Force Macrovision AGC pulse detection on 3.21.10 Brightness Control Register Address Default 7 09h 80h 6 5 4 3 0 Brightness[7:0] Brightness[7:0]: This register works for CVBS and S-Video luminance. 1111 1111 = 255 (bright) 1000 0000 = 128 (default) 0000 0000 = 0 (dark) The output black level relative to the nominal black level (64 out of 1024) as a function of the Brightness[7:0] setting is as follows: Black Level = nominal_black_level + (Brightness[7:0] – 128) 36 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.11 Color Saturation Control Register Address Default 0Ah 80h 7 6 5 4 3 2 1 0 Saturation[7:0] Saturation[7:0]: This register works for CVBS and S-Video chrominance. 1111 1111 = 255 (maximum) 1000 0000 = 128 (default) 0000 0000 = 0 (no color) The total chrominance gain relative to the nominal chrominance gain as a function of the Saturation[7:0] setting is as follows: Chrominance Gain = nominal_chrominance_gain × (Saturation[7:0] / 128) 3.21.12 Hue Control Register Address Default 7 0Bh 00h 6 5 4 3 2 1 0 Hue control Hue control (does not apply to SECAM) 0111 1111 = +180 degrees 0000 0000 = 0 degrees (default) 1000 0000 = –180 degrees Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 37 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.13 Outputs and Data Rates Select Register Address Default 7 Reserved 0Dh 47h 6 YCbCr output code range 5 CbCr code format 4 3 YCbCr data path bypass 2 1 YCbCr output format 0 YCbCr output code range 0 = ITU-R BT.601 coding range (Y ranges from 16 to 235. U and V range from 16 to 240) 1 = Extended coding range (Y, U, and V range from 1 to 254) (default) CbCr code format 0 = Offset binary code (2s complement + 128) (default) 1 = Straight binary code (2s complement) YCbCr data path bypass 00 = Normal operation (default) 01 = Decimation filter output connects directly to the YCbCr output pins. This data is similar to the digitized composite data, but the HBLANK area is replaced with ITU-R BT.656 digital blanking. 10 = Digitized composite (or digitized S-video luminance). A/D output connects directly to YCbCr output pins. 11 = Reserved YCbCr output format 000 = 8-bit 4:2:2 YCbCr with discrete sync output 001 = Reserved 010 = Reserved 011 = Reserved 100 = Reserved 101 = Reserved 110 = Reserved 111 = 8-bit ITU-R BT.656 interface with embedded sync output (default) 38 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.14 Luminance Processing Control #3 Register Address Default 7 0Eh 00h 6 5 4 3 2 Reserved 1 0 Luminance trap filter select Luminance filter stop band bandwidth (MHz) 00 = No notch (default) 01 = Notch 1 10 = Notch 2 11 = Notch 3 Luminance filter select [1:0] selects one of the four chrominance trap (notch) filters to produce luminance signal by removing the chrominance signal from the composite video signal. The stopband of the chrominance trap filter is centered at the chrominance subcarrier frequency with stopband bandwidth controlled by the two control bits. See the following table for the stopband bandwidths. The WCF bit is controlled in the chrominance control #2 register, see Section 3.21.25. WCF 0 1 FILTER SELECT NTSC/PAL/SECAM ITU-R BT.601 00 1.2244 01 0.8782 10 0.7297 11 0.4986 00 1.4170 01 1.0303 10 0.8438 11 0.5537 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 39 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.15 Configuration Shared Pins Register Address Default 7 Reserved 0Fh 00h 6 LOCK23 5 Reserved 4 LOCK24B 3 FID/GLCO 2 VSYNC/PALI 1 INTREQ/ GPCL/VBLK 0 Reserved, must be set to 0 LOCK23 (pin 23) function select 0 = FID (default, if bit 3 is selected to output FID) 1 = Lock indicator (indicates whether the device is locked vertically) LOCK24B (pin 24) function select 0 = PALI (default, if bit 2 is selected to output PALI) 1 = Lock indicator (indicates whether the device is locked horizontally) FID/GLCO (pin 23) function select (also see register 03h for enhanced functionality) 0 = FID (default) 1 = GLCO VSYNC/PALI (pin 24) function select (also see register 03h for enhanced functionality) 0 = VSYNC (default) 1 = PALI INTREQ/GPCL/VBLK (pin 27) function select 0 = INTREQ (default) 1 = GPCL or VBLK depending on bit 7 of register 03h See Figure 3-12 for the relationship between the configuration shared pins. 3.21.16 Active Video Cropping Start Pixel MSB Register Address Default 7 11h 00h 6 5 4 3 AVID start pixel MSB [9:2] 2 1 0 Active video cropping start pixel MSB [9:2], set this register first before setting register 12h. The TVP5151 decoder updates the AVID start values only when register 12h is written to. This start pixel value is relative to the default values of the AVID start pixel. 40 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.17 Active Video Cropping Start Pixel LSB Register Address Default 12h 00h 7 6 5 Reserved 4 3 2 AVID active 1 0 AVID start pixel LSB [1:0] AVID active 0 = AVID out active in VBLK (default) 1 = AVID out inactive in VBLK Active video cropping start pixel LSB [1:0]: The TVP5151 decoder updates the AVID start values only when this register is written to. AVID start [9:0] (combined registers 11h and 12h) 01 1111 1111 = 511 00 0000 0001 = 1 00 0000 0000 = 0 (default) 11 1111 1111 = –1 10 0000 0000 = –512 3.21.18 Active Video Cropping Stop Pixel MSB Register Address Default 13h 00h 7 6 5 4 3 AVID stop pixel MSB [9:2] 2 1 0 Active video cropping stop pixel MSB [9:2], set this register first before setting the register 14h. The TVP5151 decoder updates the AVID stop values only when register 14h is written to. This stop pixel value is relative to the default values of the AVID stop pixel. 3.21.19 Active Video Cropping Stop Pixel LSB Register Address Default 7 14h 00h 6 5 4 3 Reserved 2 1 0 AVID stop pixel LSB Active video cropping stop pixel LSB [1:0]: The number of pixels of active video must be an even number. The TVP5151 decoder updates the AVID stop values only when this register is written to. AVID stop [9:0] (combined registers 13h and 14h) 01 1111 1111 = 511 00 0000 0001 = 1 00 0000 0000 = 0 (default) (see Figure 3-6 and Figure 3-7) 11 1111 1111 = –1 10 0000 0000 = –512 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 41 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.20 Genlock and RTC Register Address Default 15h 01h 7 6 5 Reserved 4 3 Reserved F/V bit control 2 1 GLCO/RTC 0 F/V bit control BIT 5 0 BIT 4 NUMBER OF LINES 0 0 1 1 0 1 1 F BIT V BIT Standard ITU-R BT.656 ITU-R BT.656 Nonstandard even Force to 1 Switch at field boundary Nonstandard odd Toggles Switch at field boundary Standard ITU-R BT.656 ITU-R BT.656 Nonstandard Toggles Switch at field boundary Standard ITU-R BT.656 ITU-R BT.656 Nonstandard Pulse mode Switch at field boundary Illegal GLCO/RTC. The following table shows the different modes. BIT 2 BIT 1 BIT 0 GENLOCK/RTC MODE 0 X 0 GLCO 0 X 1 RTC output mode 0 (default) 1 X 0 GLCO 1 X 1 RTC output mode 1 All other values are reserved. Figure 3-9 shows the timing of GLCO, and Figure 3-10 shows the timing of RTC. 3.21.21 Horizontal Sync Start Register Address Default 7 16h 80h 6 5 4 3 2 1 0 HSYNC start Horizontal sync (HSYNC) start 1111 1111 = –127 × 4 pixel clocks 1111 1110 = –126 × 4 pixel clocks 1000 0001 = –1 × 4 pixel clocks 1000 0000 = 0 pixel clocks (default) 0111 1111 = 1 × 4 pixel clocks 0111 1110 = 2 × 4 pixel clocks 0000 0000 = 128 × 4 pixel clocks 42 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com BT.656 EAV Code U Y V Y F F YOUT[7:0] 0 0 0 0 X Y BT.656 SAV Code 8 0 1 0 8 0 1 0 F F 0 0 0 0 X Y U Y HSYNC AVID 128 SCLK Start of Digital Line Start of Digital Active Line Nhbhs Nhb Figure 3-13. Horizontal Sync Table 3-14. Clock Delays (SCLKs) STANDARD Nhbhs Nhb NTSC 28 272 PAL 32 284 SECAM 32 284 Detailed timing information is also available in Section 3.12. 3.21.22 Vertical Blanking Start Register Address Default 7 18h 00h 6 5 4 3 Vertical blanking start 2 1 0 Vertical blanking (VBLK) start 0111 1111 = 127 lines after start of vertical blanking interval 0000 0001 = 1 line after start of vertical blanking interval 0000 0000 = Same time as start of vertical blanking interval (default) (see Figure 3-5) 1111 1111 = 1 line before start of vertical blanking interval 1000 0000 = 128 lines before start of vertical blanking interval Vertical blanking is adjustable with respect to the standard vertical blanking intervals. The setting in this register determines the timing of the INTREQ/GPCL/VBLK signal when it is configured to output vertical blank (see register 03h). The setting in this register also determines the duration of the luminance bypass function (see register 07h). Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 43 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.23 Vertical Blanking Stop Register Address Default 19h 00h 7 6 5 4 3 Vertical blanking stop 2 1 0 Vertical blanking (VBLK) stop 0111 1111 = 127 lines after stop of vertical blanking interval 0000 0001 = 1 line after stop of vertical blanking interval 0000 0000 = Same time as stop of vertical blanking interval (default) (see Figure 3-5) 1111 1111 = 1 line before stop of vertical blanking interval 1000 0000 = 128 lines before stop of vertical blanking interval Vertical blanking is adjustable with respect to the standard vertical blanking intervals. The setting in this register determines the timing of the INTREQ/GPCL/VBLK signal when it is configured to output vertical blank (see register 03h). The setting in this register also determines the duration of the luminance bypass function (see register 07h). 3.21.24 Chrominance Control #1 Register Address Default 7 1Ah 0Ch 6 Reserved 5 4 Color PLL reset 3 Chrominance adaptive comb filter enable (ACE) 2 Chrominance comb filter enable (CE) 1 0 Automatic color gain control Color PLL reset 0 = Color PLL not reset (default) 1 = Color PLL reset When a 1 is written to this bit, the color PLL phase is reset to zero and the subcarrier PLL phase reset bit is transmitted on terminal 23 (GLCO) on the next line (NTSC or PAL). Chrominance adaptive comb filter enable (ACE) 0 = Disable 1 = Enable (default) Chrominance comb filter enable (CE) 0 = Disable 1 = Enable (default) Automatic color gain control (ACGC) 00 = ACGC enabled (default) 01 = Reserved 10 = ACGC disabled 11 = ACGC frozen to the previously set value 44 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.25 Chrominance Control #2 Register Address Default 7 1Bh 14h 6 5 Reserved 4 3 2 WCF 1 0 Chrominance filter select Wideband chrominance filter (WCF) 0 = Disable 1 = Enable (default) Chrominance low pass filter select 00 = No notch (default) 01 = Notch 1 10 = Notch 2 11 = Notch 3 Chrominance output bandwidth (MHz) WCF 0 1 FILTER SELECT NTSC/PAL/SECAM ITU-R BT.601 00 1.2214 01 0.8782 10 0.7297 11 0.4986 00 1.4170 01 1.0303 10 0.8438 11 0.5537 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 45 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.26 Interrupt Reset Register B Address Default 7 Software initialization reset 1Ch 00h 6 Macrovision detect changed reset 5 Reserved 4 Field rate changed reset 3 Line alternation changed reset 2 Color lock changed reset 1 H/V lock changed reset 0 TV/VCR changed reset Interrupt reset register B is used by the external processor to reset the interrupt status bits in interrupt status register B. Bits loaded with a 1 allow the corresponding interrupt status bit to reset to 0. Bits loaded with a 0 have no effect on the interrupt status bits. Software initialization reset 0 = No effect (default) 1 = Reset software initialization bit Macrovision detect changed reset 0 = No effect (default) 1 = Reset Macrovision detect changed bit Field rate changed reset 0 = No effect (default) 1 = Reset field rate changed bit Line alternation changed reset 0 = No effect (default) 1 = Reset line alternation changed bit Color lock changed reset 0 = No effect (default) 1 = Reset color lock changed bit H/V lock changed reset 0 = No effect (default) 1 = Reset H/V lock changed bit TV/VCR changed reset [TV/VCR mode is determined by counting the total number of lines/frame. The mode switches to VCR for nonstandard number of lines] 0 = No effect (default) 1 = Reset TV/VCR changed bit 46 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.27 Interrupt Enable Register B Address Default 7 Software initialization occurred 1Dh 00h 6 Macrovision detect changed 5 Reserved 4 Field rate changed 3 Line alternation changed 2 Color lock changed 1 H/V lock changed 0 TV/VCR changed Interrupt enable register B is used by the external processor to mask unnecessary interrupt sources for interrupt B. Bits loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the external pin. Conversely, bits loaded with zeros mask the corresponding interrupt condition from generating an interrupt on the external pin. This register only affects the external pin, it does not affect the bits in the interrupt status register. A given condition can set the appropriate bit in the status register and not cause an interrupt on the external pin. To determine if this device is driving the interrupt pin either AND interrupt status register B with interrupt enable register B or check the state of interrupt B in the interrupt B active register. Software initialization occurred 0 = Disabled (default) 1 = Enabled Macrovision detect changed 0 = Disabled (default) 1 = Enabled Field rate changed 0 = Disabled (default) 1 = Enabled Line alternation changed 0 = Disabled (default) 1 = Enabled Color lock changed 0 = Disabled (default) 1 = Enabled H/V lock changed 0 = Disabled (default) 1 = Enabled TV/VCR changed 0 = Disabled (default) 1 = Enabled Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 47 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.28 Interrupt Configuration Register B Address Default 1Eh 00h 7 6 5 4 Reserved 3 2 1 0 Interrupt polarity B Interrupt polarity B 0 = Interrupt B is active low (default). 1 = Interrupt B is active high. Interrupt polarity B must be the same as interrupt polarity A of Interrupt Configuration Register A at Address C2h. Interrupt Configuration Register B is used to configure the polarity of interrupt B on the external interrupt pin. When the interrupt B is configured for active low, the pin is driven low when active and high impedance when inactive (open-drain). Conversely, when the interrupt B is configured for active high, it is driven high for active and driven low for inactive. Note: An external pullup resistor (4.7 kΩ to 10 kΩ) is required when the polarity of the external interrupt terminal (pin 27) is configured as active low. 3.21.29 Indirect Register Data Address Default 21h-22h 00h Address 22h 21h 7 6 5 4 3 2 1 0 Data[15:8] Data[7:0] I2C registers 21h and 22h can be used to write data to or read data from indirect registers. See I2C registers 23h and 24h. 3.21.30 Indirect Register Address Address Default 7 23h 00h 6 5 4 3 2 1 0 ADDR[7:0] ADDR[7:0] = LSB of indirect address 48 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.31 Indirect Register Read/Write Strobe Address Default 24h 00h 7 6 5 4 3 2 1 0 R/W[7:0] This register selects the most significant bits of the indirect register address and performs either an indirect read or write operation. Data will be written from are read to Indirect Register Data registers 21h-22h. R/W[7:0]: 01h = read from 00h-1FFh address bank 02h = write to 00h-1FFh address bank 03h = read from 200h-3FFh address bank 04h = write to 200h-3FFh address bank 05h = read from 300h-3FFh address bank 06h = write to 300h-3FFh address bank 3.21.32 Video Standard Register Address Default 7 28h 00h 6 5 4 3 Reserved 2 1 0 Video standard Video standard 0000 = Autoswitch mode (default) 0001 = Reserved 0010 = (M, J) NTSC ITU-R BT.601 0011 = Reserved 0100 = (B, G, H, I, N) PAL ITU-R BT.601 0101 = Reserved 0110 = (M) PAL ITU-R BT.601 0111 = Reserved 1000 = (Combination-N) PAL ITU-R BT.601 1001 = Reserved 1010 = NTSC 4.43 ITU-R BT.601 1011 = Reserved 1100 = SECAM ITU-R BT.601 With the autoswitch code running, the application can force the device to operate in a particular video standard mode by writing the appropriate value into this register. Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 49 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.33 Cb Gain Factor Register Address 2Ch 7 6 5 4 3 2 1 0 Cb gain factor This is a read-only register that provides the gain applied to the Cb in the YCbCr data stream. 3.21.34 Cr Gain Factor Register Address 2Dh 7 6 5 4 3 2 1 0 Cr gain factor This is a read-only register that provides the gain applied to the Cr in the YCbCr data stream. 3.21.35 Macrovision On Counter Register Address Default 2Eh 0Fh 7 6 5 4 3 Macrovision on counter 2 1 0 This register allows the user to determine how many consecutive frames in which the Macrovision AGC pulses are detected before the decoder decides that the Macrovision AGC pulses are present. 3.21.36 Macrovision Off Counter Register Address Default 2Fh 01h 7 6 5 4 3 Macrovision off counter 2 1 0 This register allows the user to determine how many consecutive frames in which the Macrovision AGC pulses are not detected before the decoder decides that the Macrovision AGC pulses are not present. 3.21.37 656 Revision Select Register Address Default 7 30h 00h 6 5 4 Reserved 3 2 1 0 656 revision select 656 revision select 0 = Adheres to ITU-R BT.656.4 and BT.656.5 timing (default) 1 = Adheres to ITU-R BT.656.3 timing 50 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.38 Patch Write Address Address Default 7Eh 00h 7 6 5 4 3 2 1 0 R/W[7:0] This register is used for downloading firmware patch code. Please refer to the patch load application note for more detail. This register must not be written to or read from during normal operation. 3.21.39 Patch Code Execute Address Default 7Fh 00h 7 6 5 4 3 2 1 0 R/W[7:0] Writing to this register following a firmware patch load restarts the CPU and initiates execution of the patch code. This register must not be written to or read from during normal operation. 3.21.40 MSB of Device ID Register Address Default 80h 51h 7 6 5 4 3 MSB of device ID 2 1 0 2 1 0 This register identifies the MSB of the device ID. Value = 51h. 3.21.41 LSB of Device ID Register Address Default 7 81h 51h 6 5 4 3 LSB of device ID This register identifies the LSB of the device ID. Value = 51h. Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 51 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.42 ROM Version Register Address Default 82h 04h 7 6 5 4 3 ROM version [7:0] 2 1 0 1 0 ROM Version [7:0]: This register identifies the ROM code revision number. 3.21.43 RAM Version Register Address Default 83h 00h 7 6 5 4 3 RAM version [7:0] 2 RAM Version [7:0]: This register identifies the RAM code revision number. Example: Patch Release = v01.25 ROM Version = 01h RAM Version = 25h Note: Use of the latest patch release is highly recommended. 3.21.44 Vertical Line Count MSB Register Address 84h 7 6 5 4 3 2 Reserved 1 0 Vertical line count MSB Vertical line count bits [9:8] 3.21.45 Vertical Line Count LSB Register Address 7 85h 6 5 4 3 Vertical line count LSB 2 1 0 Vertical line count bits [7:0] Registers 84h and 85h can be read and combined to extract the detected number of lines per frame. This can be used with nonstandard video signals such as a VCR in fast-forward or rewind modes to synchronize the downstream video circuitry. 52 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.46 Interrupt Status Register B Address 7 Software initialization 86h 6 Macrovision detect changed 5 Reserved 4 Field rate changed 3 Line alternation changed 2 Color lock changed 1 H/V lock changed 0 TV/VCR changed Software initialization 0 = Software initialization is not ready. 1 = Software initialization is ready. Macrovision detect changed 0 = Macrovision detect status has not changed. 1 = Macrovision detect status has changed. Field rate changed 0 = Field rate has not changed. 1 = Field rate has changed. Line alternation changed 0 = Line alteration has not changed. 1 = Line alternation has changed. Color lock changed 0 = Color lock status has not changed. 1 = Color lock status has changed. H/V lock changed 0 = H/V lock status has not changed. 1 = H/V lock status has changed. TV/VCR changed 0 = TV/VCR status has not changed. 1 = TV/VCR status has changed. Interrupt status register B is polled by the external processor to determine the interrupt source for interrupt B. After an interrupt condition is set, it can be reset by writing to the interrupt reset register B at subaddress 1Ch with a 1 in the appropriate bit. Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 53 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.47 Interrupt Active Register B Address 87h 7 6 5 4 Reserved 3 2 1 0 Interrupt B Interrupt B 0 = Interrupt B is not active on the external terminal (default). 1 = Interrupt B is active on the external terminal. The interrupt active register B is polled by the external processor to determine if interrupt B is active. 3.21.48 Status Register #1 Address 7 Peak white detect status 88h 6 Line-alternating status 5 Field rate status 4 Lost lock detect 3 Color subcarrier lock status 2 Vertical sync lock status 1 Horizontal sync lock status 0 TV/VCR status Peak white detect status 0 = Peak white is not detected. 1 = Peak white is detected. Line-alternating status 0 = Nonline alternating 1 = Line alternating Field rate status 0 = 60 Hz 1 = 50 Hz Lost lock detect 0 = No lost lock since status register #1 was last read. 1 = Lost lock since status register #1 was last read. Color subcarrier lock status 0 = Color subcarrier is not locked. 1 = Color subcarrier is locked. Vertical sync lock status 0 = Vertical sync is not locked. 1 = Vertical sync is locked. Horizontal sync lock status 0 = Horizontal sync is not locked. 1 = Horizontal sync is locked. TV/VCR status. TV mode is determined by detecting standard line-to-line variations and specific chrominance SCH phases based on the standard input video format. VCR mode is determined by detecting variations in the chrominance SCH phases compared to the chrominance SCH phases of the standard input video format. 0 = TV 1 = VCR 54 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.49 Status Register #2 Address 7 Reserved 89h 6 Weak signal detection 5 PAL switch polarity 4 Field sequence status 3 AGC and offset frozen status 2 1 Macrovision detection 0 Weak signal detection 0 = No weak signal 1 = Weak signal mode PAL switch polarity of first line of odd field 0 = PAL switch is 0. 1 = PAL switch is 1. Field sequence status 0 = Even field 1 = Odd field AGC and offset frozen status 0 = AGC and offset are not frozen. 1 = AGC and offset are frozen. Macrovision detection 000 = No copy protection 001 = AGC process present (Macrovision Type 1 present) 010 = Colorstripe process Type 2 present 011 = AGC process and colorstripe process Type 2 present 100 = Reserved 101 = Reserved 110 = Colorstripe process Type 3 present 111 = AGC process and color stripe process Type 3 present Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 55 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.50 Status Register #3 Address 8Ah 7 6 5 4 3 2 Analog gain 1 0 Digital gain Analog gain: 4-bit front-end AGC analog gain setting Digital gain: 4 MSBs of 6-bit front-end AGC digital gain setting The product of the analog and digital gain is as follows: Gain Product = (1 + 3 × analog_gain / 15) × (1 + gain_step × digital_gain / 4096) Where, 0 ≤ analog_gain ≤ 15 0 ≤ digital_gain ≤ 63 The gain_step setting as a function of the analog_gain setting is shown in Table 3-15. Table 3-15. gain_step Setting analog_gain gain_step 0 61 1 55 2 48 3 44 4 38 5 33 6 29 7 26 8 24 9 22 10 20 11 19 12 18 13 17 14 16 15 15 3.21.51 Status Register #4 Address 7 8Bh 6 5 4 3 Subcarrier to horizontal (SCH) phase 2 1 0 SCH (color PLL subcarrier phase at 50% of the falling edge of horizontal sync of line one of odd field; step size 360°/256) 0000 0000 = 0.00° 0000 0001 = 1.41° 0000 0010 = 2.81° 1111 1110 = 357.2° 1111 1111 = 358.6° 56 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.52 Status Register #5 Address 8Ch 7 Autoswitch mode 6 5 Reserved 4 3 2 Video standard 1 0 Sampling rate (SR) This register contains information about the detected video standard at which the device is currently operating. When autoswitch code is running, this register must be tested to determine which video standard has been detected. Autoswitch mode 0 = Forced video standard 1 = Autoswitch mode Video standard VIDEO STANDARD [3:1] SR VIDEO STANDARD BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 Reserved 0 0 0 1 (M, J) NTSC ITU-R BT.601 0 0 1 0 Reserved 0 0 1 1 (B, D, G, H, I, N) PAL ITU-R BT.601 0 1 0 0 Reserved 0 1 0 1 (M) PAL ITU-R BT.601 0 1 1 0 Reserved 0 1 1 1 PAL-Nc ITU-R BT.601 1 0 0 0 Reserved 1 0 0 1 NTSC 4.43 ITU-R BT.601 1 0 1 0 Reserved 1 0 1 1 SECAM ITU-R BT.601 3.21.53 Patch Read Address Address Default 7 8Eh 00h 6 5 4 3 2 1 0 R/W[7:0] This register can be used for patch code read-back. This register must not be written to or read from during normal operation. Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 57 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.54 Closed Caption Data Registers Address 90h–93h Address 90h 91h 92h 93h 7 6 5 4 Closed Closed Closed Closed 3 caption field 1 byte caption field 1 byte caption field 2 byte caption field 2 byte 2 1 0 1 2 1 2 These registers contain the closed caption data arranged in bytes per field. 3.21.55 WSS/CGMS-A Data Registers Address 94h–99h NTSC Address 94h 95h 96h 97h 98h 99h 7 6 b13 b12 b13 b12 5 b5 b11 b19 b5 b11 b19 4 b4 b10 b18 b4 b10 b18 3 b3 b9 b17 b3 b9 b17 2 b2 b8 b16 b2 b8 b16 1 b1 b7 b15 b1 b7 b15 0 b0 b6 b14 b0 b6 b14 BYTE WSS field 1 byte WSS field 1 byte WSS field 1 byte WSS field 2 byte WSS field 2 byte WSS field 2 byte 1 2 3 1 2 3 These registers contain the wide screen signaling (WSS/CGMS-A) data for NTSC. For NTSC, the bits are: Bits 0–1 represent word 0, aspect ratio. Bits 2–5 represent word 1, header code for word 2. Bits 6–13 represent word 2, copy control. Bits 14–19 represent word 3, CRC. PAL/SECAM Address 94h 95h 96h 97h 98h 99h 7 b7 6 b6 5 b5 b13 b7 b6 b5 b13 4 3 b4 b3 b12 b11 Reserved b4 b3 b12 b11 Reserved 2 b2 b10 1 b1 b9 0 b0 b8 BYTE WSS field 1 byte 1 WSS field 1 byte 2 b2 b10 b1 b9 b0 b8 WSS field 2 byte 1 WSS field 2 byte 2 For PAL/SECAM, the bits are: Bits 0–3 represent group 1, aspect ratio. Bits 4–7 represent group 2, enhanced services. Bits 8–10 represent group 3, subtitles. Bits 11–13 represent group 4, others. 58 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.56 VPS Data Registers Address 9Ah–A6h Address 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h 7 6 5 4 3 2 1 0 VPS byte 1 VPS byte 2 VPS byte 3 VPS byte 4 VPS byte 5 VPS byte 6 VPS byte 7 VPS byte 8 VPS byte 9 VPS byte 10 VPS byte 11 VPS byte 12 VPS byte 13 These registers contain the entire VPS data line except the clock run-in code and the start code. 3.21.57 VITC Data Registers Address A7h–AFh Address A7h A8h A9h AAh ABh ACh ADh AEh AFh 7 6 5 4 3 VITC byte 1, frame byte 1 VITC byte 2, frame byte 2 VITC byte 3, seconds byte 1 VITC byte 4, seconds byte 2 VITC byte 5, minutes byte 1 VITC byte 6, minutes byte 2 VITC byte 7, hour byte 1 VITC byte 8, hour byte 2 VITC byte 9, CRC 2 1 0 These registers contain the VITC data. 3.21.58 VBI FIFO Read Data Register Address 7 B0h 6 5 4 3 2 1 0 FIFO read data This address is provided to access VBI data in the FIFO through the host port. All forms of teletext data come directly from the FIFO, while all other forms of VBI data can be programmed to come from the registers or from the FIFO. Current status of the FIFO can be found at address C6h and the number of bytes in the FIFO is located at address C7h. If the host port is to be used to read data from the FIFO, then the host access enable bit at address CDh must be set to 1. The format used for the VBI FIFO is shown in Section 3.9. Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 59 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.59 Teletext Filter and Mask Registers Address Default Address B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh B1h–BAh 00h 7 6 Filter Filter Filter Filter Filter Filter Filter Filter Filter Filter 1 1 1 1 1 2 2 2 2 2 5 mask 1 mask 2 mask 3 mask 4 mask 5 mask 1 mask 2 mask 3 mask 4 mask 5 4 3 2 Filter Filter Filter Filter Filter Filter Filter Filter Filter Filter 1 1 1 1 1 2 2 2 2 2 1 pattern 1 pattern 2 pattern 3 pattern 4 pattern 5 pattern 1 pattern 2 pattern 3 pattern 4 pattern 5 0 For an NABTS system, the packet prefix consists of five bytes. Each byte contains four data bits (D[3:0]) interlaced with four Hamming protection bits (H[3:0]): 7 D[3] 6 H[3] 5 D[2] 4 H[2] 3 D[1] 2 H[1] 1 D[0] 0 H[0] Only the data portion D[3:0] from each byte is applied to a teletext filter function with the corresponding pattern bits P[3:0] and mask bits M[3:0]. Hamming protection bits are ignored by the filter. For a WST system (PAL or NTSC), the packet prefix consists of two bytes so that two patterns are used. Patterns 3, 4, and 5 are ignored. The mask bits enable filtering using the corresponding bit in the pattern register. For example, a 1 in the LSB of mask 1 means that the filter module must compare the LSB of nibble 1 in the pattern register to the first data bit on the transaction. If these match, a true result is returned. A 0 in a bit of mask 1 means that the filter module must ignore that data bit of the transaction. If all zeros are programmed in the mask bits, the filter matches all patterns returning a true result (default 00h). Pattern and mask for each byte and filter are referred as <1,2><P,M><1,2,3,4,5>, where: <1,2> identifies the filter 1 or 2 <P,M> identifies the pattern or mask <1,2,3,4,5> identifies the byte number 60 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.60 Teletext Filter Control Register Address Default 7 BBh 00h 6 Reserved 5 4 3 Filter logic 2 Mode 1 TTX filter 2 enable 0 TTX filter 1 enable Filter logic allows different logic to be applied when combining the decision of filter 1 and filter 2 as follows: 00 = NOR (Default) 01 = NAND 10 = OR 11 = AND Mode 0 = Teletext WST PAL mode B (2 header bytes) (default) 1 = Teletext NABTS NTSC mode C (5 header bytes) TTX filter 2 enable 0 = Disabled (default) 1 = Enabled TTX filter 1 enable 0 = Disabled (default) 1 = Enabled If the filter matches or if the filter mask is all zeros, a true result is returned. Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 61 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.61 Interrupt Status Register A Address Default 7 Lock state interrupt C0h 00h 6 Lock interrupt 5 4 Reserved 3 2 FIFO threshold interrupt 1 Line interrupt 0 Data interrupt The interrupt status register A can be polled by the host processor to determine the source of an interrupt. After an interrupt condition is set it can be reset by writing to this register with a 1 in the appropriate bit(s). Lock state interrupt 0 = TVP5151 is not locked to the video signal (default). 1 = TVP5151 is locked to the video signal. Lock interrupt 0 = A transition has not occurred on the lock signal (default). 1 = A transition has occurred on the lock signal. FIFO threshold interrupt 0 = The amount of data in the FIFO has not yet crossed the threshold programmed at address C8h (default). 1 = The amount of data in the FIFO has crossed the threshold programmed at address C8h. Line interrupt 0 = The video line number has not yet been reached (default). 1 = The video line number programmed in address CAh has occurred. Data interrupt 0 = No data is available (default). 1 = VBI data is available either in the FIFO or in the VBI data registers. 62 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.62 Interrupt Enable Register A Address Default 7 Reserved C1h 00h 6 Lock interrupt enable 5 4 Reserved 3 2 FIFO threshold interrupt enable 1 Line interrupt enable 0 Data interrupt enable The interrupt enable register A is used by the host processor to mask unnecessary interrupt sources. Bits loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the external pin. Conversely, bits loaded with a 0 mask the corresponding interrupt condition from generating an interrupt on the external pin. This register only affects the interrupt on the external terminal, it does not affect the bits in interrupt status register A. A given condition can set the appropriate bit in the status register and not cause an interrupt on the external terminal. To determine if this device is driving the interrupt terminal, either perform a logical AND of interrupt status register A with interrupt enable register A, or check the state of the interrupt A bit in the interrupt configuration register at address C2h. Lock interrupt enable 0 = Disabled (default) 1 = Enabled FIFO threshold interrupt enable 0 = Disabled (default) 1 = Enabled Line interrupt enable 0 = Disabled (default) 1 = Enabled Data interrupt enable 0 = Disabled (default) 1 = Enabled Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 63 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.63 Interrupt Configuration Register A Address Default C2h 04h 7 6 5 Reserved 4 3 2 YCbCr enable (VDPOE) 1 Interrupt A 0 Interrupt polarity A YCbCr enable (VDPOE) 0 = YCbCr pins are high impedance. 1 = YCbCr pins are active if other conditions are met (default) (see Table 3-13). Interrupt A (read only) 0 = Interrupt A is not active on the external pin (default). 1 = Interrupt A is active on the external pin. Interrupt polarity A must be the same as interrupt polarity B of Interrupt Configuration Register B at Address 1Eh. Interrupt polarity A 0 = Interrupt A is active low (default). 1 = Interrupt A is active high. Interrupt configuration register A is used to configure the polarity of the external interrupt terminal. When interrupt A is configured as active low, the terminal is driven low when active and high impedance when inactive (open drain). Conversely, when the terminal is configured as active high, it is driven high when active and driven low when inactive. Note: An external pullup resistor (4.7 kΩ to 10 kΩ) is required when the polarity of the external interrupt terminal (pin 27) is configured as active low. 3.21.64 VDP Configuration RAM Register Address Default Address C3h C4h C5h C3h DCh C4h 0Fh 7 C5h 00h 6 5 4 3 Configuration data RAM address (7:0) Reserved 2 1 0 RAM address 8 The configuration RAM data is provided to initialize the VDP with initial constants. The configuration RAM is 512 bytes organized as 32 different configurations of 16 bytes each. The first 12 configurations are defined for the current VBI standards. An additional two configurations can be used as a custom programmed mode for unique standards such as Gemstar. Address C3h is used to read or write to the RAM. The RAM internal address counter is automatically incremented with each transaction. Addresses C5h and C4h make up a 9-bit address to load the internal address counter with a specific start address. This can be used to write a subset of the RAM for only those standards of interest. NOTE Registers D0h–FBh must all be programmed with FFh before writing or reading the configuration RAM. Full field mode (CFh) must be disabled as well. 64 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com The suggested RAM contents are shown in Table 3-16. All values are hexadecimal. Table 3-16. VBI Configuration RAM for Signals With Pedestal ADDRESS 0 1 2 3 4 5 6 7 8 9 A B C D E F WST SECAM INDEX 000 AA AA FF FF E7 2E 20 A6 E4 B4 0E 0 7 0 10 0 WST SECAM 010 AA AA FF FF E7 2E 20 A6 E4 B4 0E 0 7 0 10 0 WST PAL B 020 AA AA FF FF 27 2E 20 AB A4 72 10 0 7 0 10 0 WST PAL B 030 AA AA FF FF 27 2E 20 AB A4 72 10 0 7 0 10 0 WST PAL C 040 AA AA FF FF E7 2E 20 22 A4 98 0D 0 0 0 10 0 WST PAL C 050 AA AA FF FF E7 2E 20 22 A4 98 0D 0 0 0 10 0 WST NTSC 060 AA AA FF FF 27 2E 20 23 63 93 0D 0 0 0 10 0 WST NTSC 070 AA AA FF FF 27 2E 20 23 63 93 0D 0 0 0 10 0 NABTS, NTSC 080 AA AA FF FF E7 2E 20 A2 63 93 0D 0 7 0 15 0 NABTS, NTSC 090 AA AA FF FF E7 2E 20 A2 63 93 0D 0 7 0 15 0 NABTS, NTSC-J 0A0 AA AA FF FF A7 2E 20 A3 63 93 0D 0 7 0 10 0 NABTS, NTSC-J 0B0 AA AA FF FF A7 2E 20 A3 63 93 0D 0 7 0 10 0 CC, PAL/SECAM 0C0 AA 2A FF 3F 04 51 6E 02 A4 7B 09 0 0 0 27 0 CC, PAL/SECAM 0D0 AA 2A FF 3F 04 51 6E 02 A4 7B 09 0 0 0 27 0 CC, NTSC 0E0 AA 2A FF 3F 04 51 6E 02 63 8C 09 0 0 0 27 0 CC, NTSC 0F0 AA 2A FF 3F 04 51 6E 02 63 8C 09 0 0 0 27 0 WSS/CGMS-A, PAL/SECAM 100 5B 55 C5 FF 0 71 6E 42 A4 CD 0F 0 0 0 3A 0 WSS/CGMS-A, PAL/SECAM 110 5B 55 C5 FF 0 71 6E 42 A4 CD 0F 0 0 0 3A 0 WSS/CGMS-A, NTSC C 120 38 00 3F 00 0 71 6E 43 63 7C 08 0 0 0 39 0 WSS/CGMS-A, NTSC C 130 38 00 3F 00 0 71 6E 43 63 7C 08 0 0 0 39 0 VITC, PAL/SECAM 140 0 0 0 0 0 8F 6D 49 A4 85 08 0 0 0 4C 0 VITC, PAL/SECAM 150 0 0 0 0 0 8F 6D 49 A4 85 08 0 0 0 4C 0 VITC, NTSC 160 0 0 0 0 0 8F 6D 49 63 94 08 0 0 0 4C 0 VITC, NTSC 170 0 0 0 0 0 8F 6D 49 63 94 08 0 0 0 4C 0 VPS, PAL 180 AA AA FF FF BA CE 2B 8D A4 DA 0B 0 7 0 60 0 VPS, PAL 190 AA AA FF FF BA CE 2B 8D A4 DA 0B 0 7 0 60 0 Gemstar 2x Custom 1 1A0 99 99 FF FF 05 51 6E 05 63 18 13 80 00 00 60 00 Gemstar 2x Custom 1 1B0 Programmable Custom 2 1C0 Programmable Custom 2 1D0 Programmable Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 65 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.65 VDP Status Register Address 7 FIFO full error C6h 6 FIFO empty 5 TTX available 4 CC field 1 available 3 CC field 2 available 2 WSS available 1 VPS available 0 VITC available The VDP status register indicates whether data is available in either the FIFO or data registers, and status information about the FIFO. Reading data from the corresponding register does not clear the status flags automatically. These flags are only reset by writing a 1 to the respective bit. However, bit 6 is updated automatically. FIFO full error 0 = No FIFO full error 1 = FIFO was full during a write to FIFO. The FIFO full error flag is set when the current line of VBI data can not enter the FIFO. For example, if the FIFO has only ten bytes left and teletext is the current VBI line, the FIFO full error flag is set, but no data is written because the entire teletext line does not fit. However, if the next VBI line is closed caption requiring only two bytes of data plus the header, this goes into the FIFO, even if the full error flag is set. FIFO empty 0 = FIFO is not empty. 1 = FIFO is empty. TTX available 0 = Teletext data is not available. 1 = Teletext data is available. CC field 1 available 0 = Closed caption data from field 1 is not available. 1 = Closed caption data from field 1 is available. CC field 2 available 0 = Closed caption data from field 2 is not available. 1 = Closed caption data from field 2 is available. WSS available 0 = WSS data is not available. 1 = WSS data is available. VPS available 0 = VPS data is not available. 1 = VPS data is available. VITC available 0 = VITC data is not available. 1 = VITC data is available. 66 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.66 FIFO Word Count Register Address C7h 7 6 5 4 3 Number of words 2 1 0 1 0 This register provides the number of words in the FIFO. One word equals two bytes. 3.21.67 FIFO Interrupt Threshold Register Address Default C8h 80h 7 6 5 4 3 Number of words 2 This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this value (default 80h). This interrupt must be enabled at address C1h. One word equals two bytes. 3.21.68 FIFO Reset Register Address Default C9h 00h 7 6 5 4 3 2 1 0 Any data Writing any data to this register resets the FIFO and clears any data present in all VBI read registers. 3.21.69 Line Number Interrupt Register Address Default 7 Field 1 enable CAh 00h 6 Field 2 enable 5 4 3 2 1 0 Line number This register is programmed to trigger an interrupt when the video line number matches this value in bits 5:0. This interrupt must be enabled at address C1h. The value of 0 or 1 does not generate an interrupt. Field 1 enable 0 = Disabled (default) 1 = Enabled Field 2 enable 0 = Disabled (default) 1 = Enabled Line number default is 00h. Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 67 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.70 Pixel Alignment Registers Address Default CBh 4Eh Address CBh CCh CCh 00h 7 6 5 4 3 Switch pixel [7:0] 2 1 Reserved 0 Switch pixel [9:8] These registers form a 10-bit horizontal pixel position from the falling edge of sync, where the VDP controller initiates the program from one line standard to the next line standard; for example, the previous line of teletext to the next line of closed caption. This value must be set so that the switch occurs after the previous transaction has cleared the delay in the VDP, but early enough to allow the new values to be programmed before the current settings are required. 3.21.71 FIFO Output Control Register Address Default CDh 01h 7 6 5 4 Reserved 3 2 1 0 Host access enable This register is programmed to allow I2C access to the FIFO or to allow all VDP data to go out the video port as ancillary data. Host access enable 0 = Output FIFO data to the video output YOUT[7:0] as ancillary data 1 = Read FIFO data via I2C register B0h (default) 3.21.72 Full Field Enable Register Address Default 7 CFh 00h 6 5 4 Reserved 3 2 1 0 Full field enable This register enables the full field mode. In this mode, all lines outside the vertical blank area and all lines in the line mode registers programmed with FFh are sliced with the definition of register FCh. Values other than FFh in the line mode registers allow a different slice mode for that particular line. Full field enable 0 = Disable full field mode (default) 1 = Enable full field mode 68 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.73 Line Mode Registers Address Default Address D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB D0h 00h D1h–FBh FFh 7 6 DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB 5 4 3 Line 6 Field 1 Line 6 Field 2 Line 7 Field 1 Line 7 Field 2 Line 8 Field 1 Line 8 Field 2 Line 9 Field 1 Line 9 Field 2 Line 10 Field 1 Line 10 Field 2 Line 11 Field 1 Line 11 Field 2 Line Line Line Line Line Line Line Line Line Line Line Line Line Line Line Line Line Line Line Line Line Line Line Line Line Line Line Line Line Line Line Line 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 Field Field Field Field Field Field Field Field Field Field Field Field Field Field Field Field Field Field Field Field Field Field Field Field Field Field Field Field Field Field Field Field 2 1 0 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 These registers program the specific VBI standard at a specific line in the video field. Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 69 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com Bit 7 0 = Disable filtering of null bytes in closed caption modes 1 = Enable filtering of null bytes in closed caption modes (default) In teletext modes, bit 7 enables the data filter function for that particular line. If it is set to 0, the data filter passes all data on that line. Bit 6 0 = Send VBI data to registers only 1 = Send VBI data to FIFO and the registers. Teletext data only goes to FIFO (default). Bit 5 0 = Allow VBI data with errors in the FIFO 1 = Do not allow VBI data with errors in the FIFO (default) Bit 4 0 = Do not enable error detection and correction 1 = Enable error detection and correction (default) Bits [3:0] 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 = WST SECAM WST PAL B WST PAL C WST NTSC NABTS NTSC TTX NTSC-J CC PAL CC NTSC WSS/CGMS-A PAL WSS/CGMS-A NTSC VITC PAL VITC NTSC VPS PAL Gemstar 2x Custom 1 Custom 2 Active video (VDP off) (default) A value of FFh in the line mode registers is required for any line to be sliced as part of the full field mode. 3.21.74 Full Field Mode Register Address Default 7 FCh 7Fh 6 5 4 3 2 1 0 Full field mode This register programs the specific VBI standard for full field mode. It can be any VBI standard. Individual line settings take priority over the full field register. This allows each VBI line to be programmed independently but have the remaining lines in full field mode. The full field mode register has the same definitions as the line mode registers (default 7Fh). 70 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 4 Electrical Specifications Absolute Maximum Ratings (1) 4.1 over operating free-air temperature range (unless otherwise noted) Supply voltage range IO_DVDD to DGND –0.5 V to 4.5 V DVDD to DGND –0.5 V to 2.3 V PLL_AVDD to PLL_AGND –0.5 V to 2.3 V CH_AVDD to CH_AGND –0.5 V to 2.3 V Digital input voltage range, VI to DGND –0.5 V to 4.5 V Input voltage range, XTAL1 to PLL_GND –0.5 V to 2.3 V Analog input voltage range AI to CH_AGND –0.2 V to 2.0 V –0.5 V to 4.5 V Digital output voltage range, VO to DGND Commercial Operating free-air temperature, TA 0°C to 70°C –40°C to 85°C Industrial –65°C to 150°C Storage temperature range, Tstg (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not recommended. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 4.2 Recommended Operating Conditions MIN NOM MAX UNIT 3.6 V IO_DVDD Digital I/O supply voltage 1.65 1.8 3.3 DVDD Digital supply voltage 1.65 1.8 1.95 V PLL_AVDD Analog PLL supply voltage 1.65 1.8 1.95 V CH_AVDD Analog core supply voltage 1.65 1.8 1.95 V VI(P-P) Analog input voltage (ac-coupling necessary) 0.75 V VIH Digital input voltage high (1) VIL Digital input voltage low (1) VIH_XTAL XTAL input voltage high (1) XTAL input voltage low IOH High-level output current (1) IOL Low-level output current (1) 0.7 PLL_AVDD (1) SCLK high-level output current IOL_SCLK SCLK low-level output current (1) 4.3 Commercial Operating free-air temperature Industrial V 2 mA –2 mA 4 mA –4 mA 0 70 –40 85 °C Specified by design Reference Clock Specifications MIN f Frequency Δf Frequency tolerance (1) (1) V V 0.3 PLL_AVDD IOH_SCLK (1) V 0.3 IO_DVDD (1) VIL_XTAL TA 0 0.7 IO_DVDD NOM MAX 27 –50 UNIT MHz +50 ppm Specified by design Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 71 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 4.4 www.ti.com Electrical Characteristics Typical supply voltages: DVDD = 1.8 V, PLL_AVDD = 1.8 V, CH_AVDD = 1.8 V, IO_DVDD = 3.3 V, For minimum/maximum values: TA = 0°C to 70°C for commercial or TA = –40°C to 85°C for industrial, For typical values: TA = 25°C (unless otherwise noted) 4.5 DC Electrical Characteristics TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT IDD(IO_D) 3.3-V I/O digital supply current 100% color bar input 6.9 7.9 mA IDD(D) 1.8-V digital supply current 100% color bar input 30 33.5 mA IDD(PLL_A) 1.8-V analog PLL supply current 100% color bar input 5.7 7.9 mA IDD(CH_A) 1.8-V analog core supply current 100% color bar input 27.9 39.2 mA PTOT Total power dissipation, normal mode 100% color bar input 137 185 mW PDOWN Total power dissipation, power-down mode (2) 100% color bar input 1 mW (3) Ci Input capacitance VOH Output voltage high (3) By design IOH = 2 mA VOL Output voltage low (3) IOL = –2 mA VOH_SCLK SCLK output voltage high (3) IOH = 4 mA (3) 8 pF 0.8 IO_DVDD V 0.22 IO_DVDD V 0.8 IO_DVDD V IOL = –4 mA VOL_SCLK SCLK output voltage low 0.22 IO_DVDD V IIH High-level input current (4) VI = VIH ±20 µA IIL Low-level input current (4) VI = VIL ±20 µA (1) (2) (3) (4) Measured with 22-Ω series termination resistors and 10-pF load. Assured by device characterization Specified by design YOUT7 is a bidirectional terminal with an internal pulldown resistor. This terminal may sink more than the specified current when in RESET mode. 4.6 Analog Electrical Characteristics PARAMETER TEST CONDITIONS MIN Input impedance, analog video inputs (1) Zi TYP MAX 500 (1) UNIT kΩ Ci Input capacitance, analog video inputs Vi(pp) Input voltage range (2) ΔG Gain control maximum ΔG Gain control minimum DNL Absolute differential nonlinearity A/D only 0.5 1 LSB INL Absolute integral nonlinearity A/D only 1 2.5 LSB Fr Frequency response 6 MHz, Specified by design –0.9 dB SNR Signal-to-noise ratio 6 MHz, 1.0 VP-P 50 dB NS Noise spectrum 50% flat field 50 dB DP Differential phase Modulated ramp 0.5 ° Differential gain Modulated ramp 1.5 % DG (1) (2) 72 10 Ccoupling = 0.1 µF 0 pF 0.75 12 V dB 0 dB Specified by design The 0.75-V maximum applies to the sync-chrominance amplitude, not sync-white. The recommended termination resistors are 37.4 Ω, as seen in Section 6. Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 4.7 Clocks, Video Data, Sync Timing TEST CONDITIONS (1) PARAMETER Duty cycle, SCLK MIN TYP MAX 47 50 53 t1 SCLK high time ≥90% 18.5 t2 SCLK low time ≤10% 18.5 t3 SCLK fall time 90% to 10% t4 SCLK rise time 10% to 90% t5 Propagation delay time (1) UNIT % ns ns 3 5 ns 5 ns 8 ns Measured with 22-Ω series termination resistors and 10-pF load. t1 t2 SCLK t3 YOUT[7:0], AVID, VSYNC, HSYNC, FID/GLCO t4 VOH Valid Data Valid Data VOL t5 Figure 4-1. Clocks, Video Data, and Sync Timing Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 73 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com I2C Host Interface Timing (1) 4.8 NO. PARAMETER MIN TYP MAX UNIT µs t1 Bus free time between STOP and START 1.3 t2 Data Hold time t3 Data Setup time 100 ns t4 Setup time for a (repeated) START condition 0.6 µs t5 Setup time for a STOP condition 0.6 ns t6 Hold time (repeated) START condition 0.6 t7 Rise time SDA and SCL signal 250 0 µs 0.9 µs ns t8 Fall time SDA and SCL signal 250 ns Cb Capacitive load for each bus line 400 pF fI2C I2C clock frequency 400 kHz (1) Specified by design Stop SDA Start Stop Data t1 t4 t3 t2 t5 Change SCL Data t7 t6 t6 t8 Figure 4-2. I2C Host Interface Timing 4.9 Thermal Specifications PARAMETER PACKAGE θJA Junction-to-ambient thermal resistance, still air TQFP-32 (PBS) θJC Junction-to-case thermal resistance, still air TQFP-32 (PBS) TJ(MAX) Maximum junction temperature for reliable operation TQFP-32 (PBS) 74 Electrical Specifications BOARD MIN TYP MAX UNIT JEDEC Low-K 125.3 ºC/W JEDEC High-K 91.1 ºC/W 39.3 ºC/W 105 ºC Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 5 Example Register Settings The following example register settings are provided only as a reference. These settings, given the assumed input connector, video format, and output format, set up the TVP5151 decoder and provide video output. Example register settings for other features and the VBI data processor are not provided here. 5.1 5.1.1 Example 1 Assumptions Device: TVP5151 Input connector: Composite (AIP1A) Video format: NTSC-M, PAL (B, G, H, I), or SECAM NOTE NTSC-4.43, PAL-N, and PAL-M are masked from the autoswitch process by default. See the autoswitch mask register at address 04h. Output format: 8-bit ITU-R BT.656 with embedded syncs 5.1.2 Recommended Settings Recommended I2C writes: For this setup, only one write is required. All other registers are set up by default. I2C register address 03h = Miscellaneous controls register address I2C data 09h = Enables YCbCr output and the clock output NOTE HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high impedance by default. See the miscellaneous control register at address 03h. Example Register Settings Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 75 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 5.2 5.2.1 www.ti.com Example 2 Assumptions Device: TVP5151 Input connector: S-video (AIP1A (luminance), AIP1B (chrominance)) Video Format: NTSC (M, 4.43), PAL (B, G, H, I, M, N, Nc) or SECAM (B, D, G, K1, L) Output format: 8-bit 4:2:2 YCbCr with discrete sync outputs 5.2.2 Recommended Settings Recommended I2C writes: This setup requires additional writes to output the discrete sync 4:2:2 data outputs, the HSYNC, and the VSYNC, and to autoswitch between all video formats mentioned above. I2C register address 00h = Video input source selection #1 register I2C data 01h = Selects the S-Video input, AIP1A (luminance), and AIP1B (chrominance) I2C register address 03h = Miscellaneous controls register address I2C data 0Dh = Enables the YCbCr output data, HSYNC, VSYNC/PALI, AVID, and FID/GLCO I2C register address 04h = Autoswitch mask register I2C data C0h = Unmask NTSC-4.43, PAL-N, and PAL-M from the autoswitch process I2C register address 0Dh = Outputs and data rates select register I2C data 40h = Enables 8-bit 4:2:2 YCbCr with discrete sync output 76 Example Register Settings Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 6 Application Information 6.1 Application Example IO_DVDD C2 1 µF C1 1 µF 10 kW See Note I C3 1 µF C4 0.1 µF R1 CH1_IN 0.1 µF AAF PDN INTREQ/GPCL/VBLK AVID HSYNC AVDD 10 kW See Note H PDN INTREQ/GPCL/VBLK AVID HSYNC IO_DVDD AVDD R6 37.4 Ω TVP5151 VSYNC/PALI FID/GLCO SDA SCL DVDD DGND YOUT0 YOUT1 S1 2 R3 2.2 kW R4 2.2 kW 24 23 22 21 20 19 18 17 VSYNC/PALI FID/GLCO SDA SCL VSYNC/PALI FID/GLCO DVDD C7 0.1 µF 9 10 11 12 13 14 15 16 OSC_IN 1 C6 0.1 µF AIP1A AIP1B PLL_AGND PLL_AVDD XTAL1/OSC_IN XTAL2 AGND RESETB SCLK IO_DVDD YOUT7/I2CSEL YOUT6 YOUT5 YOUT4 YOUT3 YOUT2 C5 37.4 Ω OSC_IN 1 2 3 4 5 6 7 8 0.1 µF R5 AAF CH_AVDD CH_AGND REFM REFP PDN INTREQ/GPCL/VBLK AVID/CLK_IN HSYNC C11 R2 37.4 Ω CH2_IN 32 31 30 29 28 27 26 25 37.4 Ω Y1 SCLK 27.000 MHz ± 50 ppm SCLK RESETB IO_DVDD C8 CL1 R C9 R7 10 kW A. B. C. D. E. F. G. H. I. YOUT[7:0] IO_DVDD C10 0.1 µF CL2 2 Implies I C address is BAh. If B8h is to be used, connect pulldown resistor to digital ground. The use of INTREQ/GPCL/VBLK, AVID, HSYNC, and VSYNC/PALI is optional. When OSC_IN is connected through S1, remove the capacitors for the crystal. PDN needs to be high, if device has to be always operational. RESETB is operational only when PDN is high. This allows an active-low reset to the device. 100-kΩ resistor (R) in parallel with the crystal is recommended for most crystal types. Anti-aliasing filter (AAF) highly recommended for best video quality. System level ESD protection is not included in this application circuit, but it is highly recommended on the analog video inputs. An external 10-kΩ pulldown resistor is required when the INTREQ/GPCL/VBLK output (pin 27) is disabled (bit 5 of I2C register 03h is set to 0). An external 10-kΩ pullup resistor is required when the INTREQ/GPCL/VBLK output (pin 27) is enabled and configured as an active-low interrupt (bit 5 of I2C register 03h is set to 1, bit 1 of I2C register 0Fh is set to 0, and bit 0 of I2C register 1Eh is set to 0). Figure 6-1. Application Example Application Information Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 77 TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 7 Revision History Table 7-1. Revision History REVISION SLES241 COMMENTS Initial release Section 1.4, Related Products added Section 1.5, Trademarks modified Section 3.16, Figure 3-8 changed to depict various clocking options. Changed crystal parallel resistor recommendation. SLES241A Section 3.21.10, Luminance Brightness description modified Section 3.21.11, Chrominance Saturation description modified Section 3.21.50, Status Register #3 description modified Section 6.1, Changed recommendation for resistor in parallel with the crystal Minor editorial changes throughout Section 3.3, Figure 3-2, Chroma trap filter characteristics for NTSC added. Section 3.3, Figure 3-3, Chroma trap filter characteristics for PAL added. SLES241B Section 3.4, Figure 3-4, Color low-pass filter characteristics added. Section 3.8, Table 3-1, Modified name for register 1100b. Section 3.20, Table 3-11, Added I2C indirect registers at address 21h-24h. Section 4.9, Added Power Dissipation Ratings. AEC-Q100 qualification added. Section 3.13, Updated description. Section 3.21.29, Added Indirect Register Data SLES241C Section 3.21.30, Added Indirect Register Address Section 3.21.31, Added Indirect Register Read/Write Strobe Section 3.21.38, Added Patch Write Address Section 3.21.39, Added Patch Code Execute Section 3.21.53, Added Patch Read Address SLES241D Removed AEC-Q100 qualification. Table 2-1, Modified description for terminal 27. Table 3-11, Modified registers 82h and 83h. Section 3.21.4, Modified description for bits 7:5 of I2C register 03h. SLES241E Section 3.21.15, Removed support for 1x output clock frequency (bit 0 of register 0Fh). Section 3.21.42, Modified the register description for register 82h. Section 3.21.43, Modified the register description for register 83h. Figure 6-1, Added note concerning ESD protection. Added pulldown and pullup resistors to pin 27 output. 78 Revision History Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TVP5151IPBS ACTIVE TQFP PBS 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TVP5151IPBSR ACTIVE TQFP PBS 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TVP5151IZQC ACTIVE BGA MICROSTAR JUNIOR ZQC 48 360 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR TVP5151IZQCR ACTIVE BGA MICROSTAR JUNIOR ZQC 48 2500 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR TVP5151PBS ACTIVE TQFP PBS 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TVP5151PBSR ACTIVE TQFP PBS 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TVP5151ZQC ACTIVE BGA MICROSTAR JUNIOR ZQC 48 360 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR TVP5151ZQCR ACTIVE BGA MICROSTAR JUNIOR ZQC 48 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com (3) 18-Jul-2012 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TVP5151IPBSR TQFP PBS 32 1000 330.0 16.4 7.2 7.2 1.5 12.0 16.0 Q2 TVP5151PBSR TQFP PBS 32 1000 330.0 16.4 7.2 7.2 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TVP5151IPBSR TQFP PBS 32 1000 367.0 367.0 38.0 TVP5151PBSR TQFP PBS 32 1000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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