ETC GMS81504

HYUNDAI MicroElectronics
GMS81504
GMS81504
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
OVERVIEW
Description
The GMS81504 is a high-performance CMOS 8-bit microcontroller with 4K bytes of ROM. The device is one
of GMS800 family. The HYUNDAI GMS81504 is a powerful microcontroller which provides a highly flexible
and cost effective solution to many embedded control applications. The GMS81504 provides the following
standard features: 4K bytes of ROM, 128 bytes of RAM, 23 I/O lines(21 lines for 28SOP), 16-bit or 8-bit
timer/counter, a precision analog to digital converter, on-chip oscillator and clock circuitry. In addition, the
GMS81504 supports power saving modes to reduce power consumption. The Stop Mode saves the RAM contents
but freezes the oscillator disabling all other chip functions until the next hardware reset or external interrupt.
ROM size
RAM size
4K bytes
128 bytes
4K bytes
(OTP)
128 bytes
Package
Device name
30SDIP
GMS81504 K
28SOP
GMS81504 D
30SDIP
GMS81504T K
Features
4K On-chip Program Memory
One Programmable Clock Out port
128 Bytes of On-Chip Data RAM
One Buzzer Driving port
Instruction execution time: 0.5us at 8MHz
23 Programmable I/O Lines
2.7V to 5.5V Wide Operating Range
Seven Interrupt Sources
1~8 MHz Operating frequency
All LED Direct Drive Output Ports
Basic Interval Timer
4-Channel 8-Bit On-Chip Analog to Digital
Converter
Two 8-Bit Timer/ Counters (can be used
as one 16-bit)
Power Down Mode (STOP Mode)
Two external interrupt ports
Development Tools
The GMS800 family is supported by a full-featured
macro assembler, an in-circuit emulators CHOICEJr.TM, socket adapters for OTP device.
The availability of OTP devices are especially useful
for customers expecting frequent code changes and
updates. The OTP devices, packaged in plastic packages permit the user to program them once. In addition
to the program memory, the configuration fuses must
be programmed.
In-Circuit
Emulators
CHOICE-Jr.TM
OTP devices
GMS81504T K (30 SDIP)
Socket
Adapters for
OTP Devices
OA815A-30SD (30 SDIP)
Assembler
HME Macro Assembler
1
GMS81504
HYUNDAI MicroElectronics
BLOCK DIAGRAM
RAM
128 x 8
PORT 0
8
I/O
R00~R07
BIT*
BUZZER
PORT 4
8
I/O
R40~R47
TIMER 0
CPU
TIMER 1
ADC
EXT INT
ROM
4K x 8
PORT 5
R55/BUZ
R56**
R57**
PORT 6
R64
R65
R66
R67
* BIT: Basic Interval Timer
** The R56, R57 port are not served on 28SOP package.
Figure 1. Block Diagram
2
HYUNDAI MicroElectronics
GMS81504
PIN ASSIGNMENT
30 SDIP
28 SOP
Figure 2. Pin Connections
3
GMS81504
HYUNDAI MicroElectronics
PACKAGES
Unit: INCH
30 SDIP
28 SOP
0.299 0.419
0.292 0.398
0.713
0.697
0.106
0.093
0.020
0.013
4
0.050 BSC
0.0118
0.004
0°~8°
0.042
0.016
0.0125
0.008
HYUNDAI MicroElectronics
PIN DESCRIPTIONS
VDD: Supply voltage.
VSS: Circuit Ground.
TEST: For test purposes only. Connect it to VDD.
RESET: Reset the MCU.
XIN: Input to the inverting oscillator amplifier and
input to the internal clock operating circuit.
XOUT: Output from the inverting oscillator amplifier.
R00~R07: R0 is an 8-bit, CMOS, bidirectional I/O
port. As an output port each pin can sink several LS
TTL inputs. R0 pins that have 1 or 0 written to their
Port Direction Mode Register, can be used as outputs
or inputs.
R40~R47: R4 is an 8-bit, CMOS, bidirectional I/O
port. As an output port each pin can sink several LS
TTL inputs. R4 pins that have 1 or 0 written to their
Port Direction Mode Register, can be used as outputs
or inputs.
In addition, Port R40, R41, R44, R46 serve the functions of the various following special features.
Port Pin
Alternate Function
R40
INT0 (External Interrupt 0)
R41
INT1 (External Interrupt 1)
R44/EC0
R46
GMS81504
R55, R56, R57: R5 is a 3-bit, CMOS, bidirectional I/O
port. As an output port each pin can sink several LS
TTL inputs. R5 pins that have 1 or 0 written to their
Port Direction Mode Register, can be used as outputs
or inputs. R56 and R57 differs in having internal
pull-ups.
Port R55 serves the functions of special features.
Port Pin
Alternate Function
R55
BUZ (Square wave output for Buzzer
driving)
R64~R67: R6 is an 4-bit, CMOS, bidirectional I/O
port. R64~R67 are bidirectional I/O port. As an output
port each pin can sink several LS TTL inputs.
R64~R67 pins that have 1 or 0 written to their Port
Direction Mode Register, can be used as outputs or
inputs.
R6 serves the analog to digital converter functions of
following.
Port Pin
R64
R65
R66
R67
Alternate Function
AN4 (ADC input 4)
AN5 (ADC input 5)
AN6 (ADC input 6)
AN7 (ADC input 7)
AVDD: Supply voltage to the ladder resistor of ADC
circuit. To enhance the resolution of analog to digital
converter, use independent power source as well as
possible, other than digital power source.
EC0 (External Count Input to
Timer/Counter 0)
T1O (Timer 1 Clock-Out)
5
GMS81504
Port Pin
HYUNDAI MicroElectronics
Descriptions
I/O
Primary Functions
Secondary Functions
Pull-up/
Pull-down
RESET
STOP
Mode
-
-
-
VDD
-
Power supply to MCU
-
VSS
-
Ground
-
-
-
-
AVDD
-
Power supply for ADC
-
-
-
-
TEST
I
Test mode
-
-
-
-
RESET
I
Reset the MCU
-
Pull-up
Low
Last state
XIN
I
Oscillation input
-
-
Oscillation
Low
XOUT
Oscillation output
-
-
Oscillation
High
R00~R07
I/O
O
General I/O
-
-
Input 3)
Last state
R40/INT0
R41/INT1
R42
R43
R44/EC0
R45
R46/T1O
R47
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General I/O
"
"
"
"
"
"
"
External interrupt 0
External interrupt 1
External count input 0
Timer 1 output
-
Input 3)
Last state
R55/BUZ
R56 1)
R57 1)
I/O
I/O
I/O
General I/O
"
"
Buzzer driving output
-
Input 3)
Last state
R64/AN4
R65/AN5
R66/AN6
R67/AN7
I/O
I/O
I/O
I/O
General I/O
"
"
"
Analog input 4
Analog input 5
Analog input 6
Analog input 7
Input 3)
Last state
-
Pull-up 2)
Pull-up 2)
-
NOTES:
1) R56 and R57 are not physically served on 28 pin SOP package.
2) When input mode is selected, pull-up is activated. In output mode, pull-up is de-activated.
3) During MCU reset, status of R56,R57 are weak high (Typ. impedance 50~100KΩ). Other pin impedance is very high(High-Z).
6
HYUNDAI MicroElectronics
GMS81504
PORT STRUCTURES
R00~R07, R47
VDD
DATA REG.
PROTECT DIODE
DATA BUS
DIRECTION REG.
DATA BUS
PROTECT DIODE
VSS
MUX
DATA BUS
Rd.
R40/INT0, R41/INT1, R44/EC0
PMR4
DATA REG.
DATA BUS
DIRECTION REG.
DATA BUS
DATA BUS
MUX
Rd.
ALTERNATE FUNCTION
EX) INT0
R46/T1O, R55/BUZ
SELECTION (PMR)
ALTERNATE FUNCTION
EX) T1O
MUX
DATA REG.
DATA BUS
DATA BUS
DIRECTION REG.
DATA BUS
MUX
Rd.
7
GMS81504
HYUNDAI MicroElectronics
R42, R43, R45
VDD
DATA REG.
PROTECT DIODE
DATA BUS
DIRECTION REG.
DATA BUS
PROTECT DIODE
VSS
MUX
DATA BUS
Rd.
R56, R57
PULL-UP RESISTOR
DATA REG.
DATA BUS
DIRECTION REG.
DATA BUS
MUX
DATA BUS
INPUT MODE: PULL-UP RESISTOR IS ACTIVATED.
OUTPUT MODE: PULL-UP RESISTOR IS DE-ACTIVATED.
Rd.
R64/AN4, R65/AN5, R66/AN6, R67/AN7
DATA REG.
DATA BUS
DIRECTION REG.
DATA BUS
DATA BUS
MUX
Rd.
Rd.
TO A/D Converter
Ch. Select
8
0: Output
1: Reset, Input, AD ch. select
HYUNDAI MicroElectronics
GMS81504
RESET
TEST
OTP: No P-Ch diode
Pull-up Resister
XIN, XOUT
VDD
VDD
XIN
VDD
XOUT
STOP
9
GMS81504
HYUNDAI MicroElectronics
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . -0.3 to +6.0 V
Storage Temperature . . . . . . . . . . . . -40 to +125 °C
Voltage on any pin with
respect to Ground (VSS) . . . . . . -0.3 to VDD+0.3 V
Maximum current out of VSS pin . . . . . . . . . 150 mA
Maximum current into VDD pin . . . . . . . . . 100 mA
Maximum output current sunk by (IOL per I/O Pin)
R00~R07, R42, R43, R56, R57 . . . . . . . . 30 mA
R40, R41, R44~R47, R55, R64~67 . . . . . . 20 mA
Maximum output current sourced by (IOH per I/O Pin)
R00~R07, R42, R43, R56, R57 . . . . . . . . 24 mA
R40, R41, R44~R47, R55, R64~67 . . . . . . 18 mA
Maximum current (Σ IOL) . . . . . . . . . . . . 120 mA
Maximum current (Σ IOH) . . . . . . . . . . . . 100 mA
Notice:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these of any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
Specifications
Min.
Max.
Unit
Supply Voltage
VDD
fXIN = 8 MHz
fXIN = 4 MHz
4.5
2.7
5.5
5.5
V
Operating Frequency
fXIN
VDD = 4.5~5.5V
VDD = 2.7~5.5V
1.0
1.0
8.0
4.2
MHz
-20
80
°C
Operating Temperature
10
TOPR
HYUNDAI MicroElectronics
GMS81504
DC Characteristics ( 5V )
(VDD = 5.0V± 10%, VSS = 0V, TA = -20 ~ 80 °C, fXIN = 8 MHz)
Parameter
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Current
Input Pull-up Current
Power Current
Hysteresis
Pin
Symbol
Specifications
Test Condition
Unit
Min.
Typ.*
Max.
XIN
VIH1
-
0.9VDD
-
VDD
V
RESET, R0, R4,
R5, R6
V IH2
-
0.8VDD
-
VDD
V
XIN
VIL1
-
0
-
0.1VDD
V
RESET, R0, R4,
R5, R6
VIL2
-
0
-
0.2VDD
V
R0, R4, R5, R6
VOH
VDD = 5V
IOH = -2mA
-
V
R40, R41,
R44~R47, R55, R6
VOL1
VDD = 5V
IOL = 5mA
-
0.3
1.0
V
R0, R42, R43, R56,
R57
VOL2
VDD = 5V
IOL = 10mA
-
0.6
1.0
V
RESET, R0, R4,
R5, R6
V DD-1.0 VDD-0.2
IIH
VI = VDD
-5.0
-
5.0
uA
IIL
VI = 0V
-5.0
-
5.0
uA
uA
RESET
IP1
VDD = 5V
-180
-120
-30
R56, R57
IP2
VDD = 5V
-90
-60
-15
uA
Operating mode
IDD
fXIN=8MHz
-
5
40
mA
STOP mode
ISTOP
VDD = 5V
-
2
30
uA
RESET,
R40~R45
V T+
~VT-
VDD = 5V
0.5
0.8
-
V
* : Data in "Typ" column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
A/D Converter Characteristics ( 5V )
(VDD = 5.0V± 10%, VAIN = 5.0V, VSS = 0V, TA = 25 °C)
Parameter
Specifications
Symbol
Min.
Unit
Typ.*
Max.
Analog Input Range
VAIN
VSS
-
AVDD
V
Overall Accuracy
ACC
-
±2.0
±3.0
LSB
Conversion Time
TCONV
-
-
40
uS
Analog power supply Input
Range
VAVDD
4.5
5.0
5.5
V
* : Data in "Typ" column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
11
GMS81504
HYUNDAI MicroElectronics
DC Characteristics ( 3V )
(VDD = 3.0V± 10%, VSS = 0V, TA = -20 ~ 80 °C, fXIN = 4 MHz)
Parameter
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Pin
Unit
Min.
Typ.*
Max.
VIH1
-
0.9VDD
-
VDD
V
RESET, R0, R4,
R5, R6
V IH2
-
0.8VDD
-
VDD
V
XIN
VIL1
-
0
-
0.1VDD
V
RESET, R0, R4,
R5, R6
VIL2
-
0
-
0.2VDD
V
R0, R4, R5, R6
VOH
VDD = 3V
IOH = -2mA
-
V
R40, R41,
R44~R47, R55, R6
VOL1
VDD = 3V
IOL =2mA
0.3
1.0
V
R0, R42, R43, R56,
R57
VOL2
VDD = 3V
IOL = 5mA
0.4
1.0
V
VDD -1.0 VDD-0.4
-
IIH
VI = VDD
-3.0
-
3.0
uA
IIL
VI = 0V
-3.0
-
3.0
uA
RESET
IP1
VDD = 3V
-15
-30
-60
uA
R56, R57
IP2
VDD = 3V
-7.5
-15
-30
uA
IDD
fXIN=4MHz
-
1
5
mA
RESET, R0, R4,
R5, R6
Input Pull-up
Current
Operating mode
Hysteresis
Specifications
Test Condition
XIN
Input Leakage
Current
Power Current
Symbol
STOP mode
ISTOP
VDD = 3V
-
1
10
uA
RESET,
R40~R45
V T+
~VT-
VDD = 3V
0.3
0.6
-
V
* : Data in "Typ" column is at 3 V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
**: Power Fail Detection function is not available.
A/D Converter Characteristics ( 3V )
(VDD = 3.0V± 10%, VAIN = 3.0V, VSS = 0V, TA = 25 °C)
Parameter
Specifications
Symbol
Min.
Unit
Typ.*
Max.
Analog Input Range
V AIN
VSS
-
AVDD
V
Overall Accuracy
ACC
-
±1.5
±2.5
LSB
Conversion Time
TCONV
-
-
40
uS
Analog power supply Input
Range
VAVDD
2.7
3.0
3.3
V
* : Data in "Typ" column is at 3 V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
12
HYUNDAI MicroElectronics
GMS81504
AC Characteristics
(VDD = 2.7~5.5V, VSS = 0V, TA = -20 ~ 80 °C)
Parameter
Main clock frequency
Pin
Specifications
Symbol
XIN
Unit
Min.
Typ.
Max.
fXIN
1
-
8
MHz
Oscillation stabilization Time
XIN, XOUT
tST
20
-
-
ms
External Clock Pulse Width
XIN
tCPW
80
-
-
ns
External Clock Transition Time
XIN
tRCP, tFCP
-
-
20
ns
Interrupt Pulse Width
INT0, INT1
tIW
2
-
-
tSYS
RESET Input Low Width
RESET
tRST
8
-
-
tSYS
Event Counter Input Pulse
Width
EC0
tECW
2
-
-
tSYS
Event Counter Transition Time
EC0
tREC, tFEC
-
-
20
ns
Timing Chart
tCPW
1 / fOSC
tCPW
0.9VDD
0.1VDD
XIN
tRCP
tFCP
tIW
INT0, INT1
tIW
0.8VDD
0.2VDD
tRST
RESET
0.2VDD
tECW
EC0
tECW
0.8VDD
0.2VDD
tREC
tFEC
13
GMS81504
HYUNDAI MicroElectronics
TYPICAL CHARACTERISTICS
These parameters are for design guidance only and are not tested.
IDD
(mA)
IDD - VDD
ISTOP
(uA)
TA=25°C
8
ISTOP
TA=25°C
8
fXIN = 8MHz
6
6
4
4
fXIN = 4MHz
2
2
0
2
3
4
5
VDD
(V)
0
2
3
4
5
VDD
(V)
2
3
4
VOL
(V)
VDD=5V
IOL
(mA)
24
IOL - VOL
IOL
(mA)
VDD=5.0V
TA=25°C
20
18
15
12
10
6
5
0
1
2
3
4
VOL
(V)
0
-24
IOH - VOH
IOH
(mA)
VDD=5.0V
TA=25°C
-20
-18
-15
-12
-10
-6
-5
0
1
2
3
4 VDD-VOH
(V)
R00~R07, R42, R43, R56, R57
14
VDD=5.0V
TA=25°C
1
R40, R41, R44~R47, R55, R64~67
R00~R07, R42, R43, R56, R57
IOH
(mA)
IOL - VOL
0
IOH - VOH
VDD=5.0V
TA=25°C
1
2
3
4 VDD-VOH
(V)
R40, R41, R44~R47, R55, R64~67
HYUNDAI MicroElectronics
GMS81504
VDD=3.0V
IOL
(mA)
20
IOL - VOL
IOL
(mA)
VDD=3.0V
TA=25°C
8
15
6
10
4
5
2
0
0.5
1.0
1.5
2.0
0
2.5 (V) VOL
-8
IOH - VOH
IOH
(mA)
VDD=3.0V
TA=25°C
-8
-6
-6
-4
-4
-2
-2
0
0.5
1.0
1.5
2.0
2.5 (V) VDD ---- VOH
R00~R07, R42, R43, R56, R57
VDD=3.0V
TA=25°C
0.5
1.0
1.5
2.0
2.5 (V)
VOL
R40, R41, R44~R47, R55, R64~67
R00~R07, R42, R43, R56, R57
IOH
(mA)
IOL - VOL
0
IOH - VOH
VDD=3.0V
TA=25°C
0.5
1.0
1.5
2.0
2.5 (V) VDD ---- VOH
R40, R41, R44~R47, R55, R64~67
15
GMS81504
HYUNDAI MicroElectronics
MEMORY ORGANIZATION
The GMS81504 has separate address spaces for Program and Data Memory. Program memory can only be
read, not written to. It can be up to 4K bytes of Program
Memory. Data memory can be read and written to up
to 128 bytes including the stack area.
Registers
This device has six registers that are the Program
Counter (PC), a Accumulator (A), two Index registers
(X,Y), the Stack Pointer (SP) and the Program Status
Word (PSW). The Program Counter consists of 16-bit
register.
A
ACCUMULATOR
X
X REGISTER
Y
Y REGISTER
The index registers also have increment, decrement,
compare and data transfer functions and they can be
used as simple accumulators.
Stack Pointer: The stack pointer is an 8-bit register
used for occurrence interrupts and calling out subroutines. The stack can be located at any position within
00H to 7FH of the internal data memory.
Caution:
The stack pointer must be initialized by software
because its value is undefined after reset.
Ex) LDX
#07FH
TXSP
; SP ← 7FH
Stack Address (00H~7FH)
15
8 7
0
0
SP
Hardware fixed.
SP
PCH
STACK POINTER
PCL
PROGRAM COUNTER
PSW
PROGRAM STATUS
WORD
Figure 3. Configuration of Registers
Accumulator: The accumulator is the 8-bit general
purpose register, used for data operation such as transfer, temporary saving and conditional judgment, etc.
The accumulator can be used as a 16-bit register with
Y register as shown below.
Y
Y
A
A
Figure 5. Stack Pointer
Caution:
To prevent overrapped between user RAM an system stack area, user have to consider using RAM.
Reset Routine Example:
RESET:
CLR_LP:
ORG
LDX
LDA
STA
CMPX
BNE
LDX
TXSP
:
0F000H
#0
#0
{X}+
#80H
CLR_LP
#07FH
;RAM CLEAR
;INITIALIZE SP.
Figure 4. Configuration of YA 16-bit register
Program Counter: The program counter is a 16-bit
wide which consists of two 8-bit registers, PCH, PCL.
This counter indicates the address of the next instruction to be executed. In reset state, the program counter
has reset vector address (PCH: FFH, PCL: FEH). .
X register, Y register: In the addressing modes which
use these index registers, the register contents are
added to the specified address and this becomes the
actual address. These modes are extremely effective
for referencing subroutine tables and memory tables.
Program Status Word : The Program Status Word
(PSW) contains several status bits that reflect the current state of the CPU. The PSW shown in Figure 6. It
contains the Negative flag, the Overflow flag, the
Direct page flag, the Break flag, the Half Carry (for
BCD operations), the Interrupt enable flag, the Zero
TWO 8-BIT REGISTERS
16
ONE "YA" 16-BIT REGISTER
HYUNDAI MicroElectronics
GMS81504
MSB
PSW
N
LSB
V
G
B
NEGATIVE FLAG
OVERFLOW FLAG
G FLAG TO SELECT DIRECT PAGE
(NOT AVAILABLE ON GMS81504)
BRK FLAG
H
I
Z
C
RESET VALUE: 00H
CARRY FLAG RECEIVES
CARRY OUT
ZERO FLAG
INTERRUPT ENABLE
FLAG
HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERANDS
Figure 6. PSW (Program Status Word) Register
flag and the Carry bit.
vector address.
[Carry flag C]
This flag stores any carry or borrow from the ALU of
CPU after an arithmetic operation and is also changed
by the Shift instruction or rotate instruction.
[Direct page flag G]
This flag is not available on GMS81504 because this
flag is usable over 256 bytes RAM other than the
GMS81504, assign direct page for direct addressing
mode. In the direct addressing mode, addressing area
is within zero page 00H to FFH when this flag is "0".
If it is set to "1", addressing area is 100H to 1FFH.
It is set by SETG instruction, and cleared by CLRG.
[Zero flag Z]
This flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other
result.
[Interrupt disable flag I] This flag enables/disables all
interrupts except interrupt caused by Reset or software
BRK instruction. All interrupts are disabled when
cleared to "0". This flag immediately becomes "0"
when an interrupt is served. It is set by the EI instruction, cleared by the DI instruction.
[Half carry flag H]
After operation, set when there is a carry from bit 3 of
ALU or there is not a borrow from bit 4 of ALU. This
bit can not be set or cleared except CLRV instruction,
clearing with Overflow flag (V).
[Break flag B]
This flag set by software BRK instruction to distinguish BRK from TCALL instruction which as the same
[Overflow flag V]
This flag is set to "1" when an overflow occurs in the
result of an arithmetic operation involving signs. An
overflow occurs when the result of an addition or
subtraction exceeds +127(7FH) or -128(80H).
The CLRV instruction clears the overflow flag. There
is no set instruction. When the BIT instruction is
executed, for other than the above, bit 6 of memory is
copy to this flag.
[Negative flag N]
This flag is set to match the sign bit (bit 7) status of the
result of a data or arithmetic operation. When the BIT
instruction is executed, bit 7 of memory is copy to this
flag.
17
GMS81504
HYUNDAI MicroElectronics
1) INTERRUPT
2) RETI
SP ← SP + 1
M(SP) ← (PCH)
SP ← SP - 1
(PSW) ← M(SP)
SP ← SP - 1
M(SP) ← (PCL)
SP ← SP + 1
M(SP) ← (PCL)
SP ← SP - 1
(PCL) ← M(SP)
SP ← SP - 1
M(SP) ← (PSW)
SP ← SP + 1
SP ← SP - 1
(PCH) ← M(SP)
4) RET
5) PUSH A (X,Y,PSW)
6) POP A (X,Y,PSW)
SP ← SP + 1
M(SP) ← ACC.
SP ← SP + 1
(PCL) ← M(SP)
SP ← SP - 1
M(SP) ← (PCH)
SP ← SP + 1
(PCH) ← M(SP)
Figure 7. Stack Operation
18
3) CALL
M(SP) ← (PCH)
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Program Memory
Address
A 16-bit program counter is capable of addressing up
to 64K bytes, but this devices have 4K bytes (8K for
GMS81608) program memory space only the physically implemented. Accessing a location above FFFFH
will cause a wrap-around to 0000H.
Figure 8, shows a map of the upper part of the Program
Memory. After reset, the CPU begins execution from
reset vector which is stored in address FFFEH, FFFFH.
As shown in Figure 8, each area is assigned a fixed
location in Program Memory. Program Memory area
contains the user program, Page Call (PCALL) area
contains subroutine program, to reduce program byte
length because of using by 2 bytes PCALL instead of
3 bytes CALL instruction. If it is frequently called,
more useful to save program byte length.
F000H
PROGRAM
MEMORY
FEFFH
FF00H
FFBFH
FFC0H
GMS81504
PCALL
AREA
TCALL
AREA
FFDFH
FFE0H INTERRUPT
VECTOR
AREA
FFFFH
Figure 8. Program Memory
Table Call (TCALL) causes the CPU to jump to each
TCALL address, where it commences execution of the
service routine. The Table Call service locations are
spaced at 2-byte interval : FFC0H for TCALL15,
FFC2H for TCALL14, etc.
FFC0H
FFC2H
FFC4H
FFC6H
FFC8H
FFCAH
FFCCH
FFCEH
FFD0H
FFD2H
FFD4H
FFD6H
FFD8H
FFDAH
FFDCH
FFDEH
TCALL Name
TCALL15
TCALL14
TCALL13
TCALL12
TCALL11
TCALL10
TCALL9
TCALL8
TCALL7
TCALL6
TCALL5
TCALL4
TCALL3
TCALL2
TCALL1
TCALL0/ BRK1)
1) The BRK software interrupt is using same address with
TCALL0.
The interrupt causes the CPU to jump to specific
location, where it commences execution of the service
routine. The External interrupt 0, for example, is assigned to location FFFAH. The interrupt service locations are spaced at 2-byte interval : FFF8H for External
Interrupt 1, FFFAH for External Interrupt 0, etc.
Any area from FF00H to FFFFH, if it not going to be
used, its service location is available as general purpose Program Memory.
Address
FFE0H
FFE2H
FFE4H
FFE6H
FFE8H
FFEAH
FFECH
FFEEH
FFF0H
FFF2H
FFF4H
FFF6H
FFF8H
FFFAH
FFFCH
FFFEH
Vector Name
Basic Interval Timer
Analog to Digital Converter
Timer/ Counter 1
Timer/ Counter 0
External Interrupt 1
External Interrupt 0
RESET
19
GMS81504
HYUNDAI MicroElectronics
Data Memory
Figure 9 shows the internal Data Memory space available. Data Memory are divided into three groups, a
user RAM, control registers and Stack.
Caution:
Write only registers can not be accessed by bit
manipulation instruction.
Address
Symbol
R/W
00H
MSB
DATA
MEMORY
(RAM)
128 BYTES
(INCLUDE STACK
AREA)
7FH
80H
NOT USED
BFH
C0H
FFH
CONTROL
REGISTERS
Figure 9. Data Memory
The stack pointer should be initialized within 00H to
7FH by software because of implemented area of
internal data memory.
The control registers are used by the CPU and Peripheral functions for controlling the desired operation of
the device.
Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog
to digital converters, I/O ports. The control registers
are in address C0H to FFH.
Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses
will in general return random data, and write accesses
will have an indeterminate effect.
More detail informations of each register are explained
in each peripheral sections.
C0H
C1H
C8H
C9H
CAH
CBH
CCH
CDH
D0H
D1H
D3H 2)
D3H 2)
E2H
E4H
E5H
E8H
E9H
ECH
F4H
F5H
F6H
F7H
F8H
R0
R0DD
R4
R4DD
R5
R5DD
R6
R6DD
PMR4
PMR5
BITR
CKCTLR
TM0
+ Note 3
+ Note 3
ADCM
ADR
BUR
IENL
IRQL
IENH
IRQH
IEDS
R/W
W 1)
R/W
W 1)
R/W
W 1)
R/W
W 1)
W 1)
W 1)
R
W 1)
R/W
R/W
R/W
R/W 4)
R
W 1)
R/W
R/W
R/W
R/W
W 1)
LSB
X
00000000
X
00000000
X
000----X
0000----0-0--00
--0----00000000
---10111
00000000
X
X
--000001
X
X
0-0----0-0----00--00-00--00-00000000
Legend - = Unimplemented locations.
X= Undefined value.
NOTES:
1) The all write only registers can not be accessed by bit
manipulation instruction.
2) The register BITR and CKCTLR are located at same address.
Address D3H is read as BITR, as written to CKCTLR.
3) Several names are given at same address. Refer to below
table.
When read
Address
E4H
E5H
When write
Timer mode
Capture Mode
T0
T1
CDR0
CDR1
4) Only bit 0 of ADCM can be read.
20
Power-on
Reset Value
TDR0
TDR1
HYUNDAI MicroElectronics
GMS81504
Control Registers for the GMS81504
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
EC0S
-
-
INT1S
INT0S
BUZS
-
-
-
-
-
-
ENPCK
BTCL
BTS2
BTS1
BTS0
T1SL1
T1SL0
T0ST
T0CN
T0SL1
T0SL0
C0H
R0
R0 port data register
C1H
R0DD
R0 port direction register
C8H
R4
R4 port data register
C9H
R4DD
R4 port direction register
CAH
R5
R5 port data register
CBH
R5DD
R5 port direction register
CCH
R6
R6 port data register
CDH
R6DD
R6 port direction register
D0H
PMR4
-
T1S
D1H
PMR5
-
-
D3H1)
BITR
D3H1)
CKCTLR
-
-
E2H
TM0
CAP0
T1ST
E4H
T0/ TDR0/ CDR0
Timer 0 register/ Timer data register 0/ Capture data register 0
E5H
T1/ TDR1/ CDR1
Timer 1 register/ Timer data register 1/ Capture data register 1
E8H
ADCM
E9H
ADR
ECH
BUR
BUCK1
BUCK0
F4H
IENL
AE
-
F5H
IRQL
AIF
-
F6H
IENH
INT0E
F7H
IRQH
F8H
IEDS
Basic Interval Timer data register
-
-
ADEN
ADS2
ADS1
ADS0
ADST
ADSF
BU5
BU4
BU3
BU2
BU1
BU0
BITE
-
-
-
-
-
BITIF
-
-
-
-
-
INT1E
-
-
T0E
T1E
-
-
INT0IF
INT1IF
-
-
T0IF
T1IF
-
-
-
-
-
-
IED1H
IED1L
IED0H
IED0L
ADC result data register
Legend - = Unimplemented locations.
NOTES:
1) The register BITR and CKCTLR are located at same address. Address D3H is read as BITR, written to CKCTLR.
21
GMS81504
HYUNDAI MicroElectronics
I/O PORTS
The GMS81504/08 have five ports, R0, R1, R4, R5,
R6. These ports pins may be multiplexed with an
alternate function for the peripheral features on the
device. In general, when a initial reset state, all ports
are used as a general purpose input port.
All pins have data direction registers which can configure these pins as output or input.
A "1" in the port direction register configures the
corresponding port pin as output. Conversely, write
"0" to the corresponding bit to specify as an input pin.
For example, to use the even numbered bit of R1 as
output ports and the odd numbered bits as input ports,
write "55H" to address C1H (R0 direction register)
during initial setting as shown in Figure 10.
WRITE "55H" TO PORT R0 DIRECTION REGISTER
0 1 0 1 0 1 0 1
C0H
C1H
:
C8H
C9H
R0 DATA
R0 DIRECTION
:
R4 DATA
R4 DIRECTION
7 6 5
4 3 2 1
0 BIT
R4 and R4DD registers: R4 is an 8-bit bidirectional
I/O port (address C8H). Each pin is individually configurable as input and output through the R4DD register (address C9H).
In addition, Port R4 is multiplexed with various special
features. The control register PMR4 (address D0H)
controls to select alternate function. After reset, this
value is "0", port may be used as general I/O ports. To
select alternate function such as External interrupt or
External counter or Timer clock out, write "1" to the
corresponding bit of PMR4.
Port Pin
Alternate Function
R40
R41
INT0 (External Interrupt 0)
INT1 (External Interrupt 1)
R44
EC0 (External Count Input to Timer/
Counter 0)
R46
T1O (Timer 1 Clock-Out)
Regardless of the direction register R4DD, PMR4 is
selected to use as alternate functions, port pin can be
used as a corresponding alternate features.
I O I O I O I O
7 6 5
4 3 2 1
0 PORT
I: INPUT PORT
O: OUTPUT PORT
Port 4 Data Register
R4
R47 R46 R45 R44 R43 R42 R41 R40
Figure 10. Example port I/O assignment
Reading data register reads the status of the pins
whereas writing to it will write to the port latch.
R0 and R0DD registers: R0 is a 8-bit bidirectional
I/O port (address C0H). Each pin is individually configurable as input and output through the R0DD register (address C1H).
Port 0 Data Register
R0
ADDRESS: C0H
RESET VALUE: Undefined
R07 R06 R05 R04 R03 R02 R01 R00
Input/ Output data
Port 0 Direction Register
R0DD
ADDRESS: C1H
RESET VALUE: 00000000
R07 R06 R05 R04 R03 R02 R01 R00
Direction select
0: Input
1: Output
22
ADDRESS: C8H
RESET VALUE: Undefined
Input/ Output data
Port 4 Direction Register
R4DD
ADDRESS: C9H
RESET VALUE: 00000000
R47 R46 R45 R44 R43 R42 R41 R40
Direction select
0: Input
1: Output
HYUNDAI MicroElectronics
GMS81504
R5 and R5DD registers: R5 is a 3-bit bidirectional
I/O port (address CAH). R55, R56 and R57 only are
physically implemented on this device.
R56, R57 have internal pullups which is activated on
input but deactivated on output. As input, these pins
that are externally pull low will source current (IP2 on
the DC characteristics) because of the internal pullups.
Caution:
Pins R56, R57 are served on 30SDIP package
only, but not served on 28SOP . Refer to Pin
assignment.
ADDRESS: CAH
RESET VALUE: Undefined
Port 5 Data Register
R5
-
-
R55
-
-
-
Input/ Output data
ADDRESS: CBH
RESET VALUE: --0---00
Port 5 Direction Register
R5DD
-
-
R55
-
-
-
Each pin is individually configurable as input and
output through the R5DD register (address CBH).
Port Pin
MSB
-
EC0S
-
-
-
-
BUZS
-
-
-
-
-
0: R55
1: BUZ (Buzzer Port)
INT1S INT0S
0: R40
1: INT0
0: R41
1: INT1
0: R46
1: T1O
Edge Selection Register
ADDRESS: F8H
RESET VALUE: ----0000
MSB
-
PMR5
LSB
T1S
0: R44
1: EC0
IEDS
ADDRESS: D1H
RESET VALUE: --0-----
ADDRESS: D0H
RESET VALUE: -0-0--00
Port 4 Mode Register
-
Direction select
0: Input
1: Output
Port 5 Mode Register
The control register PMR5 (address D1H) controls the
selection alternate function. After reset, this value is
"0", port may be used as general I/O ports. To use
buzzer function, write "1" to the PMR5.
PMR4
R51 R50
Alternate Function
BUZ (Square-wave output for
Buzzer driving)
R55
R51 R50
LSB
-
-
INT1
INT0
External Interrupt Edge select
00: Reserved
01: Falling (1-to-0 transition)
10: Rising (0-to-1 transition)
11: Both (Rising & Falling)
LSB
23
GMS81504
HYUNDAI MicroElectronics
R6 and R6DD registers: R6 is a 4-bit port (address
CCH). Pins R64~R67 are individually configurable as
input and output through the R6DD register (address
CDH).
Port Pin
R64
R65
R66
R67
R6DD (address CDH) controls the direction of the R6
pins, even when they are being used as analog inputs.
The user must make sure to keep the pins configured
as inputs when using them as analog inputs.
24
R6
Alternate Function
AN4 (ADC input 4)
AN5 (ADC input 5)
AN6 (ADC input 6)
AN7 (ADC input 7)
ADDRESS: CCH
RESET VALUE: Undefined
Port 6 Data Register
R67 R66 R65 R64
-
-
-
-
Input/ Output data
Port 6 Direction Register
R6DD
R67 R66 R65 R64
-
ADDRESS: CDH
RESET VALUE: 0000----
-
-
Direction select
0: Input
1: Output
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GMS81504
BASIC INTERVAL TIMER
timer interrupt. The BITR is interrupt request flag of
Basic interval timer.
The GMS81504 has one 8-bit Basic Interval Timer that
is free-run, can not stop. Block diagram is shown in
Figure 11.
The 8-bit Basic interval timer register (BITR) is incremented every internal count pulse which is divided by
prescaler. Since prescaler has divided ratio by 16 to
2048, the count rate is 1/16 to 1/2048 of the oscillator
frequency. As the count overflows from FFH to 00H,
this overflow causes to generate the Basic interval
BTS[2:0]
XIN PIN
8
When write "1" to bit BTCL of CKCTLR, data register
is cleared to "0" and restart to count-up. It becomes "0"
after one machine cycle by hardware.
BTCL
CLEAR
3
÷16
÷32
÷64
÷128
÷256
÷512
÷1024
÷2048
Caution:
All control bits of Basic interval timer are in
CKCTLR register which is located at same address with BITR (address D3H). Address D3H is
read as BITR, written to CKCTLR.
MUX
BITR (8 BITS)
BASIC INTERVAL TIMER
INTERRUPT
BITIF
PRESCALER
Figure 11. Block Diagram of The Basic Interval Timer
CKCTLR
Symbol
-
-
-
ENPCK BTCL
Position
BTS2
BTS1
BTS0
ADDRESS: D3H
RESET VALUE: ---10111
Name and Significance
ENPCK
CKCTLR.4
Enable Peripheral clock.
1: Supply clock to every peripherals
0: Stop clock
BTCL
CKCTLR.3
BTCL is set to "1", BITR is cleared. BTCL becomes "0" automatically
after one machine cycle, and starts counting.
BASIC INTERVAL TIMER CLOCK SELECTION
BTS2
BTS1
BTS0
Prescale value
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
32
64
128
256
512
1024
2048
Figure 12. CKCTLR: Control Clock Register
25
GMS81504
HYUNDAI MicroElectronics
In addition the "capture" function, the register is incremented in response external or internal clock sources
same with timer or counter function. When external
clock edge input, the count register is captured into
Timer data register correspondingly.
TIMER/COUNTER
The GMS81504 has two Timer/Counter registers.
Each module can generate an interrupt to indicate that
an event has occurred (i.e. timer match).
Timer 0 and Timer 1 are can be used either the two
8-bit Timer/Counter or one 16-bit Timer/Counter to
combine them.
It has four operating modes: "8-bit timer/counter",
"16-bit timer/counter", "8-bit capture", "16-bit capture" which are selected by bit in Timer mode register
TM0 as shown in right Table.
In the "timer" function, the register is incremented
every internal clock input. Thus, one can think of it as
counting internal clock input. Since a least clock consists of 4 and most clock consists of 64 oscillator
periods, the count rate is 1/4 to 1/64 of the oscillator
frequency.
TM0 FOR TIMER 0, TIMER 1
CAP0
T1SL1
T1SL0
0
0
0
16-bit Timer/Counter
In the "counter" function, the register is incremented
in response to a 1-to-0 (falling edge) transition at its
corresponding external input pin, EC0.
EX)
Timer 0
Timer 1
1
0
0
16-bit Capture
0
X
X
8-bit Timer
8-bit Timer
1
X
X
8-bit Capture
8-bit Timer
When TM0: 00110111 (PRESCALER= 16)
TDR0: FAH = 250D
OSCILLATOR FREQ.= 4MHz
INTERRUPT PERIOD =
1
× 16 × 250 = 1ms
4 × 106 Hz
COUNT PULSE
PERIOD
MATCH
(TDR0 = T0)
4 us
FA
F9
F8
F7
F6
F5
F4
F3
F2
F1
TDR0
3
1
2
00H
CLEAR
TIMER 0
INTERRUPT
CLEAR
OCCUR INTERRUPT
OCCUR INTERRUPT
CLEAR
OCCUR INTERRUPT
INTERRUPT
PERIOD
Figure 13. Timer Count Operation Example
26
TIME
HYUNDAI MicroElectronics
GMS81504
MATCH
TDR0
MATCH
Stop
Stop
Restart
Clear and Start
Count Up
00H
CLEAR
TIMER
INTERRUPT
OCCUR INTERRUPT
CLEAR
CLEAR
TIME
OCCUR INTERRUPT
HIGH
TxST
LOW
HIGH
TxCN
LOW
Figure 14. Timer Count Operation
27
GMS81504
HYUNDAI MicroElectronics
8-bit Timer/Counter Mode
The GMS81504 has two 8-bit Timer/Counters, Timer
0, Timer 1. The Timer 0, Timer 1 only as shown in
Figure 15.
The "timer" or "counter" function is selected by control
registers TM0 as shown in Figure 17. To use as an
8-bit timer/counter mode, bit CAP0 of TM0 should be
cleared to "0" and bits T1SL1, T1SL0 of TM0 should
not set to zero (Figure 15).
These timers have each 8-bit count register and data
register. The count register is incremented by every
internal or external clock input. The internal clock has
a prescaler divide ratio option of 4, 16, 64 (selected by
control bits T1SL1, T1SL0 of register TM0).
In the Timer 0, timer register T0 increments from 00H
until it matches TDR0 and then reset to 00H. The match
output of Timer 0 generates Timer 0 interrupt (latched
in T0IF bit)
As TDRx and Tx register are in same address, when
reading it as a Tx, written to TDRx.
Caution:
The contents of Timer data register TDRx should
be initialized 1H~FFH except 0H, because it is undefined after reset.
In counter function, the counter is incremented every
1-to-0 (falling edge) transition of EC0 pin. In order to
use counter function, the bit EC0S of the Port mode
register PMR4 are set to "1". The Timer 0 can be used
as a counter by pin EC0 input, but Timer 1 can not.
MSB
TM0
LSB
CAP0
T1ST
0
X
T1SL1 T1SL0
≠0
≠0
EDGE DETECTOR
X
X
T0SL1 T0SL0
X
"0"
EC0 PIN
"1"
÷4
÷ 16
÷ 64
T0CN
ADDRESS: E2H
RESET VALUE: 00H
X
T0ST
0: Stop
1: Clear and Start
T0SL[1:0]
XIN PIN
T0ST
CLEAR
T0 (8-BITS)
MUX
T0CN
T0IF
PRESCALER
COMPARATOR
TIMER 0
INTERRUPT
TIMER 0
TDR0 (8-BITS)
T1SL[1:0]
MUX
T1ST
0: Stop
1: Clear and Start
CLEAR
T1 (8-BITS)
TIMER 1
T1IF
TIMER 1
INTERRUPT
F/F
T1O PIN
COMPARATOR
TDR1 (8-BITS)
Figure 15. 8-bit Timer/Counter Mode
28
HYUNDAI MicroElectronics
GMS81504
To pulse out, the timer match can goes to port pin as
shown in Figure 15. Thus, pulse out is generated by
the timer match. These operation is implemented to pin
T1O. The pin T1O is output from Timer 1. Output
frequency is calculated as following equation.
fT1O (Hz) =
fT1O: Pin T1O output pulse frequency
fXIN: Oscillator frequency
Prescaler: Refer to bit T1SL1,T1SL0 of TM0 at Figure 17.
MSB
PMR4
-
fXIN
2 ⋅ Prescaler ⋅ TDR
LSB
T1S
-
EC0S
-
-
INT1S INT0S
ADDRESS: D0H
RESET VALUE: -0-0--00
0: R40
1: INT0 (EXTERNAL INTERRUPT 0)
0: R41
1: INT1 (EXTERNAL INTERRUPT 1)
0: R44
1: EC0 (EXTERNAL INPUT PIN FOR TIMER 0)
0: R46
1: T1O (TIMER 1 PULSE OUTPUT)
Figure 16. PMR4: R4 Port Mode Register
MSB
TM0
CAP0
LSB
T1ST
T1SL1 T1SL0
T0ST
T0CN T0SL1 T0SL0
TIMER 1
TIMER 0
CAP0 Capture mode selection flag, When set, timer
operate as one 16-bit capture timer combine
two 8-bit timers.
T0ST
T1ST
T0CN Start/Stop control for Timer 0. A logic 1
starts the timer.
When set, Timer 1 count register is cleared
and start again.
When cleared, stop the counting.
TIMER 1
T1SL1
0
0
1
1
ADDRESS: E2H
RESET VALUE: 00H
When set, The Timer 0 Count Register is
cleared and start again.
When cleared, stop the counting.
TIMER 0
T1SL0 INPUT CLOCK
0
1
0
1
16-BIT TIMER MODE (NOTE 1)
8-BIT TIMER, ÷ 4 ← PRESCALER
8-BIT TIMER, ÷ 16
8-BIT TIMER, ÷ 64
T0SL1
0
0
1
1
T0SL0 INPUT CLOCK
0
1
0
1
Timer or Counter select
÷ 4 ← PRESCALER
÷ 16
÷ 64
NOTE:
If this mode selected, the Timer 0 are used as a 16-bit timer mode. The Timer 1 is engaged to the Timer 0.
The source clock is selected by bits T0SL1 and T0SL0.
Figure 17. TM0: Timer 0, Timer 1 Mode Register
29
GMS81504
HYUNDAI MicroElectronics
The clock source of the Timer 0 is selected either
internal or external clock by bit T0SL1, T0SL0.
16-bit Timer/Counter Mode
The Timer register is being run with all 16 bits. A 16-bit
timer/counter register T0, T1 are incremented from
0000H until it matches TDR0, TDR1 and then resets
to 0000H. The match output generates Timer 0 interrupt.
Bit T1ST is not effect in this 16-bit mode.
Bit T0SL1 and T0SL0 select the clock source among
three prescaler divide ratio and external EC0 clock.
MSB
TM0
T0SL[1:0]
LSB
CAP0
T1ST
0
X
T1SL1 T1SL0
0
0
EDGE DETECTOR
"0"
XIN PIN
÷4
÷ 16
÷ 64
PRESCALER
MUX
"1"
T0CN
X
X
ADDRESS: E2H
T0SL1 T0SL0
RESET VALUE: 00H
X
X
T0ST
0: Stop
1: Clear and Start
DO NOT CARE
EC0 PIN
T0ST
T1
T0
(16 BITS)
CLEAR
T0CN
TDR1
TDR0
(16 BITS)
HIGHER
LOWER
Figure 18. 16-bit Timer/Counter Mode
30
TIMER 0
INTERRUPT
(NOT TIMER 1 INTERRUPT)
T0IF
COMPARATOR
TIMER 0 + TIMER 1
HYUNDAI MicroElectronics
GMS81504
register T0, to be captured into registers CDR0, respectively. After captured, Timer 0 register T0 is cleared
and restarts by hardware.
8-bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer
mode register TM0 as shown in Figure 19. In this
mode, Timer 1 still operates as an 8-bit timer/counter.
In 8-bit capture mode, Timer 1 can not be used as
capture mode.
Caution:
The CDRx and TDRx are in same address.
In the capture mode, reading operation is read the
CDRx, not TDRx because path is opened to the
CDRx.
The Timer/Counter register is incremented in response
internal or external input. This counting function is
same with normal timer mode, but Timer interrupt is
not generated. Timer/Counter still does the above, but
with the added feature that a edge transition at external
input INT0 pin causes the current value in the Timer 0
It has three transition modes: "falling edge", "rising
edge", "both edge" which are selected by interrupt
edge selection register IEDS (Refer to External interrupt section). In addition, the transition at INT0 pin
generates an interrupt signal.
MSB
TM0
LSB
CAP0
T1ST
T1SL1
T1SL0
T0ST
T0CN
T0SL1
T0SL0
1
X
≠0
≠0
X
X
X
X
T0ST
0: Stop
1: Clear and Start
T0SL[1:0]
EDGE DETECTOR
0
EC0 PIN
XIN PIN
ADDRESS: E2H
RESET VALUE: 00H
T0 (8-BITS)
÷4
÷ 16
÷ 64
MUX
1
T0CN
CAPTURE
PRESCALER
TIMER 0
CDR0 (8-BITS)
INT0 PIN
INT0IF
T1SL[1:0] ≠ 00
IEDS[1:0]
MUX
INT0
INTERRUPT
T1ST
0: Stop
1: Clear and Start
T1 (8-BITS)
CLEAR
TIMER 1
T1IF
TIMER 1
INTERRUPT
F/F
T1O PIN
COMPARATOR
TDR1 (8-BITS)
Figure 19. 8-bit Capture Mode
31
GMS81504
HYUNDAI MicroElectronics
16-bit Capture Mode
Bit T1ST is not effect in this 16-bit mode.
16-bit capture mode is the same as 8-bit capture, except
that the Timer register is being run will 16 bits.
Bit T0SL1 and T0SL0 select the clock source among
three prescaler divide ratio and external EC0 clock.
DO NOT CARE
MSB
TM0
T1ST
T1SL1
T1SL0
T0ST
T0CN
T0SL1
T0SL0
1
X
0
0
X
X
X
X
EDGE DETECTOR
0
EC0 PIN
÷4
÷ 16
÷ 64
ADDRESS: E2H
RESET VALUE: 00H
T0ST
0: Stop
1: Clear and Start
T0SL[1:0]
XIN PIN
LSB
CAP0
1
MUX
T1
(8-BITS)
T0
(8-BITS)
CDR1
(8-BITS)
CDR0
(8-BITS)
HIGHER
LOWER
T0CN
PRESCALER
IEDS[1:0]
TIMER 0
+
TIMER 1
INT0 PIN
INT0IF
Figure 20. 16-bit Capture Mode
32
INT 0
INTERRUPT
HYUNDAI MicroElectronics
GMS81504
ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit
digital value. The A/D module has eight analog inputs,
which are multiplexed into one sample and hold. The
output of the sample and hold is the input into the
converter, which generates the result via successive
approximation. The analog supply voltage is connected to AVDD of ladder resistance of A/D module.
The A/D module has two registers which are the control register ADCM and A/D result register ADR. The
register ADCM, shown in Figure 22, controls the
operation of the A/D converter module. The port pins
can be configured as analog inputs or digital I/O. To
ADEN
"0"
AVDD PIN
R64/AN4
100
R65/AN5
101
110
R67/AN7
111
The processing of conversion is start when the start bit
ADST is set to "1". After one cycle, it is cleared by
hardware. The register ADR contains the results of the
A/D conversion. When the conversion is completed,
the result is loaded into the ADR, the A/D conversion
status bit ADSF is set to "1", and the A/D interrupt flag
AIF is set. The block diagram of the A/D module is
shown in Figure 21. The A/D status bit ADSF is set
automatically when A/D conversion is completed,
cleared when A/D conversion is in process. The conversion time takes maximum 40 uS (at fXIN=4 MHz).
ADS[2:0]
000~011: RESERVED
VIN
R66/AN6
How to Use A/D Converter
LADDER
RESISTOR
DECODER
"1"
3
use analog inputs, I/O is selected input mode by R6DD
direction register.
S/H
SUCCESSIVE
APPROXIMATION
CIRCUIT
AIF
A/D
INTERRUPT
SAMPLE & HOLD
ADR
INPUT CHANNEL SELECTION
ADDRESS: E9H
RESET VALUE: Undefined
A/D RESULT REGISTER
Figure 21. A/D Block Diagram
33
GMS81504
ADCM
HYUNDAI MicroElectronics
MSB
-
-
R/W
R/W
R/W
R/W
R/W
LSB
R
-
-
ADEN
ADS2
ADS1
ADS0
ADST
ADSF
ADDRESS: E8H
RESET VALUE: --00001
A/D status bit (READ ONLY)
0: A/D conversion is in process.
1: A/D conversion is completed, not in
process.
RESERVED
A/D start bit
1: Setting this bit starts an A/D conversion.
After one cycle, bit is cleared to "0".
0: Bit force to zero.
Analog channel select
000~011: Reserved
100: channel 4 (R64/AN4)
101: channel 5 (R65/AN5)
110: channel 6 (R66/AN6)
111: channel 7 (R67/AN7)
A/D converter Enable bit
0: A/D converter module shut off and
consumes no operating current.
1: Enable A/D converter
Figure 22. ADCM: A/D Converter Control Register
34
HYUNDAI MicroElectronics
GMS81504
BUZZER FUNCTION
The buzzer driver consists of 6-bit binary counter, the
buzzer register BUR and the clock selector. It generates square-wave which is very wide range frequency
(250 Hz~125 kHz at fXIN=4 MHz) by user programmable counter.
XIN PIN
fBUZ (Hz) =
COUNTER
(6 BIT)
MUX
PRESCALER
Pin R55 is assigned for output port of Buzzer driver by
setting the bit 5 of PMR5 (address D1H) to "1". At this
time, the pin R55 must be defined as output mode (the
bit 5 of R5DD=1). In the emulator, even if pin R55 is
defined as input, buzzer output is available.
The bit 0 to 5 of BUR determines output frequency for
buzzer sound.
Frequency calculation is following below.
÷ 16
÷ 32
÷ 64
÷ 128
F/F
BUZ PIN
BUR[7:6]
BUR[5:0]
(6 BIT)
BUR REGISTER
Figure 23. Buzzer Driver
clock from prescaler output.
The 6-bit buzzer counter is cleared and start the counting by writing signal to the register BUR. It is increment from 00H until it matches 6-bit register BUR.
fXIN
2 ⋅ Prescaler ratio ⋅ BUR value
fBUZ: Buzzer frequency
fXIN: Oscillator frequency
Prescaler: Prescaler divide ratio by BUCK1, BUCK0
BUR:Lower 6-bit of BUR. Buzzer period data value
Caution:
The register BUR contains undefined value after
reset. It must be initialized with 1H~3FH (none 0H).
The bits BUCK1, BUCK0 of BUR selects the source
MSB
BUR
LSB
BUCK1 BUCK0
BU5
BU4
BU3
BU2
Prescaler ratio
00: fXIN ÷ 16
01: fXIN ÷ 32
10: fXIN ÷ 64
11: fXIN ÷ 128
BU1
BU0
ADDRESS: ECH
RESET VALUE: Undefined
6-bit BUR value
Figure 24. BUR: Buzzer Period Data Register
MSB
PMR5
-
LSB
-
BUZS
-
-
-
-
-
ADDRESS: D1H
RESET VALUE: --0-----
R55/ BUZ Port Selection
0: R55
1: BUZ
Figure 25. PMR5: Port 5 Mode Register
35
GMS81504
HYUNDAI MicroElectronics
INTERRUPTS
The GMS81504 interrupt circuits consist of Interrupt
enable register (IENH, IENL), Interrupt request flags
of IRQH, IRQL, priority circuit and Master enable
flag(I flag of PSW). The configuration of interrupt
circuit is shown in Figure 1-26.
12 interrupt sources are provided including the Reset.
Interrupt source
Hardware RESET
External Interrupt 0
External Interrupt 1
Timer/Counter 0
Timer/Counter 1
AD Converter
Basic interval timer
Symbol
Priority
RESET
INT0IF
INT1IF
T0IF
T1IF
AIF
BITIF
1
2
3
4
5
6
7
*Vector addresses are shown in Program Memory
section.
The External Interrupts INT0, INT1 can each be transition-activated, depending on interrupt edge selection
register.
INTERRUPT REQUEST FLAG
INT0IF BIT 7
INT1
INT1IF BIT 6
TIMER0
T0IF
BIT 3
TIMER1
T1IF
BIT 2
BITIF
The interrupts are controlled by the interrupt master
enable flag I-flag (bit 2 of PSW), the interrupt enable
register (IENH, IENL) and the interrupt request flags
(in IRQH, IRQL) except Power-on reset and software
BRK interrupt.
Interrupt enable registers are shown in Figure 27.
These registers are composed of interrupt enable flags
of each interrupt source, these flags determines
whether an interrupt will be accepted or not. When
enable flag is "0", a corresponding interrupt source is
prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once.
0
1
IENL
BIT 7
I-flag is in PSW, it is cleared by "DI", set by "EI"
instruction.
When it goes interrupt service, I-flag is cleared by
hardware, thus any other interrupt are inhibited.
When interrupt service is completed by "RETI"
instruction, I-flag is set to "1" by hardware.
BRK (Software Interrupt)
PRIORITY
CONTROL
IRQL
BIT *
The Basic Interval Timer Interrupt is generated by
BITIF which are set by a overflow in the timer/counter
register.
IENH
IRQH
AIF
The AD converter Interrupt is generated by AIF which
is set by finishing the analog to digital conversion.
INTERRUPT ENABLE FLAG
INT0
ADC
The Timer 0, Timer 1 Interrupts are generated by T0IF,
T1IF, which are set by a match in their respective
timer/counter register.
0
1
RELEASE THE STOP
(IF IN STOP MODE)
TO CPU
I-FLAG
Master Interrupt
Enable Flag
BIT 5
RESET
NOTE:
* BIT: BASIC INTERVAL TIMER
Figure 1-26. Block Diagram of Interrupt Function
36
HYUNDAI MicroElectronics
GMS81504
MSB
IENH
LSB
INT0E INT1E
-
-
T0E
T1E
-
BITE
-
-
-
-
MSB
IENL
AE
ADDRESS: F6H
RESET VALUE: 00--00--
-
LSB
-
-
ADDRESS: F4H
RESET VALUE: 0-0-----
Enables or disables the interrupt individually.
If flag is cleared, the interrupt is disabled.
0: Disable
1: Enable
Figure 27. IENH, IENL: Interrupt Enable Registers
When an interrupt is responded to, the I-flag is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is vectored to. Once
in the interrupt service routine the source(s) of the
interrupt can be determined by polling the interrupt
flag bits.
The interrupt flag bit(s) must be cleared in software
before reenabling interrupts to avoid recursive interrupts. The Interrupt Request flags are able to be read
and write.
both edge. INT0, INT1 are multiplexed with general
I/O ports (R40, R41). To use external interrupt pin, set
bit 0 to bit 3 of the port mode register PMR4.
The PMR4 and IEDS registers are shown in Figure
30.
EDGE DETECTOR
IEDS[1:0]
INT0
INT0IF
INT0 INTERRUPT
External Interrupt
External interrupt on INT0, INT1 pins are edge triggered depending on the edge selection register IEDS.
IEDS[3:2]
INT1
INT1IF
INT1 INTERRUPT
The edge detection of external interrupt has three
transition activated mode: rising edge, falling edge,
Figure 28. External Interrupt
37
GMS81504
HYUNDAI MicroElectronics
MAX. 13 fOSC
8 fOSC
fXIN
INTERRUPT
ACTIVE
INTERRUPT
PROCESSING
INSTRUCTION EXECUTION
(INTERRUPT HOLDING)
INTERRUPT
ROUTINE
Figure 29. INT Pin Interrupt Timing
MSB
PMR4
-
LSB
T1S
-
EC0S
-
-
INT1S INT0S
ADDRESS: D0H
RESET VALUE: -0-0--00
0: R40
1: INT0 (EXTERNAL INTERRUPT 0)
0: R41
1: INT0 (EXTERNAL INTERRUPT 1)
0: R44
1: EC0 (EXTERNAL INPUT PIN FOR TIMER 0)
0: R46
1: T1O (TIMER 1 PULSE OUTPUT)
MSB
IEDS
-
LSB
-
-
-
IED1H IED1L IED0H IED0L
INT1
ADDRESS: F8H
RESET VALUE: ----0000
INT0
Edge selection register
IEDxH.IEDxL
00: Reserved
01: Falling (1-to-0 transition)
10: Rising (0-to-1 transition)
11: Both (Rising & Falling)
Figure 30. PMR4 and IEDS Registers
38
HYUNDAI MicroElectronics
GMS81504
BRK Interrupt
Multiple Interrupt
Software interrupt can be invoked by BRK instruction,
which is the lowest priority order.
If two requests of different priority levels are received
simultaneously, the request of higher priority level is
serviced. If requests of the same priority level are
received simultaneously, an internal polling sequence
determines by hardware which request is serviced.
Hardware interrupt priority is shown in Page36.
Interrupt vector address of BRK is shared with the
vector of TCALL0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of
PSW is set to distinguish BRK from TCALL0.
Each processing step is determined by B-flag as shown
below.
B-FLAG = 0
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER 0 is in progress.
Because of re-setting the interrupt enable registers IENH, IENL
and master enable flag "EI" in the Timer/Counter 0 routine.
=1
BRK or
TCALL0
BRK
INTERRUPT
ROUTINE
RETI
However, multiple processing through software for
special features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any
further interrupt. But as user set I-flag in interrupt
routine, some further interrupt can be serviced even if
certain interrupt is in progress.
TCALL0
ROUTINE
RET
TIMER 0
ROUTINE
MAIN
ROUTINE
INT 0
ROUTINE
MOV IENH,#80H
MOV IENL,#00H
EI
INT0
ROUTINE
Occur
TIMER 0 INTERRUPT
Figure 31. Execution of BRK/ TCALL0
RETI
MOV IENH,#FFH
MOV IENL,#FFH
RETI
Figure 32. Execution of Multi-Interrupt
39
GMS81504
HYUNDAI MicroElectronics
restored to its normal operating level, and must be held
active long enough to allow the oscillator to restart and
stabilize (minimum 20 msec).
STOP MODE
For applications where power consumption is a critical
factor, device provides reduced power of STOP.
Caution:
The NOP instruction have to be written more than
two to next line of the STOP instruction.
Ex)
STOP
NOP
NOP
An instruction that STOP causes that to be the last
instruction executed before going into the Stop mode.
In the Stop mode, the on-chip oscillator is stopped.
With the clock frozen, all functions are stopped, but
the on-chip RAM and Control registers are held. The
port pins out the values held by their respective port
data register Rx, port direction register RxDD. The
status of peripherals during Stop mode is shown below.
Peripheral
Status
RAM
Retain
Control registers
Retain
I/O
Retain
Oscillation
Stop
XIN
Low
XOUT
High
Release Stop Mode
The exit from Stop mode is hardware reset or external
interrupt. Reset redefines all the Control registers but
does not change the on-chip RAM. External interrupts
allow both on-chip RAM and Control registers to
retain their values.
If I-flag = 1, the normal interrupt response takes place.
If I-flag = 0, the chip will resume execution starting
with the instruction following the STOP instruction. It
will not vector to interrupt service routine.
In the Stop mode of operation, VDD can be reduced to
minimize power consumption. Care must be taken,
however, to ensure that VDD is not reduced before the
Stop mode is invoked, and that VDD is restored to its
normal operating level, before the Stop mode is terminated. The reset should not be activated before VDD is
When exit from Stop mode by external interrupt from
Stop mode, enough oscillation stabilization time is
required to normal operation. Figure 33 shows the
timing diagram. When release the Stop mode, the
OSCILLATOR
INTERNAL
CLOCK
EXTERNAL
INTERRUPT
BASIC INTERVAL
TIMER COUNTER
N
N+1
NORMAL OPERATION
N+2
00
01
FE
STOP INSTRUCTION
EXECUTION
CLEAR BASIC
INTERVAL TIMER
STOP MODE
STABILIZATION
TIME
FF
00
01
02
NORMAL OPERATION
tST > 20 ms
Figure 33. Timing of Stop Release by External Interrupt
40
03
HYUNDAI MicroElectronics
GMS81504
Wake-up and Reset Function Table
Chip Status
before event
Event
Chip function after event
PC
Oscillator
Circuit
RESET
Do not care
Vector
on
STOP instruction
Normal operation
N+1
off
External Interrupt
Normal operation
Vector
on
Vector
N+1
on
on
External Interrupt Wake-up
Stop, I-flag = 1
Stop, I-flag = 0
PC: Program Counter contents after the event.
N: Address of STOP instruction.
Basic interval timer is activated on wake-up. It is
incremented from 00H until FFH then 00H. The count
overflow is set to start normal operation. Therefore,
before STOP instruction, user must be set its relevant
prescaler divide ratio to have long enough time. This
guarantees that crystal oscillator has started and stabilized.
By reset, exit from Stop mode is shown in Figure 34.
Minimizing Current Consumption in
Stop Mode
The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the
user should turn-off output drivers that are sourcing or
sinking current, if it is practical. Weak pull-ups on port
pins should be turned off, if possible. All inputs should
be either as VSS or at VDD (or as close to rail as
possible). An intermediate voltage on an input pin
causes the input buffer to draw a significant amount of
current.
STOP MODE
OSCILLATOR
INTERNAL
CLOCK
RESET
STOP INSTRUCTION
EXECUTION
tST = 64 ms
at 8 MHz
STABILIZATION TIME
Time can not be control by software.
Figure 34. Timing of Stop Mode Release by Reset
41
GMS81504
HYUNDAI MicroElectronics
RESET
Register
The reset input is the RESET pin, which is the input to
a Schmitt Trigger. A reset in accomplished by holding
the RESET pin low for at least 8 oscillator periods,
while the oscillator running. After reset, 64ms (at 8
MHz) plus 7 oscillator periods are required to start
execution as shown in Figure 36.
Internal RAM is not affected by reset. When VDD is
turned on, the RAM content is indeterminate. Initial
state of each register is as follow. Therefore, this RAM
should be initialized before reading or testing it.
EX) 5V OPERATION
+5V
10KΩ
RESET
7042
+
10uF
4.2V RESET IC
Figure 35. Example of Reset circuit
1
A
X
Y
PSW
PC
SP
Content
X
X
X
00H
X
X
R0
R0DD
R4
R4DD
R5
R5DD
R6
R6DD
PMR4
PMR5
X
00000000
X
00000000
X
000----X
0000----0-0--00
--0-----
BITR
CKCTLR
TM0
TDR0/ T0/ CDR0
TDR1/ T1/ CDR1
00H
--010111
00H
X
X
ADCM
ADR
BUR
--000001
X
X
IENH
IENL
IRQH
IRQL
IEDS
- = unimplemented bit
X= unknown
00--00-0-0----00--00-0-0---------000
2
3
?
?
4
5
6
7
OSCILLATOR
RESET
ADDRESS BUS
DATA BUS
?
?
tST = 64 ms
at 8 MHz
?
?
?
?
FFFE FFFF
FE
RESET PROCESS STEP
STABILIZATION TIME
Figure 36. Timing Diagram after Reset
42
ADL
Start
ADH
OP Code
MAIN PROGRAM
HYUNDAI MicroElectronics
GMS81504
OSCILLATOR CIRCUIT
XIN and XOUT are the input and output, respectively,
of a inverting amplifier which can be configured for
use as an on-chip oscillator, as shown in Figure 37.
C1
VSS
XIN
XOUT
XOUT
C2
RESET
XIN
VSS
R00
R01
Recommend:
C1,C2 = 30 pF ± 10 pF for Crystals.
Figure 38. Layout of Crystal
Figure 37. Oscillator Connections
To drive the device from an external clock source,
XOUT should be left unconnected while XIN is driven
as shown in Figure 39. There are no requirements on
the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must be
observed.
N/C
EXTERNAL
OSCILLATOR
SIGNAL
Oscillation circuit is designed to be used either with a
ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal
manufacturer for appropriate values of external components.
In addition, see Figure 38. for the layout of the crystal.
In all cases, an external clock operation is available.
XOUT
XIN
VSS
Figure 39. External Clock Drive
Configuration
43
GMS81504
OTP PROGRAMMING
The GMS81504T is one-time PROM (OTP) microcontroller with 4K bytes electrically programmable
read only memory for the GMS81504 system evaluation, first production and fast mass production.
To programming the OTP device, user can have two
way. One is using the universal programmer which is
support HME microcontrollers, other is using the general EPROM programmer.
HYUNDAI MicroElectronics
In assembler and file type, two files are generated after
compiled. One is "*.HEX", another is "*.OTP". The
"*.HEX" file is used for emulation in circuit emulator
CHOICE-JrTM and "*.OTP" file is used for programming to OTP device.
Programming Procedure
1. Select the EPROM device and manufacturer on
EPROM programmer (Intel 27C256)
1. Using the Universal programmer
2. Select the programming algorithm as a Intelligent
mode (apply 1ms writing pulse).
Third party universal programmer are shown as below.
3. Load the file (*.OTP) to the programmer.
Manufacturer: Advantech
Web site: http://www.aec.com.tw
Programmer: LabTool-48
4. Set the programming address range as below table.
Address
Set Value
Manufacturer: Hi-Lo systems
Web site: http://www.hilosystems.com.tw
Programmer: ALL-11, GANG-08
Buffer start address
7000H
Buffer end address
7FFFH
Socket adapters are supported from third party programmer manufacturer.
Device start address
7000H
2. Using the general EPROM(27C256)
programmer
When user use general EPROM programmer, socket
adaper is essencially necessary. It convert pin to fit the
pin of general 27C256 EPROM.
Socket Adapter: OA815A-30SD (30SDIP)
44
5. Mount the socket adapter with the OTP device onto
the PROM programmer.
6. Start the PROM programmer to programming/
verifying.
GMS81504T PROGRAMMING
MANUAL
HYUNDAI MicroElectronics
GMS81504T PROGRAMMING SPECIFICATION
DEVICE OVERVIEW
The GMS81504T is a high-performance CMOS 8-bit microcontroller with 4K bytes of EPROM. The device is
one of GMS800 family. The HYUNDAI GMS81504T is a powerful microcontroller which provides a highly
flexible and cost effective solution to many embedded control applications. The GMS81504T provides the
following standard features: 4K bytes of EPROM, 128 bytes of RAM, 23 I/O lines, 16-bit or 8-bit timer/counter,
a precision analog to digital converter, on-chip oscillator and clock circuitry.
PIN DESCRIPTION
Pin No.
MCU Mode
OTP Mode
Pin No.
MCU Mode
OTP Mode
1
R01
I/O
O1
I/O
16
R57
I/O
A9
I
2
R00
I/O
O0
I/O
17
RESET
I
(1)
I
3
R47
I/O
A0
I
18
XIN
I
(1)
I
4
R46
I/O
A1
I
19
XOUT
O
(2)
O
5
R45
I/O
CE
I
20
VSS
VSS
VSS
VSS
6
R44
I/O
OE
I
21
R43
I/O
A10
I
7
R67/AN7
I/O
A2
I
22
R42
I/O
A11
I
8
R66/AN6
I/O
A3
I
23
TEST
I/O
VPP
VPP
9
AVREF
I
(1)
I
24
R07
I/O
O7
I/O
10
R65/AN5
I/O
A4
I
25
R06
I/O
O6
I/O
11
R64/AN4
I/O
(1)
I
26
R05
I/O
O5
I/O
12
R41/INT1
I/O
A5
I
27
R04
I/O
O4
I/O
13
R40/INT0
I/O
A6
I
28
R03
I/O
O3
I/O
14
R55/BUZ
I/O
A7
I
29
R02
I/O
O2
I/O
15
R56
I/O
A8
I
30
V DD
VDD
VDD
VDD
NOTES:
1. Check marked pins must be connected on VSS, because these
pins are input ports during programming, program verify and reading
2. XOUT pin must be opened during programming.
I/O: Input/Output Pin
I: Input Pin
O: Output Pin
1
GMS81504T PROGRAMMING SPECIFICATION
HYUNDAI MicroElectronics
PIN FUNCTION (OTP Mode)
VPP (Program Voltage)
VPP is the input for the program voltage for programming the EPROM.
CE ( Chip Enable)
CE is the input for programming and verifying internal EPROM.
OE (Output Enable)
OE is the input of data output control signal for verify.
A0~A11 (Address Bus)
A0~A11 are address input pins for internal EPROM.
O0~O7 (EPROM Data Bus)
These are data bus for internal EPROM.
Pin connection during programming
PROGRAMMING
The GMS81504T has address A0~A11 pins. Therefore, the programmer just program 4K bytes data (address
7000H to 7FFFH) into the GMS81504T OTP device. During the programming, addresses A12~A15 of the
programmer must be pulled to a logic high.
When the programmer write the data from 7000H to 7FFFH, consequently, the data actually will be written into
addresses F000H to FFFFHof the OTP device.
1. The data format to be programmed is made up of Motorola S1 format.
Ex) "Motorola S1" format;
S0080000574154434880
S1247000E1FF3BFF04A13F8F06E101711B821B1BE01D1B3B191BF6181BF01C1BFF081BFF0AB0
S12470211BF5091BFF0B1BFF3F1B003E1B003D1B003C1BFF3B1B003A1BFF391BFF381BFF350D
:
:
S1057FF2983FB2
S1057FFEFF0F6F
S9030000FC
2. Down load above data into programmer from PC.
3. Programming the data from address 7000H to 7FFFH into OTP MCU, the data must be turned over respectively,
and then record the data.When read the data, it also must be turned over.
Ex) 00(00000000)→FF(11111111), 76(01110110)→89(10001001), FF(11111111)→00(00000000) etc.
4. Of course, the check sum is result of the sum of whole data from address 7000H to 7FFFH in the file (not reverse
2
HYUNDAI MicroElectronics
GMS81504T PROGRAMMING SPECIFICATION
data of theOTP MCU).
* When GMS81504T shipped, the blank data of it is initially 00H (not FFH).
Programming Flow
Buffer Start Address:7000H
Buffer End Address: 7FFFH
Device Start Address: F000H
GMS81504T
xxxxxxxx.OTP
Address
F000H
Program
Verify
Reading
Program
area
Down
Loading
Universal
Programmer
4 K BYTES
Address
7000H
File Type:
Motorola
S-format
7FFFH
FFFFH
Programming Example
Data
1E
00
C4
00
FC
5E
C0
70
:
:
:
:
67
C0
:
00
F0
Address
F000H
F001H
F002H
F003H
F004H
F005H
F006H
F007H
:
:
:
:
FFF2H
FFF3H
:
FFFEH
FFFFH
File
xxxxxxxx.OTP
Programmer
Buffer
GMS81504T device
Program
Reading
Verify
Data
E1
FF
3B
FF
04
A1
3F
8F
:
:
:
:
98
3F
:
FF
0F
Address
7000H
7001H
7002H
7003H
7004H
7005H
7006H
7007H
:
:
:
:
7FF2H
7FF3H
:
7FFEH
7FFFH
Down
Loading
Up
Loading
Data
E1
FF
3B
FF
04
A1
3F
8F
:
:
:
:
98
3F
:
FF
0F
Address
7000H
7001H
7002H
7003H
7004H
7005H
7006H
7007H
:
:
:
:
7FF2H
7FF3H
:
7FFEH
7FFFH
Checksum = E1+FF+3B+FF+04+A1+3F+8F+ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ + 98+3F+ ⋅ ⋅ ⋅ ⋅ +FF+0F
3
GMS81504T PROGRAMMING SPECIFICATION
HYUNDAI MicroElectronics
DEVICE OPERATION MODE
(TA = 25°C ± 5°C)
Mode
Read
CE
OE
A0~A11
VPP
VDD
O0~O7
X
VDD
5.0V
DOUT
X
Output Disable
VIH
VIH
X
VDD
5.0V
Hi-Z
Programming
VIL
VIH
X
VPP
VDD
DIN
X
VPP
VDD
DOUT
Program Verify
X
NOTES:
1. X = Either VIL or VIH
2. See DC Characteristics Table for VDD and VPP voltages during programming.
DC CHARACTERISTICS
(VSS=0 V, TA = 25°C ± 5°C)
Symbol
VPP
VDD(1)
Item
Min
Typ
Max
Unit
Intelligent Programming
12.0
-
13.0
V
Quick-pulse Programming
12.5
-
13.0
V
Intelligent Programming
5.75
-
6.25
V
Quick-pulse Programming
6.0
-
6.5
V
50
mA
30
mA
IPP (2)
VPP supply current
IDD (2)
VDD supply current
VIH
Input high voltage
VIL
Input low voltage
VOH
Output high voltage
VOL
Output low voltage
IIL
Input leakage current
0.8 VDD
CE=VIL
V
0.2 VDD
V DD-1.0
V
V
IOH = -2.5 mA
0.4
V
IOL = 2.1 mA
5
uA
NOTES:
1. VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. The maximum current value is with outputs O0 to O7 unloaded.
4
Test condition
HYUNDAI MicroElectronics
GMS81504T PROGRAMMING SPECIFICATION
SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be steady
Will be steady
May change
from H to L
Will be changing
from H to L
May change
from L to H
Will be changing
from L to H
Do not care any
change permitted
Changing state
unknown
Does not apply
Center line is
high impedance
"Off" state
READING WAVEFORMS
VIH
Addresses
Address Valid
VIL
VIH
(2)
OE
VIL
tAS
tOE
tDH
VIH
High-Z
Output
Valid Output
VIL
NOTES:
1. The input timing reference level is 1.0 V for a VIL and 4.0V for a VIH at VDD=5.0V
2. To read the output data, transition requires on the OE from the high to the low after address setup time tAS.
5
GMS81504T PROGRAMMING SPECIFICATION
HYUNDAI MicroElectronics
PROGRAMMING ALGORITHM WAVEFORMS
Program
Verify
Program
VIH
Addresses
Address Stable
VIL
tAS
tAH
VIH
Data
High-Z
Data In Stable
VIL
Data out Valid
tDH
tDS
12.5V
VPP
VDD
tVPS
6.0V
VDD
5.0V
tVDS
VIH
CE
VIL
tPW
tOES
VIH
OE
VIL
tOPW
NOTES:
1. The input timing reference level is 1.0 V for a VIL and 4.0V for a VIH at VDD=5.0V
6
tOE
tDFP
HYUNDAI MicroElectronics
GMS81504T PROGRAMMING SPECIFICATION
AC READING CHARACTERISTICS
(VSS=0 V, TA = 25°C ± 5°C)
Symbol
Item
Min
tAS
Address setup time
tOE
Data output delay time
tDH
Data hold time
Typ
Max
Unit
2
Test condition
us
200
ns
0
ns
NOTES:
1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
AC PROGRAMMING CHARACTERISTICS
(VSS=0 V, TA = 25°C ± 5°C; See DC Characteristics Table for VDD and VPP voltages.)
Symbol
Item
Min
Typ
Max
Unit
Address set-up time
2
us
tOES
OE set-up time
2
us
tDS
Data setup time
2
us
tAH
Address hold time
0
us
tDH
Data hold time
1
us
tDFP
Output disable delay time
0
us
tVPS
VPP setup time
2
us
tVDS
VDD setup time
2
us
tPW
Program pulse width
0.95
CE pulse width when over
programming
2.85
tAS
tOPW
tOE
Data output delay time
*AC CONDITIONS OF TEST
Input Rise and Fall Times (10% to 90%)
Input Pulse Levels . . . . . . . . . . .
Input Timing Reference Level . . . . .
Output Timing Reference Level . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1.0
1.05
ms
78.75
ms
200
ns
Condition*
(Note 1)
(Note 2)
20 ns
0.45V to 4.55V
1.0V to 4.0V
1.0V to 4.0V
NOTES:
1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. The length of the overprogram pulse may vary from 2.85 msec to 78.75 msec as a function of the iteration counter value X
(Intelligent Programming Algorithm only). Refer to page 8.
7
GMS81504T PROGRAMMING SPECIFICATION
HYUNDAI MicroElectronics
Intelligent Programming Algorithm
START
ADDRESS= FIRST LOCATION
VCC = 6.0V
VPP = 12.5V
X=0
PROGRAM ONE 1 ms PULSE
INCREMENT X
X = 25 ?
YES
NO
FAIL
VERIFY
BYTE
VERIFY
ONE BYTE
FAIL
PASS
PASS
PROGRAM ONE PULSE
OF 3X msec DURATION
INCREMENT
ADDRESS
NO
LAST
ADDRESS ?
YES
VCC = VPP = 5.0V
COMPARE
ALL BYTES TO
ORIGINAL
DATA
FAIL
PASS
DEVICE PASSED
8
DEVICE FAILED
MASK ORDER & VERIFICATION SHEET
GMS81504-HB
Customer should write inside thick line box.
1. Customer Information
Company Name
2. Device Information
Package
YYYY
MM
Mask Data
Application
DD
Order Date
Tel:
Fax:
30SDIP
Hitel
28SOP
Chollian
Internet
File Name
Check Sum
.OTP
(
)
27256
0 00 0 h
S et “F F h ” in
th is a re a
Name &
Signature:
6F F F h
7 00 0 h
7F F F h
( 4K )
.O T P file da ta
(Please check mark into
)
3. Marking Specification
Customer’s logo
HME
GMS81504-HBxxx
GMS81504-HBxxx
KOREA
YYWW
YYWW
KOREA
Customer logo is not required
Customer’s part number
HME ROM code number
Note: If the customer logo must be used in the special mark
Please submit a clean original of the logo.
4. Delivery Schedule
Quantity
Date
Customer Sample
YYYY
MM
DD
Risk Order
YYYY
MM
DD
5. ROM Code Verification
Verification D ate:
YYYY
pcs
pcs
This box is written after “5.Verification”.
MM
DD
YYYY
MM
DD
Approval Date:
Please confirm our verification data.
Check Sum:
Tel:
Name &
Signature:
HME Confirmation
Fax:
I agree w ith your verification data and confirm
you to m ake m ask set.
Tel:
Fax:
Name &
Signature:
HYUNDAI MicroElectronics