ETC MC80F0104B

MAGNACHIP SEMICONDUCTOR LTD.
8-BIT SINGLE-CHIP MICROCONTROLLERS
MC80F0104/0204
MC80C0104/0204
Preliminary User’s Manual (Ver. 0.2)
REVISION HISTORY
VERSION 0.2 (MAR. 2005) This book
Fix some errata.
VERSION 0.1 (MAR. 2005) This book
First Edition
Version 0.2
Published by
MCU Application Team
2005 MagnaChip semiconductor Ltd. All right reserved.
Additional information of this manual may be served by MagnaChip semiconductor offices in Korea or Distributors and Representatives.
MagnaChip semiconductor reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable; however, MagnaChip semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
Preliminary
MC80F0104/0204
1. OVERVIEW ...................................................................................................................................................... 1
Description ...................................................................................................................................................... 1
Features .......................................................................................................................................................... 1
Development Tools ......................................................................................................................................... 2
Ordering Information ................................................................................................................................. 3
2. BLOCK DIAGRAM .......................................................................................................................................... 4
3. PIN ASSIGNMENT .......................................................................................................................................... 5
4. PACKAGE DRAWING ..................................................................................................................................... 6
5. PIN FUNCTION ................................................................................................................................................ 8
6. PORT STRUCTURES .................................................................................................................................... 10
7. ELECTRICAL CHARACTERISTICS ............................................................................................................. 14
Absolute Maximum Ratings .......................................................................................................................... 14
Recommended Operating Conditions ........................................................................................................... 14
A/D Converter Characteristics ...................................................................................................................... 14
DC Electrical Characteristics ........................................................................................................................ 15
AC Characteristics ........................................................................................................................................ 16
Typical Characteristics .................................................................................................................................. 17
8. MEMORY ORGANIZATION .......................................................................................................................... 18
Registers ....................................................................................................................................................... 18
Program Memory .......................................................................................................................................... 21
Data Memory ................................................................................................................................................ 24
Addressing Mode .......................................................................................................................................... 29
9. I/O PORTS ..................................................................................................................................................... 33
R0 and R0IO register .................................................................................................................................... 33
R1 and R1IO register .................................................................................................................................... 34
R3 and R3IO register .................................................................................................................................... 36
10. CLOCK GENERATOR ................................................................................................................................ 37
Oscillation Circuit ......................................................................................................................................... 37
11. BASIC INTERVAL TIMER ........................................................................................................................... 39
12. WATCHDOG TIMER ................................................................................................................................... 41
13. TIMER/EVENT COUNTER .......................................................................................................................... 44
8-bit Timer / Counter Mode ........................................................................................................................... 47
16-bit Timer / Counter Mode ......................................................................................................................... 52
8-bit Compare Output (16-bit) ....................................................................................................................... 53
8-bit Capture Mode ....................................................................................................................................... 53
16-bit Capture Mode ..................................................................................................................................... 58
....................................................................................................................................................PWM Mode 60
14. ANALOG TO DIGITAL CONVERTER ......................................................................................................... 64
15. SERIAL INPUT/OUTPUT (SIO) ................................................................................................................... 67
Transmission/Receiving Timing .................................................................................................................... 68
The usage of Serial I/O ................................................................................................................................. 70
The Method to Test Correct Transmission .................................................................................................... 70
16. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) ..................................................... 71
Mar. 2005 Ver 0.2
MC80F0104/0204
Preliminary
UART Serial Interface Functions .................................................................................................................. 71
Serial Interface Configuration ....................................................................................................................... 72
Communication operation ............................................................................................................................. 76
Relationship between main clock and baud rate .......................................................................................... 77
17. BUZZER FUNCTION ................................................................................................................................... 78
18. INTERRUPTS .............................................................................................................................................. 80
Interrupt Sequence ....................................................................................................................................... 82
BRK Interrupt ................................................................................................................................................ 84
Multi Interrupt ................................................................................................................................................ 84
External Interrupt .......................................................................................................................................... 86
19. POWER SAVING OPERATION .................................................................................................................. 88
Sleep Mode ................................................................................................................................................... 88
Stop Mode ..................................................................................................................................................... 89
Stop Mode at Internal RC-Oscillated Watchdog Timer Mode ....................................................................... 92
Minimizing Current Consumption .................................................................................................................. 94
20. RESET ......................................................................................................................................................... 96
21. POWER FAIL PROCESSOR ....................................................................................................................... 98
22. COUNTERMEASURE OF NOISE ............................................................................................................. 100
Oscillation Noise Protector .......................................................................................................................... 100
Oscillation Fail Processor ........................................................................................................................... 101
23. Device Configuration Area ...................................................................................................................... 102
24. MASK Option (MC80C0104/0204) ........................................................................................................... 103
25. Emulator EVA. Board Setting ................................................................................................................ 104
26. IN-SYSTEM PROGRAMMING (ISP) ......................................................................................................... 107
Getting Started / Installation ........................................................................................................................ 107
Basic ISP S/W Information .......................................................................................................................... 107
Hardware Conditions to Enter the ISP Mode .............................................................................................. 109
Reference ISP Circuit Diagram and MagnaChip Supplied ISP Board ........................................................ 110
27. A. INSTRUCTION MAP .................................................................................................................................. i
28. B. INSTRUCTION SET .................................................................................................................................. ii
1. arithmetic/ logic operation ............................................................................................................................ii
2. REGISTER / MEMORY OPERATION ........................................................................................................iv
3. 16-BIT operation ..........................................................................................................................................v
4. BIT MANIPULATION ...................................................................................................................................v
5. BRANCH / JUMP OPERATION ..................................................................................................................vi
6. CONTROL OPERATION & etc. ................................................................................................................. vii
29. MASK ORDER SHEET .................................................................................................................................. 1
30. MASK ORDER SHEET .................................................................................................................................. 2
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
MC80F0104/0204
MC80C0104/0204
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 10-BIT A/D CONVERTER AND UART
1. OVERVIEW
1.1 Description
The MC80F0104/0204 is advanced CMOS 8-bit microcontroller with 4K bytes of FLASH. This is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. This provides the
following features : 4K bytes of FLASH, 256 bytes of RAM, 8/16-bit timer/counter, watchdog timer, 10-bit A/D converter,
8-bit Serial Input/Output, UART, buzzer driving port, 10-bit PWM output and on-chip oscillator and clock circuitry. It also
has ONP, noise filter, PFD for improving noise immunity. In addition, the MC80F0104/0204 supports power saving modes
to reduce power consumption.
The MC80C0104/0204 is the MASK ROM version of the MC80F0104/0204. It is fully compatible to the MC80F0104/0204
in function.
This document explains the base MC80F0204, the other’s eliminated functions are same as below table.
Device Name
FLASH
MASK ROM
MC80F0204
MC80C0204
MC80F0104
MC80C0104
FLASH (ROM)
Size
RAM
4KB
256B
ADC
I/O PORT
Package
10 channel
18 port
20 PDIP, 20SOP
8 channel
14 port
16 PDIP, 16 SOP
1.2 Features
• 4K Bytes On-chip FLASH
- Endurance : 100 times
- Retention time : 10 years
• 256 Bytes On-chip Data RAM
(Included stack memory)
• Minimum Instruction Execution Time:
- 333ns at 12MHz (NOP instruction)
• Programmable I/O pins
(LED direct driving can be a source and sink)
- MC80F0204 : 18(17)
- MC80F0104 : 14(13)
• One 8-bit Basic Interval Timer
• Four 8-bit Timer/counters
(or two 16-bit Timer/counter)
• One Watchdog timer
• Two 10-bit High Speed PWM Outputs
• 10-bit A/D converter
- MC80F0204 : 10 channels
- MC80F0104 : 8 channels
Mar. 2005 Ver 0.2
• Two 8-bit Serial Communication Interface
- One Serial I/O and one UART
• One Buzzer Driving port
- 488Hz ~ [email protected]
• Four External Interrupt input ports
• On-chip POR (Power on Reset)
• Fourteen Interrupt sources
- External input : 4
- Timer : 6
- A/D Conversion : 1
- Serial Interface : 1
- UART : 2
• Built in Noise Immunity Circuit
- Noise Canceller
- PFD (Power fail detector)
- ONP (Oscillation Noise Protector)
• Operating Voltage & Frequency (MC80F0104/
0204)
- 2.7V ~ 5.5V (at 0.4 ~ 8MHz)
- 4.5V ~ 5.5V (at 0.4 ~ 12MHz)
1
MC80F0104/0204
Preliminary
• Operating Voltage & Frequency(MC80C0104/
0204)
- 2.0V ~ 5.5V (at 0.4 ~ 4.2MHz)
- 2.7V ~ 5.5V (at 0.4 ~ 8MHz)
- 4.5V ~ 5.5V (at 0.4 ~ 12MHz)
• Operating Temperature : -40°C ~ 85°C
• Power Saving Modes
- STOP mode
- SLEEP mode
- RC-WDT mode
• Oscillator Type
- Crystal
- Ceramic resonator
- External RC Oscillator (C can be omitted)
- Internal Oscillator (4MHz/2MHz)
1.3 Development Tools
The MC80F0104/0204 is supported by a full-featured macro assembler, an in-circuit emulator CHOICE-Dr.TM and OTP programmers. There are two different type of programmers such as
single type and gang type. For mode detail, Macro assembler operates under the MS-Windows 95 and upversioned Windows OS.
Please contact sales part of MagnaChip semiconductor.
Software
Hardware
(Emulator)
FLASH Writer
- MS-Windows based assembler
- MS-Windows based Debugger
- HMS800 C compiler
- CHOICE-Dr.
- CHOICE-Dr. EVA80C0x B/D
- CHOICE - SIGMA I/II(Single writer)
- PGM Plus I/II/III(Single writer)
- Standalone GANG4 I/II(Gang writer)
PGMplus III ( Single Writer )
Standalone Gang4 II ( Gang Writer )
Choice-Dr. (Emulator)
2
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
1.4 Ordering Information
Device name
ROM Size
Mask version
MC80C0204B
MC80C0204D
MC80C0104B
MC80C0104D
4K bytes
4K bytes
4K bytes
4K bytes
FLASH version
MC80F0204B
MC80F0204D
MC80F0104B
MC80F0104D
4K bytes FLASH
4K bytes FLASH
4K bytes FLASH
4K bytes FLASH
Mar. 2005 Ver 0.2
RAM size
Package
256 bytes
20PDIP
20SOP
16PDIP
16SOP
256 bytes
20PDIP
20SOP
16PDIP
16SOP
3
MC80F0104/0204
Preliminary
2. BLOCK DIAGRAM
PSW
Accumulator
ALU
PC
Stack Pointer
Data
Memory
RESET
Program
Memory
System controller
8-bit Basic
Interval
Timer
System
Clock Controller
Timing generator
Data Table
Interrupt Controller
Clock Generator
Instruction
Decoder
Watch-dog
Timer
SIO/UART
VDD
VSS
R3
10-bit
A/D
Converter
8-bit
Timer/
Counter
R0
High
Speed
PWM
Buzzer
Driver
R1
Power
Supply
R31 / AN14
R32 / AN15
XIN / R33
XOUT / R34
4
R00 / INT3 / SCK
R01 / AN1 / SI
R02 / AN2 / SOUT
R03 / AN3 / INT2
R04 / AN4 / EC0 / RXD
R05 / AN5 / T0O / TXD
R06 / AN6 / T2O / ACLK
R07 / AN7 / EC1
R10 / AN0 / AVREF / PWM1O
R11 / INT0 / PWM3O
R12 / INT1 / BUZO
R13
R14
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
3. PIN ASSIGNMENT
MC80F0204B/0204D
20 PDIP
20 SOP
1
20
R03 / AN3 / INT2
R05 / AN5 / T0O / TXD
2
19
R02 / AN2 / SOUT
R06 / AN6 / T2O / ACLK
3
18
R01 / AN1 / SI
R07 / AN7 / EC1
4
17
R00 / INT3 / SCK
VDD
5
16
VSS
R10 / AN0 / AVREF / PWM1O
6
15
RESET / R35
R11 / INT0 / PWM3O
7
14
XOUT / R34
R12 / INT1 / BUZO
8
13
XIN / R33
R13
9
12
R32 / AN15
R14
10
11
R31 / AN14
MC80F0204B/0204D
R04 / AN4 / EC0 / RXD
MC80F0104B/0104D
16 PDIP
16 SOP
1
20
R03 / AN3 / INT2
R05 / AN5 / T0O / TXD
2
19
R02 / AN2 / SOUT
R06 / AN6 / T2O / ACLK
3
18
R01 / AN1 / SI
R07 / AN7 / EC1
4
17
R00 / INT3 / SCK
VDD
5
16
VSS
R10 / AN0 / AVREF / PWM1O
6
15
RESET / R35
R11 / INT0 / PWM3O
7
14
XOUT / R34
R12 / INT1 / BUZO
8
13
XIN / R33
MC80F0104B/0104D
Mar. 2005 Ver 0.2
R04 / AN4 / EC0 / RXD
5
MC80F0104/0204
Preliminary
4. PACKAGE DRAWING
20 PDIP
unit: inch
MAX
MIN
1.043
TYP 0.300
1.010
0.245
0.120
0.140
MAX 0.180
MIN 0.015
0.270
4
0.01
8
0
0
0.
0.021
0.065
0.015
0 ~ 15°
TYP 0.100
0.050
6
TYP 0.050
0.291
0.419
0.398
0.0091
0.020
0.013
0.0125
0.104
0.093
0.5118
0.4961
0.0118
0.004
0.299
20 SOP
0.042
0.016
0 ~ 8°
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
16 PDIP
unit: inch
MAX
MIN
TYP 0.300
0.765
0.260
MIN 0.015
0.240
0.120
0.140
MAX 0.180
0.745
0.022
0.065
0.015
0 ~ 15°
TYP 0.100
4
0.01
8
0.00
0.050
Mar. 2005 Ver 0.2
TYP 0.050
0.292
0.416
0.398
0.0091
0.019
0.014
0.0125
0.104
0.094
0.412
0.402
0.0118
0.004
0.299
16 SOP
0.040
0.016
0 ~ 8°
7
MC80F0104/0204
Preliminary
5. PIN FUNCTION
R10~R14: R1 is a 5-bit, CMOS, bidirectional I/O port. R1
pins can be used as outputs or inputs according to “1” or
“0” written the their Port Direction Register (R1IO).
VDD: Supply voltage.
VSS: Circuit ground.
RESET: Reset the MCU.
XIN: Input to the inverting oscillator amplifier and input to
the internal main clock operating circuit.
XOUT: Output from the inverting oscillator amplifier.
R00~R07: R0 is an 8-bit, CMOS, bidirectional I/O port.
RA pins can be used as outputs or inputs according to “1”
or “0” written the their Port Direction Register(R0IO).
Port pin
Alternate function
R00
INT3 ( External Interrupt Input Port3 )
SCK ( SPI CLK )
AN1 ( Analog Input Port 1 )
SI ( SPI Serial Data Input )
AN2 ( Analog Input Port 2 )
SOUT ( SPI Serial Data Output )
AN3 ( Analog Input Port 3 )
INT2 ( External Interrupt Input Port2 )
AN4 ( Analog Input Port 4 )
EC0 ( Event Counter Input Source 0 )
RXD ( UART Data Input )
AN5 ( Analog Input Port 5 )
T0O (Timer0 Clock Output )
TXD ( UART Data Output )
AN6 ( Analog Input Port 6 )
T2O (Timer2 Clock Output )
ACLK ( UART Clock Input )
AN7 ( Analog Input Port 7 )
EC1 ( Event Counter Input Source 1 )
R01
R02
R03
R04
R05
R06
R07
R1 serves the functions of the various following special
features in Table 5-2
Port pin
Alternate function
R10
AN0 ( Analog Input Port 0 )
AVref ( External Analog Reference Pin )
PWM1O ( PWM1 Output )
INT0 ( External Interrupt Input Port 0 )
PWM3O ( PWM3 Output )
INT1 ( External Interrupt Input Port 1 )
BUZ ( Buzzer Driving Output Port )
R11
R12
R13
R14
Table 5-2 R1 Port
R31~R34: R3 is an 4-bit, CMOS, bidirectional I/O port.
R3 pins can be used as outputs or inputs according to “1”
or “0” written the their Port Direction Register (R3IO).
R3 serves the functions of the serial interface following
special features in Table 5-3 .
Port pin
R31
R32
R33
R34
R35
Alternate function
AN14 ( Analog Input Port 14 )
AN15 ( Analog Input Port 15 )
XIN ( Oscillation Input )
XOUT ( Oscillation Output )
RESET ( Reset input port )
Table 5-1 R0 Port
Table 5-3 R3 Port
In addition, R0 serves the functions of the various special
features in Table 5-1 .
8
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
Pin No.
(20PDIP)
In/Out
VDD
5
-
Supply voltage
VSS
16
-
Circuit ground
RESET (R35)
15
I(I)
Reset signal input
Input only port
XIN (R33)
13
I (I/O)
Oscillation Input
Normal I/O Port
XOUT (R34)
14
O (I/O)
Oscillation Output
Normal I/O Port
R00 (INT3 / SCK)
17
I/O (Input / I/O)
External Interrupt Input3 / SPI clock Input/Output
R01 (AN1 / SI)
18
I/O (Input/Input)
Analog Input Port 1 / SPI Data Input
R02 (AN2 / SOUT)
19
I/O (Input/Output)
R03 (AN3 / INT2)
20
I/O (Input/Input)
Analog Input Port 3 / External Interrupt Input2
R04 (AN4 / EC0 / RXD)
1
I/O (Input/Input/Input)
Analog Input Port 4 / Event Counter Input 0 /
UART Data Input
R05 (AN5 / T0O / TXD)
2
I/O (Input/Output/Output)
Analog Input Port 5 / Timer0 Output / UART
Data Output
R06 (AN6 / T2O / ACLK)
3
I/O (Input/Output/Input)
Analog Input Port 6 / Timer2 Output / UART
Clock Input
R07 (AN7 / EC1)
4
I/O (Input/Input)
R10 (AN0 / AVREF /
PWM1O)
6
I/O (Input/Input/Output)
R11 (INT0 / PWM3O)
7
I/O (Input/Output)
External Interrupt Input 0
R12 (INT1 / BUZO)
8
I/O (Input/Output)
External Interrupt Input 1 / Buzzer Driving Output
R13
9
I/O
-
R14
10
I/O
-
R31 (AN14)
11
I/O (Input)
Analog Input Port 14
R32 (AN15)
12
I/O (Input)
Analog Input Port 15
PIN NAME
Function
Analog Input Port 2 / SPI Data Output
Normal I/O Ports
Analog Input Port 7 / Event Counter Input 1
Analog Input Port 0 / Analog Reference / PWM 1
output
Table 5-4 Pin Description
Mar. 2005 Ver 0.2
9
MC80F0104/0204
Preliminary
6. PORT STRUCTURES
R13~R14
R01 (AN1 / SI)
VDD
VDD
Pull-up
Reg.
Pull-up
Tr.
Pull-up
Reg.
Pull-up
Tr.
Open Drain
Reg.
Open Drain
Reg.
VDD
VDD
Direction
Reg.
Pin
Pin
Data Bus
VSS
MUX
VSS
VSS
VDD
Data Reg.
Data Reg.
Direction
Reg.
VDD
VSS
RD
Data Bus
MUX
AN[1]
RD
ADEN & ADS[3:0]
(ADCM)
Noise
Filter
SI
SI_EN (SIOM)
R31 (AN14), R32 (AN15)
R03 (AN3 / INT2), R07 (AN7 / EC1)
VDD
VDD
Pull-up
Tr.
Pull-up
Reg.
Open Drain
Reg.
VDD
Open Drain
Reg.
VDD
Data Reg.
Pin
VSS
ADEN & ADS[3:0] (ADCM)
VDD
VSS
Direction
Reg.
Data Bus
Pin
MUX
VSS
VSS
RD
MUX
RD
AN[15:14]
VDD
Data Reg.
Direction
Reg.
Data Bus
Pull-up
Tr.
Pull-up
Reg.
AN[3, 7]
ADEN & ADS[3:0]
(ADCM)
INT2, EC1
Noise
Filter
INT2E (PSR0.2), EC1E (PSR0.5)
10
Mar. 2005 Ver 0.2
Preliminary
R04 (AN4 / EC0 / RXD)
MC80F0104/0204
R02 (AN2 / SOUT)
VDD
VDD
Pull-up
Tr.
Pull-up
Reg.
Open Drain
Reg.
VDD
Open Drain
Reg.
VDD
Data Reg.
Data Reg.
Direction
Reg.
Data Bus
Pin
VDD
VDD
MUX
SOUT
Pin
SO_EN(SIOM)
VSS
VSS
MUX
Pull-up
Tr.
Pull-up
Reg.
RD
VSS
VSS
Direction
Reg.
Data Bus
MUX
AN[1]
RD
ADEN & ADS[3:0]
(ADCM)
Noise
Filter
EC0
EC0E (PSR0)
AN[2]
ADEN & ADS[3:0]
(ADCM)
SOUT(SI)
Noise
Filter
RXD
RXE (ASIMR)
Noise
Filter
SO_OUT_EN (SIOM)
R11 (INT0 / PWM3O), R12 (INT1 / BUZO)
R00 (INT3 / SCK)
VDD
VDD
Pull-up
Tr.
Pull-up
Reg.
Open Drain
Reg.
Data Reg.
VDD
Pull-up
Tr.
Pull-up
Reg.
Open Drain
Reg.
VDD
VDD
Data Reg.
MUX
MUX
SCK
PWM3O, BUZO
Pin
PWM3OE(PSR0.7)
BUZOE(PSR1.2)
VSS
Direction
Reg.
Pin
SCKO_EN(SIOM)
VSS
VSS
Direction
Reg.
Data Bus
Data Bus
VDD
VSS
MUX
MUX
RD
RD
INT0,INT1
INT0E(PSR0.0)
INT1E(PSR0.1)
Noise
Filter
SCK
Noise
Filter
SCK_EN(SIOM)
INT3
Noise
Filter
INT3E(PSR0.3)
Mar. 2005 Ver 0.2
11
MC80F0104/0204
Preliminary
R06 (AN6 / T2O / ACLK)
R05 (AN5 / T0O / TXD)
VDD
Pull-up
Reg.
Open Drain
Reg.
Data Reg.
VDD
Pull-up
Tr.
VDD
Open Drain
Reg.
VDD
Data Reg.
MUX
T2O
Pin
T2OE(PSR1.1)
VSS
VSS
Direction
Reg.
Pull-up
Tr.
Pull-up
Reg.
VDD
T0O
TXD
T0OE(PSR1.0)
TXE(ASIMR.7)
MUX
Pin
VSS
Direction
Reg.
Data Bus
Data Bus
MUX
VDD
MUX
RD
VSS
MUX
RD
AN[6]
AN[5]
ADEN & ADS[3:0]
(ADCM)
ACLK
ADEN & ADS[3:0]
(ADCM)
Noise
Filter
TPS[2:0](BRGCR[6:4])
RESET
R10 (AN0 / AVREF / PWM1O)
VDD
Pull-up
Tr.
Pull-up
Reg.
Open Drain
Reg.
Data Reg.
VDD
VDD
Pull-up
Tr.
Pull-up
Reg.
VDD
VDD
RD
Mask only
MUX
PWM1O
Pin
PWM1OE(PSR0.6)
Data Bus
Pin
Internal Reset
VSS
Direction
Reg.
VSS
Reset Disable
(Configuration option bit)
Data Bus
VSS
MUX
RD
AN[0]
ADEN & ADS[3:0]
(ADCM)
ADC Reference
Voltage Input
VDD
MUX
AVREFS(PSR1.3)
12
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
R33 (XIN), R34 (XOUT)
XIN, XOUT (Crystal or Ceramic Resonator)
VDD
VDD
VDD
XIN
STOP
Pull-up
Tr.
Pull-up
Reg.
Open Drain
Reg.
VDD
VDD
Data Reg.
VSS
Direction
Reg.
VDD
VDD
XIN
/ R33
VSS
MAIN
CLOCK
VSS
XOUT
Data Bus
VSS
IN4MCLK
IN2MCLK
IN4MCLKXO
IN2MCLKXO
CLOCK option
(Configuration
option bit)
XIN, XOUT (External RC or R oscillation)
MUX
RD
IN4MCLK
IN2MCLK
EXRC
VDD
Main Clock
(to ONP Block)
VDD
XIN
STOP
VDD
Pull-up
Tr.
Pull-up
Reg.
Open Drain
Reg.
VSS
VDD
VDD
Data Reg.
MAIN
CLOCK
VDD
Direction
Reg.
XOUT
/ R34
fXIN ÷ 4
XOUT
VSS
VSS
Data Bus
VSS
MUX
RD
System Clock ÷ 4
IN4MCLKXO
IN2MCLKCO
EXRCXO
CLOCK option
(Configuration option bit)
Mar. 2005 Ver 0.2
13
MC80F0104/0204
Preliminary
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage ............................................. -0.3 to +6.5 V
................................................................................. 10 mA
Storage Temperature .................................. -65 to +150 °C
Maximum current (ΣIOL) ...................................... 160 mA
Voltage on any pin with respect to Ground (VSS)
...............................................................-0.3 to VDD+0.3V
Maximum current (ΣIOH)........................................ 80 mA
Maximum current out of VSS pin .......................... 200 mA
Note: Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Maximum current into VDD pin ............................ 100 mA
Maximum current sunk by (IOL per I/O Pin) .......... 20 mA
Maximum output current sourced by (IOH per I/O Pin)
7.2 Recommended Operating Conditions
Parameter
Symbol
Condition
Min.
Max.
Unit
Supply Voltage
VDD
fXIN=0.4~12MHz
fXIN=0.4~8MHz
4.5
2.5
5.5
5.5
V
Operating Frequency
fXIN
VDD=4.5~5.5V
VDD=2.7~5.5V(MC80F0X04)
VDD=2.0~5.5V(MC80C0X04)
0.4
0.4
0.4
12
8
4.2
MHz
TOPR
VDD=2.7~5.5V(MC80F0X04)
VDD=2.0~5.5V(MC80C0X04)
-40
85
°C
Operating Temperature
7.3 A/D Converter Characteristics
(Ta=-40~85°C, VSS=0V, VDD=2.7~5.5V @fXIN=8MHz)
Parameter
Symbol
Resolution
Overall Accuracy
Integral Linearity Error
-
DLE
Offset Error of Top
EOT
Offset Error of Bottom
EOB
Analog Input Voltage
Analog Reference Voltage
Analog Input Current
Analog Block Current
14
Min.
Typ.
Max.
Unit
-
-
10
-
BIT
-
-
-
±3
LSB
-
−
±3
LSB
-
−
±3
LSB
-
±1
±3
LSB
-
±0.5
±3
LSB
ILE
Differential Linearity Error
Conversion Time
Conditions
VDD = AVREF = 5V
CPU Clock = 10MHz
VSS = 0V
TCONV
-
13
-
-
µS
VAIN
-
VSS
-
VDD
(AVREF)
V
AVREF
-
TBD
-
VDD
V
IAIN
VDD = AVREF = 5V
-
-
10
µA
VDD = AVREF = 5V
VDD = AVREF = 3V
-
1
0.5
3
1.5
mA
VDD = AVREF = 5V
power down mode
-
100
500
nA
IAVDD
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
7.4 DC Electrical Characteristics
(TA=-40~85°C, VDD=5.0V, VSS=0V),
Parameter
Symbol
Pin
Condition
Specifications
Min.
Typ.
Max.
Unit
VIH1
XIN, RESET
0.8 VDD
-
VDD
VIH2
Hysteresis Input1
0.8 VDD
-
VDD
VIH3
Normal Input
0.7 VDD
-
VDD
VIL1
XIN, RESET
0
-
0.2 VDD
VIL2
Hysteresis Input1
0
-
0.2 VDD
VIL3
Normal Input
0
-
0.3 VDD
Output High Voltage
VOH
All Output Port
VDD=5V, IOH=-5mA
VDD -1
-
-
V
Output Low Voltage
VOL
All Output Port
VDD=5V, IOL=10mA
-
-
1
V
Input Pull-up Current
IP
Normal Input
VDD=5V
-70
-
-130
µA
Input High Voltage
Input Low Voltage
V
V
Input High
Leakage Current
IIH1
All Pins (except XIN)
VDD=5V
-
-
5
µA
IIH2
XIN
VDD=5V
-
-
15
µA
Input Low
Leakage Current
IIL1
All Pins (except XIN)
VDD=5V
-5
-
-
µA
IIL2
XIN
VDD=5V
-15
-
-
µA
VDD=5V
0.5
-
-
V
2.0
-
3.0
V
Hysteresis
| VT |
Hysteresis
PFD Voltage
VPFD
VDD
POR Voltage
VPOR
VDD
POR Start Voltage2
VSTART
VDD
POR Rising Time2
TRISE
VDD
Internal RC WDT
Period
TRCWDT
XOUT
VDD=5.5V
Operating Current
IDD
VDD
Wake-up Timer
Mode Current
IWKUP
RCWDT Mode
Current at STOP
Mode
Input1
2.4
0
V
TBD
V
TBD
V/ms
36
-
90
µS
VDD=5.5V, fXIN=12MHz
-
6
9
mA
VDD
VDD=5.5V, fXIN=12MHz
-
1
2
mA
IRCWDT
VDD
VDD=5.5V
-
20
50
µA
Stop Mode Current
ISTOP
VDD
VDD=5.5V, fXIN=12MHz
-
0.7
1.6
µA
Internal Oscillation
Frequency
fIN_CLK
XOUT
VDD=5V
3
4
5
MHz
VDD=5V
1.5
1.8
µs
RESET Input Noise
Cancel Time
External RC
Oscillator Frequency
TRST_NC RESET
fRC-OSC
fXOUT = fRC-OSC ÷ 4
VDD=5.5V
R=30kΩ, C=10pF
TBD
MHz
fR-OSC
fXOUT = fR-OSC ÷ 4
VDD=5.5V, R=30kΩ
TBD
MHz
1. Hysteresis Input: INT0 ~INT3(R11,R12,R03,R00),SIO(R00,R01,R02),UART(R04,R06),EC0,EC1
2. VSTART and TRiSE parameter is presented for design guidance only and not tested or guaranteed.
Mar. 2005 Ver 0.2
15
MC80F0104/0204
Preliminary
7.5 AC Characteristics
(TA=-40~+85°C, VDD=5V±10%, VSS=0V)
Parameter
Symbol
Pins
fCP
Specifications
Unit
Min.
Typ.
Max.
XIN
1
-
8
MHz
tCPW
XIN
50
-
-
nS
tRCP,tFCP
XIN
-
-
20
nS
Oscillation Stabilizing Time
tST
XIN, XOUT
-
-
20
mS
External Input Pulse Width
tEPW
INT0, INT1, INT2, INT3
EC0, EC1
2
-
-
tSYS
RESET Input Width
tRST
RESET
8
-
-
tSYS
Operating Frequency
External Clock Pulse Width
External Clock Transition Time
tCPW
1/fCP
tCPW
VDD-0.5V
XIN
0.5V
tSYS
tRCP
tFCP
tRST
RESET
0.2VDD
tEPW
tEPW
0.8VDD
INT0, INT1
INT2, INT3
EC0, EC1
0.2VDD
Figure 7-1 Timing Chart
16
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
7.6 Typical Characteristics
These graphs and tables provided in this section are for design guidance only and are not tested or guaranteed.
In some graphs or tables the data presented are outside specified operating range (e.g. outside specified
VDD range). This is for information only and devices
are guaranteed to operate properly only within the
specified range.
The data presented in this section is a statistical summary
of data collected on units from different lots over a period
of time. “Typical” represents the mean of the distribution
while “max” or “min” represents (mean + 3σ) and (mean −
3σ) respectively where σ is standard deviation
TBD
Mar. 2005 Ver 0.2
17
MC80F0104/0204
Preliminary
8. MEMORY ORGANIZATION
The MC80F0104/0204 has separate address spaces for
Program memory and Data Memory. 4K bytes program
memory can only be read, not written to.
Data memory can be read and written to up to 256 bytes including the stack area.
8.1 Registers
This device has six registers that are the Program Counter
(PC), a Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.
PCH
A
ACCUMULATOR
X
X REGISTER
Y
Y REGISTER
SP
STACK POINTER
PCL
PROGRAM COUNTER
PSW
PROGRAM STATUS WORD
call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost.
The stack can be located at any position within 1C0H to
1FFH of the internal data memory. The SP is not initialized
by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of “FFH” is
used.
Bit 15
Stack Address (1C0H ~ 1FFH)
8 7
Bit 0
01H
SP
C0H~FFH
Hardware fixed
Figure 8-1 Configuration of Registers
Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc.
Note: The Stack Pointer must be initialized by software because
its value is undefined after Reset.
The Accumulator can be used as a 16-bit register with Y
Register as shown below.
Example: To initialize the SP
LDX
#0FFH
TXSP
Y
Y
A
A
Two 8-bit Registers can be used as a “YA” 16-bit Register
Figure 8-2 Configuration of YA 16-bit Register
X, Y Registers: In the addressing mode which uses these
index registers, the register contents are added to the specified address, which becomes the actual address. These
modes are extremely effective for referencing subroutine
tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators.
Stack Pointer: The Stack Pointer is an 8-bit register used
for occurrence interrupts and calling out subroutines. Stack
Pointer identifies the location in the stack to be accessed
(save or restore).
Generally, SP is automatically updated when a subroutine
18
; SP ← FFH
Program Counter: The Program Counter is a 16-bit wide
which consists of two 8-bit registers, PCH and PCL. This
counter indicates the address of the next instruction to be
executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH).
Program Status Word: The Program Status Word (PSW)
contains several bits that reflect the current state of the
CPU. The PSW is described in Figure 8-3 . It contains the
Negative flag, the Overflow flag, the Break flag the Half
Carry (for BCD operation), the Interrupt enable flag, the
Zero flag, and the Carry flag.
[Carry flag C]
This flag stores any carry or borrow from the ALU of CPU
after an arithmetic operation and is also changed by the
Shift Instruction or Rotate Instruction.
[Zero flag Z]
This flag is set when the result of an arithmetic operation
or data transfer is “0” and is cleared by any other result.
Mar. 2005 Ver 0.2
Preliminary
PSW
MSB
N V G B H
NEGATIVE FLAG
OVERFLOW FLAG
SELECT DIRECT PAGE
when G=1, page is selected to “page 1”
BRK FLAG
I
Z
MC80F0104/0204
LSB
C RESET VALUE: 00H
CARRY FLAG RECEIVES
CARRY OUT
ZERO FLAG
INTERRUPT ENABLE FLAG
HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS
Figure 8-3 PSW (Program Status Word) Register
[Interrupt disable flag I]
This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All interrupts are disabled when cleared to “0”. This flag immediately becomes “0” when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.
[Half carry flag H]
After operation, this is set when there is a carry from bit 3
of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).
[Break flag B]
This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector address.
[Direct page flag G]
Mar. 2005 Ver 0.2
This flag assigns RAM page for direct addressing mode. In
the direct addressing mode, addressing area is from zero
page 00H to 0FFH when this flag is "0". If it is set to "1",
addressing area is assigned 100H to 1FFH. It is set by
SETG instruction and cleared by CLRG.
[Overflow flag V]
This flag is set to “1” when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction exceeds +127(7FH) or -128(80H). The CLRV instruction
clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.
[Negative flag N]
This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
19
MC80F0104/0204
Preliminary
At acceptance
of interrupt
At execution of
a CALL/TCALL/PCALL
01FF
Push
down
01FF
PCH
01FE
PCL
01FD
01FD
PSW
01FC
01FC
01FE
PCH
PCL
At execution
of RET instruction
Push
down
01FF
PCH
01FE
PCL
At execution
of RET instruction
01FF
PCH
01FE
PCL
01FD
01FD
PSW
01FC
01FC
Pop
up
SP before
execution
01FF
01FF
01FD
01FC
SP after
execution
01FD
01FC
01FF
01FF
At execution
of PUSH instruction
PUSH A (X,Y,PSW)
01FF
A
01FE
Push
down
Pop
up
At execution
of POP instruction
POP A (X,Y,PSW)
01FF
A
01FE
01FD
01FD
01FC
01FC
Pop
up
01C0H
Stack
depth
01FFH
SP before
execution
01FF
01FE
SP after
execution
01FE
01FF
Figure 8-4 Stack Operation
20
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
8.2 Program Memory
A 16-bit program counter is capable of addressing up to
64K bytes, but this device has 4K bytes program memory
space only physically implemented. Accessing a location
above FFFFH will cause a wrap-around to 0000H.
Figure 8-5 , shows a map of Program Memory. After reset,
the CPU begins execution from reset vector which is stored
in address FFFEH and FFFFH as shown in Figure 8-6 .
As shown in Figure 8-5 , each area is assigned a fixed location in Program Memory. Program Memory area contains the user program
FFC0H
FFDFH
FFE0H
FFFFH
TCALL area
Interrupt
Vector Area
MC80F0104/0204, 4K FLASH
FEFFH
FF00H
PCALL area
F000H
Example: Usage of TCALL
LDA
#5
TCALL 0FH
:
:
;1BYTE INSTRUCTION
;INSTEAD OF 3 BYTES
;NORMAL CALL
;
;TABLE CALL ROUTINE
;
FUNC_A: LDA
LRG0
RET
;
FUNC_B: LDA
LRG1
2
RET
;
;TABLE CALL ADD. AREA
;
ORG
0FFC0H
DW
FUNC_A
DW
FUNC_B
1
;TCALL ADDRESS AREA
The interrupt causes the CPU to jump to specific location,
where it commences the execution of the service routine.
The External interrupt 0, for example, is assigned to location 0FFFCH. The interrupt service locations spaces 2-byte
interval: 0FFFAH and 0FFFBH for External Interrupt 1,
0FFFCH and 0FFFDH for External Interrupt 0, etc.
Any area from 0FF00H to 0FFFFH, if it is not going to be
used, its service location is available as general purpose
Program Memory.
Figure 8-5 Program Memory Map
Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called,
it is more useful to save program byte length.
Table Call (TCALL) causes the CPU to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0H for TCALL15, 0FFC2H for
TCALL14, etc., as shown in Figure 8-7 .
Address
0FFE0H
Vector Area Memory
Basic Interval Timer
E2
Watchdog Timer Interrupt
E4
A/D Converter
E6
-
E8
Timer/Counter 3 Interrupt
EA
Timer/Counter 2 Interrupt
EC
Timer/Counter 1 Interrupt
EE
Timer/Counter 0 Interrupt
F0
Serial Input/Output (SIO)
F2
UART Tx interrupt
F4
UART Rx interrupt
F6
External Interrupt 3
F8
External Interrupt 2
FA
External Interrupt 1
FC
External Interrupt 0
FE
RESET
Figure 8-6 Interrupt Vector Area
Mar. 2005 Ver 0.2
21
MC80F0104/0204
Preliminary
Address
0FF00H
PCALL Area Memory
Address
PCALL Area
(256 Bytes)
0FFC0H
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
0FFFFH
Program Memory
TCALL 15
TCALL 14
TCALL 13
TCALL 12
TCALL 11
TCALL 10
TCALL 9
TCALL 8
TCALL 7
TCALL 6
TCALL 5
TCALL 4
TCALL 3
TCALL 2
TCALL 1
TCALL 0 / BRK *
NOTE:
* means that the BRK software interrupt is using
same address with TCALL0.
Figure 8-7 PCALL and TCALL Memory Area
PCALL→ rel
TCALL→ n
4F35
4A
PCALL 35H
TCALL 4
4A
4F
35
~
~
~
~
~
~
0D125H
01001010
➊
~
~
NEXT
Reverse
PC: 11111111 11010110
FH
FH
DH 6H
0FF00H
0FF35H
0FFFFH
22
NEXT
➌
0FF00H
0FFD6H
25
0FFD7H
D1
➋
0FFFFH
Mar. 2005 Ver 0.2
Preliminary
Example: The usage software example of Vector address
;Interrupt Vector Table
ORG
0FFE0H
DW
BIT_TIMER
DW
WDT
DW
ADC
DW
Not_used
DW
TIMER3
DW
TIMER2
DW
TIMER1
DW
TIMER0
DW
SIO
DW
TX
DW
RX
DW
INT3
DW
INT2
DW
INT1
DW
INT0
DW
RESET
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
MC80F0104/0204
for MC80F0204.
BIT
WDT
AD Converter
Timer-3
Timer-2
Timer-1
Timer-0
Serial Interface
UART Tx
UART Rx
Ext Int.3
Ext Int.2
Ext Int.1
Ext Int.0
Reset
ORG
0F000H
; 4K bytes ROM Start address
;*******************************************
;
MAIN
PROGRAM
*
;*******************************************
RESET:
DI
;Disable All Interrupt
;RAM Clear Routine
LDX
#0
RAM_Clear0:
LDA
#0
;Page0 RAM Clear(0000h ~ 00BFh)
STA
{X}+
CMPX
#0C0h
BNE
RAM_Clear0
RAM_Clear1:
LDM
SETG
RPR,#1
LDX
#0C0h
LDA
STA
CMPX
BNE
#0
{X}+
#00h
RAM_Clear1
RAM_Clear_Finish:
CLRG
LDX
TXSP
:
:
;Initialize IO
LDM
LDM
:
:
Mar. 2005 Ver 0.2
;Page Select
;Page0 Select
#0FFh
;Initial Stack Pointer
R0, #0
R0IO,#0FFH
;Normal Port R0
;Normal Port R0 Direction
23
MC80F0104/0204
Preliminary
8.3 Data Memory
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The control registers are in
address range of 0C0H to 0FFH.
Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into three groups, a user
RAM, control registers, and Stack memory.
Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
0000H
User Memory
(192Bytes)
More detailed informations of each register are explained
in each peripheral section.
PAGE0
00BFH
00C0H
(When “G-flag=0”,
this page0 is selected)
Control
Registers
00FFH
0100H
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte
manipulation instruction, for example “LDM”.
Not Available
PAGE1
01BFH
01C0H
Example; To write at CKCTLR
LDM
User Memory
or Stack Area
(64Bytes)
01FFH
Stack Area
The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.
Figure 8-8 Data Memory Map
User Memory
When returning from the processing routine, executing the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; executing the interrupt
return instruction [RETI] restores the contents of the program counter and flags.
The MC80F0104/0204 has 256 × 8 bits for the user memory (RAM). RAM pages are selected by RPR (See Figure
8-9 ).
Note: After setting RPR(RAM Page Select Register), be sure to
execute SETG instruction. When executing CLRG instruction, be
selected PAGE0 regardless of RPR.
The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save. Refer to Figure 8-4 on page 20.
Control Registers
The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
RPR
CKCTLR,#0AH ;Divide ratio(÷32)
7
6
5
4
3
R/W
2
R/W
1
R/W
0
-
-
-
-
-
RPR2 RPR1 RPR0
ADDRESS: 0E1H
INITIAL VALUE: ---- -000B
System clock source select
000 : PAGE0
001 : PAGE1
010 : Not used
011 : Not used
100 : Not used
others : Setting prohibited
Figure 8-9 RPR(RAM Page Select Register)
24
Mar. 2005 Ver 0.2
Preliminary
Address
Register Name
Symbol
MC80F0104/0204
Initial Value
R/W
7 6 5 4 3 2 1 0
Addressing
Mode
R0
R/W
0 0 0 0 0 0 0 0
byte, bit1
R0IO
W
0 0 0 0 0 0 0 0
byte2
R1
R/W
-
-
- 0 0 0 0 0
byte, bit
R1IO
W
-
-
- 0 0 0 0 0
byte
R3
R/W
-
- 0 0 0 0 0 -
R3 port I/O direction register
R3IO
W
0 0 0 0 0 0 0 -
byte
00C8
Port 0 Open Drain Selection Register
R0OD
R/W
0 0 0 0 0 0 0 0
byte
00C9
Port 1 Open Drain Selection Register
R1OD
W
-
-
- 0 0 0 0 0
byte
00CB
Port 3 Open Drain Selection Register
R3OD
W
-
-
- 0 0 0 0 -
byte
00D0
Timer 0 mode control register
TM0
R/W
-
- 0 0 0 0 0 0
T0
R
0 0 0 0 0 0 0 0
Timer 0 data register
TDR0
W
1 1 1 1 1 1 1 1
Timer 0 capture data register
CDR0
R
0 0 0 0 0 0 0 0
Timer 1 mode control register
TM1
R/W
0 0 0 0 0 0 0 0
byte, bit
TDR1
W
1 1 1 1 1 1 1 1
byte
T1PPR
W
1 1 1 1 1 1 1 1
byte
T1
R
0 0 0 0 0 0 0 0
Timer 1 capture data register
CDR1
R
0 0 0 0 0 0 0 0
Timer 1 PWM duty register
T1PDR
R/W
0 0 0 0 0 0 0 0
byte
00D5
Timer 1 PWM high register
T1PWHR
W
-
-
byte
00D6
Timer 2 mode control register
TM2
R/W
-
- 0 0 0 0 0 0
T2
R
0 0 0 0 0 0 0 0
Timer 2 data register
TDR2
W
1 1 1 1 1 1 1 1
Timer 2 capture data register
CDR2
R
0 0 0 0 0 0 0 0
Timer 3 mode control register
TM3
R/W
0 0 0 0 0 0 0 0
TDR3
W
1 1 1 1 1 1 1 1
T3PPR
W
1 1 1 1 1 1 1 1
T3
R
0 0 0 0 0 0 0 0
Timer 3 PWM duty register
T3PDR
R/W
0 0 0 0 0 0 0 0
Timer 3 capture data register
CDR3
R
0 0 0 0 0 0 0 0
T3PWHR
W
-
- 0 0 0 0
byte
BUZR
W
1 1 1 1 1 1 1 1
byte
00C0
R0 port data register
00C1
R0 port I/O direction register
00C2
R1 port data register
00C3
R1 port I/O direction register
00C6
R3 port data register
00C7
Timer 0 register
00D1
00D2
00D3
Timer 1 data register
Timer 1 PWM period register
Timer 1 register
00D4
Timer 2 register
00D7
00D8
00D9
Timer 3 data register
Timer 3 PWM period register
Timer 3 register
00DA
00DB
Timer 3 PWM high register
00E0
Buzzer driver register
-
-
-
- 0 0 0 0
byte, bit
byte, bit
byte
byte
byte, bit
byte
byte, bit
byte
byte
Table 8-1 Control Registers
Mar. 2005 Ver 0.2
25
MC80F0104/0204
Address
Preliminary
Register Name
Symbol
Initial Value
R/W
7 6 5 4 3 2 1 0
00E1
RAM page selection register
RPR
R/W
-
- 0 0 0
byte, bit
00E2
SIO mode control register
SIOM
R/W
0 0 0 0 0 0 0 1
byte, bit
00E3
SIO data shift register
SIOR
R/W
Undefined
byte, bit
00E6
UART mode register
ASIMR
R/W
0 0 0 0 - 0 0 -
byte, bit
00E7
UART status register
ASISR
R
00E8
UART Baud rate generator control register
BRGCR
R/W
- 0 0 1 0 0 0 0
UART Receive buffer register
RXBR
R
0 0 0 0 0 0 0 0
UART Transmit shift register
TXSR
W
1 1 1 1 1 1 1 1
00EA
Interrupt enable register high
IENH
R/W
0 0 0 0 0 0 0 0
byte, bit
00EB
Interrupt enable register low
IENL
R/W
0 0 0 0 0 0 0 0
byte, bit
00EC
Interrupt request register high
IRQH
R/W
0 0 0 0 0 0 0 0
byte, bit
00ED
Interrupt request register low
IRQL
R/W
0 0 0 0 0 0 0 0
byte, bit
00EE
Interrupt edge selection register
IEDS
R/W
0 0 0 0 0 0 0 0
byte, bit
00EF
A/D converter mode control register
ADCM
R/W
0 0 0 0 0 0 0 1
byte, bit
00F0
A/D converter result high register
ADCRH
R(W)
0 1 0
00F1
A/D converter result low register
ADCRL
R
Undefined
BITR
R
Undefined
CKCTLR
W
0 - 0 1 0 1 1 1
WDTR
W
0 1 1 1 1 1 1 1
WDTDR
R
Undefined
0 0 0 0 0 0 0 0
00E9
00F2
00F4
Basic interval timer register
Clock control register
Watch dog timer register
Watch dog timer data register
-
-
-
-
-
-
Addressing
Mode
-
- 0 0 0
Undefined
byte
byte, bit
byte
byte
byte
byte
byte
00F5
Stop & sleep mode control register
SSCR
W
00F7
PFD control register
PFDR
R/W
00F8
Port selection register 0
PSR0
W
0 0 0 0 0 0 0 0
byte
00F9
Port selection register 1
PSR1
W
-
- 0 0 0 0
byte
00FC
Pull-up selection register 0
PU0
W
0 0 0 0 0 0 0 0
byte
00FD
Pull-up selection register 1
PU1
W
-
-
- 0 0 0 0 0
byte
00FF
Pull-up selection register 3
PU3
W
-
- 0 0 0 0 0 -
byte
-
-
-
-
-
-
- 0 0 0
byte
byte, bit
Table 8-1 Control Registers
1.
The ‘byte, bit’ means registers are controlled by both bit and byte manipulation instruction.
Caution) The R/W register except T1PDR and T3PDR are both can be byte and bit manipulated.
2.
The ‘byte’ means registers are controlled by only byte manipulation instruction. Do not use bit manipulation
instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers,
content of other seven bits are may varied to unwanted value.
*The mark of ‘-’ means this bit location is reserved.
26
Mar. 2005 Ver 0.2
Preliminary
Address
Name
Bit 7
Bit 6
Bit 5
MC80F0104/0204
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
T1CN
T1ST
0C0H
R0
R0 Port Data Register
0C1H
R0IO
R0 Port Direction Register
0C2H
R1
R1 Port Data Register
0C3H
R1IO
R1 Port Direction Register
0C6H
R3
R3 Port Data Register
0C7H
R3IO
R3 Port Direction Register
0C8H
R0OD
R0 Open Drain Selection Register
0C9H
R1OD
R1 Open Drain Selection Register
0CBH
R3OD
R3 Open Drain Selection Register
0D0H
TM0
0D1H
T0/TDR0/
CDR0
0D2H
TM1
0D3H
TDR1/
T1PPR
Timer1 Data Register / Timer1 PWM Period Register
0D4H
T1/CDR1
Timer1 Register / Timer1 Capture Data Register
0D5H
PWM1HR
-
-
-
-
0D6H
TM2
-
-
CAP2
T2CK2
0D7H
T2/TDR2/
CDR2
0D8H
TM3
0D9H
TDR3/
T3PPR
0DAH
T3/CDR3/
Timer3 Register / Timer3 Capture Data Register / Timer3 PWM Duty Register
T3PDR
0DBH
PWM3HR
0E0H
BUZR
0E1H
-
-
CAP0
Timer0 Register / Timer0 Data Register / Timer0 Capture Data Register
POL
16BIT
PWM1E
CAP1
T1CK1
T1CK0
Timer1 PWM High Register
T2CK1
T2CK0
T2CN
T2ST
T3CN
T3ST
Timer2 Register / Timer2 Data Register / Timer2 Capture Data Register
POL
16BIT
PWM3E
CAP3
T3CK1
T3CK0
Timer3 Data Register / Timer3 PWM Period Register
-
-
-
-
BUCK1
BUCK0
BUR5
BUR4
BUR3
BUR2
BUR1
BUR0
RPR
-
-
-
-
-
RPR2
RPR1
RPR0
0E2H
SIOM
POL
IOSW
SM1
SM0
SCK1
SCK0
SIOST
SIOSF
0E3H
SIOR
0E6H
ASIMR
TXE
RXE
PS1
PS0
-
SL
ISRM
-
0E7H
ASISR
-
-
-
-
-
PE
FE
OVE
0E8H
BRGCR
-
TPS2
TPS1
TPS0
MLD3
MLD2
MLD1
MLD0
0E9H
Timer3 PWM High Register
SIO Data Shift Register
RXR
UART Receive Buffer Register
TXR
UART Transmit Shift Register
0EAH
IENH
INT0E
INT1E
INT2E
INT3E
RXE
TXE
SIOE
T0E
0EBH
IENL
T1E
T2E
T3E
T4E
ADCE
WDTE
WTE
BITE
Table 8-2 Control Register Function Description
Mar. 2005 Ver 0.2
27
MC80F0104/0204
Address
Name
Preliminary
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0ECH
IRQH
INT0IF
INT1IF
INT2IF
INT3IF
RXIF
TXIF
SIOIF
T0IF
0EDH
IRQL
T1IF
T2IF
T3IF
T4IF
ADCIF
WDTIF
WTIF
BITIF
0EEH
IEDS
IED3H
IED3L
IED2H
IED2L
IED1H
IED1L
IED0H
IED0L
0EFH
ADCM
ADEN
ADCK
ADS3
ADS2
ADS1
ADS0
ADST
ADSF
0F0H
ADCRH
PSSEL1
PSSEL0
ADC8
-
-
-
0F1H
ADCRL
ADC Result Register Low
BITR1
Basic Interval Timer Data Register
WDTON
BTCL
BTS2
BTS1
BTS0
0F2H
0F4H
CKCTLR1
ADRST
WDTR
WDTCL
-
RCWDT
ADC Result Reg. High
7-bit Watchdog Timer Register
WDTDR
Watchdog Timer Data Register (Counter Register)
0F5H
SSCR
Stop & Sleep Mode Control Register
0F7H
PFDR
-
-
-
-
-
PFDEN
PFDM
PFDS
0F8H
PSR0
PWM3O
PWM1O
EC1E
EC0E
INT3E
INT2E
INT1E
INT0E
0F9H
PSR1
-
-
-
-
AVREFS
BUZO
T2O
T0O
0FCH
PU0
R0 Pull-up Selection Register
0FDH
PU1
R1 Pull-up Selection Register
0FFH
PU3
R3 Pull-up Selection Register
Table 8-2 Control Register Function Description
1. The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR.
Caution) The registers of dark-shaded area can not be accessed by bit manipulation instruction such as "SET1, CLR1", but should be
accessed by register operation instruction such as "LDM dp,#imm".
28
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
8.4 Addressing Mode
The HMS800 series MCU uses six addressing modes;
8.4.3 Direct Page Addressing→ dp
• Register addressing
In this mode, a address is specified within direct page.
• Immediate addressing
Example; G=0
• Direct page addressing
C535
LDA
;A ←RAM[35H]
35H
• Absolute addressing
• Indexed addressing
• Register-indirect addressing
35H
data
➋
~
~
~
~
8.4.1 Register Addressing
0E550H
C5
Register addressing accesses the A, X, Y, C and PSW.
0E551H
35
data → A
➊
8.4.2 Immediate Addressing → #imm
In this mode, second byte (operand) is accessed as a data
immediately.
Example:
0435
8.4.4 Absolute Addressing → !abs
ADC
#35H
MEMORY
04
A+35H+C → A
35
Absolute addressing sets corresponding memory data to
Data, i.e. second byte (Operand I) of command becomes
lower level address and third byte (Operand II) becomes
upper level address.
With 3 bytes command, it is possible to access to whole
memory area.
ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,
LDY, OR, SBC, STA, STX, STY
Example;
When G-flag is 1, then RAM address is defined by 16-bit
address which is composed of 8-bit RAM paging register
(RPR) and 8-bit immediate data.
LDM
35H,#55H
➊
0F100H
data
~
~
E4
0F101H
55
0F102H
35
Mar. 2005 Ver 0.2
➋
~
~
➊
A+data+C → A
07
0F101H
35
0F102H
F0
address: 0F035
data ← 55H
data
~
~
;A ←ROM[0F035H]
!0F035H
~
~
0F100H
0135H
ADC
0F035H
Example: G=1
E45535
0735F0
➋
The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR
Example; Addressing accesses the address 0135H regardless of G-flag.
29
MC80F0104/0204
983501
INC
Preliminary
;A ←ROM[135H]
!0135H
35H
data
135H
➌
~
~
0F100H
98
0F101H
35
0F102H
01
~
~
➋
~
~
➋
data
~
~
data+1 → data
data → A
➊
36H → X
DB
➊
address: 0135
X indexed direct page (8 bit offset) → dp+X
8.4.5 Indexed Addressing
X indexed direct page (no offset) → {X}
In this mode, a address is specified by the X register.
This address value is the second byte (Operand) of command plus the data of X-register. And it assigns the memory in Direct page.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA
ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR
Example; X=15H, G=1
Example; G=0, X=0F5H
D4
LDA
115H
{X}
;ACC←RAM[X].
data
~
~
45H+X
data
➌
data → A
➊
D4
0E550H
LDA
3AH
➋
~
~
C645
~
~
➋
~
~
0E550H
C6
0E551H
45
data → A
➊
45H+0F5H=13AH
X indexed direct page, auto increment→ {X}+
In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.
LDA, STA
Example; G=0, X=35H
DB
LDA
{X}+
Y indexed direct page (8 bit offset) → dp+Y
This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in
Direct page.
This is same with above (2). Use Y register instead of X.
Y indexed absolute → !abs+Y
Sets the value of 16-bit absolute address plus Y-register
data as Memory.This addressing mode can specify memory in whole area.
Example; Y=55H
30
Mar. 2005 Ver 0.2
Preliminary
D500FA
LDA
!0FA00H+Y
1625
0F100H
D5
0F101H
00
➊
0F102H
FA
0FA00H+55H=0FA55H
~
~
~
~
data
0FA55H
MC80F0104/0204
➋
ADC
[25H+X]
35H
05
36H
E0
➋ 0E005H
~
~
~
~
0E005H
➊ 25 + X(10) = 35H
data
~
~
~
~
data → A
➌
0FA00H
16
25
➌ A + data + C → A
8.4.6 Indirect Addressing
Y indexed indirect → [dp]+Y
Direct page indirect → [dp]
Assigns data address to use for accomplishing command
which sets memory data (or pair memory) by Operand.
Also index can be used with Index register X,Y.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
JMP, CALL
Example; G=0, Y=10H
Example; G=0
3F35
Processes memory data as Data, assigned by the data
[dp+1][dp] of 16-bit pair memory paired by Operand in Direct page plus Y-register data.
JMP
1725
[35H]
ADC
[25H]+Y
35H
0A
25H
05
36H
E3
26H
E0
~
~
0E30AH
~
~
➊
NEXT
~
~
0FA00H
➋
~
~
jump to
address 0E30AH
3F
~
~
0E015H
~
~
➋
~
~
0FA00H
35
➊
0E005H + Y(10)
= 0E015H
data
~
~
17
25
➌
A + data + C → A
X indexed indirect → [dp+X]
Processes memory data as Data, assigned by 16-bit pair
memory which is determined by pair data
[dp+X+1][dp+X] Operand plus X-register data in Direct
page.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Absolute indirect → [!abs]
The program jumps to address specified by 16-bit absolute
address.
JMP
Example; G=0
Example; G=0, X=10H
Mar. 2005 Ver 0.2
31
MC80F0104/0204
1F25E0
JMP
Preliminary
[!0C025H]
PROGRAM MEMORY
0E025H
25
0E026H
E7
~
~
➊
0E725H
~
~
NEXT
~
~
0FA00H
➋
jump to
address 0E30AH
~
~
1F
25
E0
32
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
9. I/O PORTS
The MC80F0104/0204 has three ports (R0, R1 and R3).
These ports pins may be multiplexed with an alternate
function for the peripheral features on the device. All port
can drive maximum 20mA of high current in output low
state, so it can directly drive LED device.
All pins have data direction registers which can define
these ports as output or input. A “1” in the port direction
register configure the corresponding port pin as output.
Conversely, write “0” to the corresponding bit to specify it
as input pin. For example, to use the even numbered bit of
R0 as output ports and the odd numbered bits as input
ports, write “55H” to address 0C1H (R0 port direction register) during initial setting as shown in Figure 9-1 .
its initial status is input.
WRITE “55H” TO PORT R0 DIRECTION REGISTER
0C0H
R0 data
0C1H
R0 direction
0C2H
R1 data
0C3H
R1 direction
0 1 0 1 0 1 0 1
7 6 5 4 3 2 1 0
BIT
I O I O I O I O PORT
7 6 5 4 3 2 1 0
I: INPUT PORT
O: OUTPUT PORT
Figure 9-1 Example of port I/O assignment
All the port direction registers in the MC80F0104/0204
have 0 written to them by reset function. On the other hand,
9.1 R0 and R0IO register
R0 is an 8-bit CMOS bidirectional I/O port (address
0C0H). Each I/O pin can independently used as an input or
an output through the R0IO register (address 0C1H). When
R00 through R07 pins are used as input ports, an on-chip
pull-up resistor can be connected to them in 1-bit units
R0 Data Register
R0
with a pull-up selection register 0 (PU0). Each I/O pin of
R0 port can be used to open drain output port by setting the
corresponding bit of the open drain selection register 0
(R0OD).
ADDRESS: 0F8H
RESET VALUE: 0000 0000B
ADDRESS: 0C0H
RESET VALUE: 00H
R07 R06 R05 R04 R03 R02 R01 R00
PSR0
PWM3OE PWM1OE EC1E EC0E INT3E INT2E INT1E INT0E
Input / Output data
R0 Direction Register
Port / INT Selection
0: R11, R12, R03, R00
1: INT0, INT1,INT2, INT3
ADDRESS: 0C1H
RESET VALUE: 00H
R0IO
Port / EC Selection
0: R04, R07
1: EC0, EC1
Port Direction
0: Input
1: Output
R0 Pull-up
Selection Register
Port / PWM Selection
0: R10, R11
1: PWM1O, PWM3O
ADDRESS: 0FCH
RESET VALUE: 00H
ADDRESS: 0F9H
RESET VALUE: ---- 0000B
PU0
Pull-up Resister Selection
0: Disable
1: Enable
R0 Open Drain
Selection Register
ADDRESS: 0C8H
RESET VALUE: 00H
R0OD
Open Drain Resister Selection
0: Disable
1: Enable
Mar. 2005 Ver 0.2
PSR1
-
-
-
-
AVREFS BUZOE T2OE T0OE
Port / TO Selection
0: R04, R07
1: EC0, EC1
R12/BUZO Selection
0: R12 port (Turn off buzzer)
1: BUZO port (Turn on buzzer)
R10 / AVREF Selection
0: R10 port
1: AVREF port
33
MC80F0104/0204
Preliminary
Figure 9-2 R0 Port Register
In addition, Port R0 is multiplexed with various alternate
functions. The port selection register PSR0 (address 0F8H)
and PSR1 (address 0F9H) control the selection of alternate
functions such as external interrupt 3 (INT3), external interrupt 2 (INT2), event counter input 0 (EC0), timer 0 output (T0O), timer 2 output (T2O) and event counter input 1
(EC1). When the alternate function is selected by writing
“1” in the corresponding bit of PSR0 or PSR1, port pin can
be used as a corresponding alternate features regardless of
the direction register R0IO.
The ADC input channel 1~7 (AN1~AN7), SIO data input
(SI), SIO data output (SOUT) and UART data input
(RXD), UART data output (TXD) and UART clock input
(ACLK) can be selected by setting ADCM(00EFH), SIOM(00E2H) and ASIMR(00E6H) register to enable the
corresponding peripheral operation and select operation
mode.
Port Pin
R00
R01
R02
R03
R04
R05
R06
R07
Alternate Function
INT3 (External interrupt 3)
SCK (SIO clock input/output)
AN1(ADC Input channel 1)
SI (SIO data input)
AN2 (ADC Input channel 2)
SOUT (SIO data output)
AN3 (ADC Input channel 3)
INT2 (External interrupt 2)
AN4 (ADC Input channel 4)
EC0 (Event counter input 0)
RXD (UART data input)
AN5 (ADC Input channel 5)
T0O (Timer output 0)
TXD (UART data output)
AN6 (ADC Input channel 6)
T2O (Timer output 2)
ACLK (UART clock input)
AN7 (ADC Input channel 7)
EC1 (Event counter input 1)
9.2 R1 and R1IO register
R1 is a 5-bit CMOS bidirectional I/O port (address 0C2H).
Each I/O pin can independently used as an input or an output through the R1IO register (address 0C3H). When R10
through R14 pins are used as input ports, an on-chip pullup resistor can be connected to them in 1-bit units with a
pull-up selection register 1 (PU1). Each I/O pin of R0 port
can be used to open drain output port by setting the corresponding bit of the open drain selection register 1 (R1OD).
In addition, Port R1 is multiplexed with various alternate
functions. The port selection register PSR0 (address 0F8H)
and PSR1 (address 0F9H) control the selection of alternate
functions such as Analog reference voltage input (AVREF),
external interrupt 0 (INT0), external interrupt 1 (INT1),
PWM 1 output (PWM1O), PWM 3 output (PWM3O) and
buzzer output (BUZO). When the alternate function is selected by writing “1” in the corresponding bit of PSR0 or
PSR1, port pin can be used as a corresponding alternate
features regardless of the direction register R1IO.
34
The ADC input channel 0 (AN0) can be selected by setting
ADCM(00EFH) register to enable ADC and select channel
0.
Port Pin
R10
R11
R12
Alternate Function
AN0 (ADC input channel 0)
AVREF (Analog reference voltage)
PWM1O (PWM 1 output)
INT0 (External Interrupt 0)
PWM3O (PWM 3 output)
INT1 (External Interrupt 1)
BUZO (Buzzer output)
Mar. 2005 Ver 0.2
Preliminary
ADDRESS: 0C2H
RESET VALUE: ---0 0000B
R1 Data Register
R1
-
-
-
R14 R13 R12 R11 R10
MC80F0104/0204
ADDRESS: 0F8H
RESET VALUE: 0000 0000B
PSR0
PWM3OE PWM1OE EC1E EC0E INT3E INT2E INT1E INT0E
Port / INT Selection
0: R11, R12, R03, R00
1: INT0, INT1,INT2, INT3
Input / Output data
R1 Direction Register
R1IO
-
-
ADDRESS: 0C3H
RESET VALUE: ---0 0000B
Port / EC Selection
0: R04, R07
1: EC0, EC1
-
Port / PWM Selection
0: R10, R11
1: PWM1O, PWM3O
Port Direction
0: Input
1: Output
R1 Pull-up
Selection Register
PU1
-
-
ADDRESS: 0FDH
RESET VALUE: ---0 0000B
-
ADDRESS: 0F9H
RESET VALUE: ---- 0000B
PSR1
Pull-up Resister Selection
0: Disable
1: Enable
R1 Open Drain
Selection Register
R1OD
-
-
ADDRESS: 0C9H
RESET VALUE: ---0 0000B
Open Drain Resister Selection
0: Disable
1: Enable
-
-
-
-
AVREFS BUZOE T2OE T0OE
Port / TO Selection
0: R04, R07
1: EC0, EC1
R12/BUZO Selection
0: R12 port (Turn off buzzer)
1: BUZO port (Turn on buzzer)
R10 / AVREF Selection
0: R10 port
1: AVREF port
Figure 9-3 R1 Port Register
Mar. 2005 Ver 0.2
35
MC80F0104/0204
Preliminary
9.3 R3 and R3IO register
R3 is a 5-bit CMOS bidirectional I/O port (address 0C6H).
Each I/O pin (except R35) can independently used as an input or an output through the R3IO register (address 0C7H).
R35 is an input only port. When R31 through R35 pins are
used as input ports, an on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up selection register 3 (PU3). R31 through R34 pins can be used to open
drain output port by setting the corresponding bit of the
open drain selection register 3 (R3OD).
In addition, Port R3 is multiplexed with alternate functions. R31 and R32 can be used as ADC input channel 14
and 15 by setting ADCM to enable ADC and select channel 14 and 15.
Port Pin
R31
R32
ADDRESS: 0C6H
RESET VALUE: --00 000-B
R3 Data Register
R3
-
-
R35 R34 R33 R32 R31
Input data
R3 Direction Register
R3IO
-
-
-
R33, R34 and R35 is multiplexed with XIN, XOUT, and
RESET pin. These pins can be used as general I/O pins by
setting writing option described in "23. Device Configuration Area" on page 102.
Input / Output data
ADDRESS: 0C7H
RESET VALUE: ---0 000-B
Port Direction
0: Input
1: Output
Alternate Function
AN14 (ADC input channel 14)
AN15 (ADC input channel 15)
-
R3 Pull-up
Selection Register
PU3
-
-
ADDRESS: 0FFH
RESET VALUE: --00 000-B
-
Pull-up Resister Selection
0: Disable
1: Enable
R3 Open Drain
Selection Register
ADDRESS: 0CBH
RESET VALUE: ---0 000-B
R3OD
Open Drain Resister Selection
0: Disable
1: Enable
36
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
10. CLOCK GENERATOR
ry is through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the data sheet
must be observed.
As shown in Figure 10-1 , the clock generator produces the
basic clock pulses which provide the system clock to be
supplied to the CPU and the peripheral hardware. It contains main-frequency clock oscillator. The system clock
operation can be easily obtained by attaching a crystal or a
ceramic resonator between the XIN and XOUT pin, respectively. The system clock can also be obtained from the external oscillator. In this case, it is necessary to input a
external clock signal to the XIN pin and open the XOUT pin.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuit-
To the peripheral block, the clock among the not-divided
original clock, clocks divided by 1, 2, 4,..., up to 4096 can
be provided. Peripheral clock is enabled or disabled by
STOP instruction. The peripheral clock is controlled by
clock control register (CKCTLR). See "11. BASIC INTERVAL TIMER" on page 39 for details.
STOP
INOSC
XIN
OSC
Circuit
XOUT
SLEEP
INOSC
Main OSC
Stop
fXIN
ONP
Circuit
Clock Pulse
Generator
(÷2)
fEX
MUX
INCLK
Int OSC
Circuit
INOSC
PRESCALER
PS0
INOSC (IN4MCLK/IN2MCLK/
IN4MCLKXO/IN2MCLKXO)
7~3
÷1
2~0
PS1
÷2
PS2
÷4
PS3
÷8
PS4
÷16
Configuration Option Register (20FFH)
fEX (Hz)
4M
Internal
system clock
PS5
÷32
PS6
÷64
PS7
÷128
PS8
÷256
PS9
PS10
PS11
PS12
÷512 ÷1024 ÷2048 ÷4096
Peripheral clock
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10
PS11
PS12
Frequency
4M
2M
1M
500K
250K
125K
62.5K
31.25K
15.63K
7.183K
3.906K
1.953K
976
period
250n
500n
1u
2u
4u
8u
16u
32u
64u
128u
256u
512u
1.024m
Figure 10-1 Block Diagram of Clock Generator
10.1 Oscillation Circuit
XIN and XOUT are the input and output, respectively, a inverting amplifier which can be set for use as an on-chip oscillator, as shown in Figure 10-2 .
C1
Xout
C2
Xin
Vss
Note: When using a system clock oscillator, carry out wiring in
the broken line area in Figure 10-2 to prevent any effects from wiring capacities.
- Minimize the wiring length.
- Do not allow wiring to intersect with other signal conductors.
- Do not allow wiring to come near changing high current.
- Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do not ground to any ground pattern where high
current is present.
- Do not fetch signals from the oscillator.
Figure 10-2 Oscillator Connections
Mar. 2005 Ver 0.2
37
MC80F0104/0204
Preliminary
n addition, see Figure 10-3 for the layout of the crystal.
omitted for more cost saving. However, the characteristics
of external R only oscillation are more variable than external RC oscillation.
Vdd
XOUT
REXT
XIN
XIN
CEXT
XOUT
fXIN÷4
Figure 10-3 Layout of Oscillator PCB circuit
Figure 10-5 RC Oscillator Connections
To drive the device from an external clock source, Xout
should be left unconnected while Xin is driven as shown in
Figure 10-4 . There are no requirements on the duty cycle
of the external clock signal, since the input to the internal
clocking circuitry is through a divide-by-two flip-flop, but
minimum and maximum high and low times specified on
the data sheet must be observed.
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and
ceramic resonator have their own characteristics, the user
should consult the crystal manufacturer for appropriate
values of external components.
OPEN
External
Clock
Source
Xout
Xin
Vss
Figure 10-4 External Clock Connections
In addition, the MC80F0104/0204 has an ability for the external RC oscillated operation. It offers additional cost savings for timing insensitive applications. The RC
oscillator frequency is a function of the supply voltage, the
external resistor (REXT) and capacitor (CEXT) values, and
the operating temperature.
The user needs to take into account variation due to tolerance of external R and C components used.
Cint ≈ 6pF
VDD
REXT
XIN
CINT ≈ 6pF
fXIN÷4
XOUT
Figure 10-6 R Oscillator Connections
To use the RC oscillation , the CLK option of the configuration bits (20FFH) should be set to “EXRC or EXRCXO”.
The oscillator frequency, divided by 4, is output from the
Xout pin, and can be used for test purpose or to synchronize other logic.
In addition to external crystal/resonator and external RC/R
oscillation, the MC80F0104/0204 provides the internal
4MHz or 2MHz oscillation. The internal 4MHz/2MHz oscillation needs no external parts.
To use the internal 4MHz/2MHz oscillation, the CLK option of the configuration bits should be set to “IN4MCLK”,
“IN2MCLK”, “IN4MCLKXO” or “IN2MCLKXO”. For
detail description on the configuration bits, refer to "23.
Device Configuration Area" on page 102
Figure 10-5 shows how the RC combination is connected
to the MC80F0104/0204. External capacitor (CEXT) can be
38
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
11. BASIC INTERVAL TIMER
If the STOP instruction executed after writing "1" to bit
RCWDT of CKCTLR, it goes into the internal RC oscillated watchdog timer mode. In this mode, all of the block is
halted except the internal RC oscillator, Basic Interval
Timer and Watchdog Timer. More detail informations are
explained in Power Saving Function. The bit WDTON decides Watchdog Timer or the normal 7-bit timer.
Source clock can be selected by lower 3 bits of CKCTLR.
The MC80F0104/0204 has one 8-bit Basic Interval Timer
that is free-run and can not stop. Block diagram is shown
in Figure 11-1 . In addition, the Basic Interval Timer generates the time base for watchdog timer counting. It also
provides a Basic interval timer interrupt (BITIF).
The 8-bit Basic interval timer register (BITR) is increased
every internal count pulse which is divided by prescaler.
Since prescaler has divided ratio by 8 to 1024, the count
rate is 1/8 to 1/1024 of the oscillator frequency. As the
count overflow from FFH to 00H, this overflow causes the
interrupt to be generated.
BITR and CKCTLR are located at same address, and address 0F2H is read as a BITR, and written to CKCTLR.
Note: All control bits of Basic interval timer are in CKCTLR register which is located at same address of BITR (address ECH). Address ECH is read as BITR, written to CKCTLR. Therefore, the
CKCTLR can not be accessed by bit manipulation instruction.
The Basic Interval Timer is controlled by the clock control
register (CKCTLR) shown in Figure 11-2. If the RCWDT
bit is set to “1”, the clock source of the BITR is changed to
the internal RC oscillation.
When write "1" to bit BTCL of CKCTLR, BITR register is
cleared to "0" and restart to count-up. The bit BTCL becomes "0" after one machine cycle by hardware.
Internal RC OSC
XIN PIN
Prescaler
RCWDT
÷8
÷16
÷32
÷64
÷128
÷256
÷512
÷1024
1
source
clock
8-bit up-counter
overflow
BITR
Basic Interval
Timer Interrupt
BITIF
0
MUX
[0F2H]
To Watchdog timer (WDTCK)
clear
Select Input clock 3
BCK[2:0]
[0F2H]
RCWDT
BTCL
CKCTLR
Basic Interval Timer
clock control register
Read
Internal bus line
Figure 11-1 Block Diagram of Basic Interval Timer
Mar. 2005 Ver 0.2
39
MC80F0104/0204
Preliminary
CKCTLR
[2:0]
Interrupt (overflow) Period (ms)
@ fXIN = 8MHz
Source clock
fXIN÷8
fXIN÷16
fXIN÷32
fXIN÷64
fXIN÷128
fXIN÷256
fXIN÷512
fXIN÷1024
000
001
010
011
100
101
110
111
0.256
0.512
1.024
2.048
4.096
8.192
16.384
32.768
Table 11-1 Basic Interval Timer Interrupt Period
7
CKCTLR
6
-
ADRST
5
4
3
RCWDT WDTONBTCL
BTCL
2
1
0
BTS2 BTS1 BTS0
ADDRESS: 0F2H
INITIAL VALUE: 0-01 0111B
Basic Interval Timer source clock select
000: fXIN ÷ 8
001: fXIN ÷ 16
010: fXIN ÷ 32
011: fXIN ÷ 64
100: fXIN ÷ 128
101: fXIN ÷ 256
110: fXIN ÷ 512
111: fXIN ÷ 1024
Caution:
Both register are in same address,
when write, to be a CKCTLR,
when read, to be a BITR.
Clear bit
0: Normal operation (free-run)
1: Clear 8-bit counter (BITR) to “0”. This bit becomes 0 automatically
after one machine cycle, and starts counting.
Watchdog timer Enable bit
0: Operate as 7-bit Timer
1: Enable Watchdog Timer operation
See the section “Watchdog Timer”.
RC Watchdog Selection bit
0: Disable Internal RC Watchdog Timer
1: Enable Internal RC Watchdog Timer
Address Trap Reset Selection
0: Enable Address Fail Reset
1: Disable Address Fail Reset
7
6
BITR
5
4
3
BTCL
2
1
0
ADDRESS: 0F2H
INITIAL VALUE: Undefined
8-BIT FREE-RUN BINARY COUNTER
Figure 11-2 BITR: Basic Interval Timer Mode Register
Example 1:
Example 2:
Interrupt request flag is generated every 8.192ms at 4MHz.
Interrupt request flag is generated every 8.192ms at 8MHz.
:
LDM
SET1
EI
:
40
CKCTLR,#1BH
BITE
:
LDM
SET1
EI
:
CKCTLR,#1CH
BITE
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
12. WATCHDOG TIMER
The watchdog timer rapidly detects the CPU malfunction
such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer
signal for detecting malfunction can be selected either a reset CPU or a interrupt request.
The RC oscillated watchdog timer is activated by setting
the bit RCWDT as shown below.
LDM
LDM
LDM
STOP
NOP
NOP
:
When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals.
The watchdog timer has two types of clock source. The
first type is an on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the external oscillator of the XIN pin. It means
that the watchdog timer will run, even if the clock on the
XIN pin of the device has been stopped, for example, by entering the STOP mode. The other type is a prescaled system clock.
CKCTLR,#3FH; enable the RC-OSC WDT
WDTR,#0FFH ; set the WDT period
SSCR, #5AH ;ready for STOP mode
; enter the STOP mode
; RC-OSC WDT running
The RC-WDT oscillation period is vary with temperature,
VDD and process variations from part to part (approximately, 33~100uS). The following equation shows the
RCWDT oscillated watchdog timer time-out.
TRCWDT=CLKRCWDT×28×WDTR + (CLKRCWDT×28)/2
where, CLKRCWDT = 33~100uS
The watchdog timer consists of 7-bit binary counter and
the watchdog timer data register. When the value of 7-bit
binary counter is equal to the lower 7 bits of WDTR, the
interrupt request flag is generated. This can be used as
Watchdog timer interrupt or reset the CPU in accordance
with the bit WDTON.
In addition, this watchdog timer can be used as a simple 7bit timer by interrupt WDTIF. The interval of watchdog
timer interrupt is decided by Basic Interval Timer. Interval
equation is as below.
TWDT = (WDTR+1) × Interval of BIT
Note: Because the watchdog timer counter is enabled after clearing Basic Interval Timer, after the bit WDTON set to "1", maximum
error of timer is depend on prescaler ratio of Basic Interval Timer.
The 7-bit binary counter is cleared by setting WDTCL(bit7 of
WDTR) and the WDTCL is cleared automatically after 1 machine
cycle.
clear
BASIC INTERVAL TIMER
OVERFLOW
Watchdog
Counter (7-bit)
Count
source
clear
“0”
“1”
enable
comparator
WDTCL
WDTON in CKCTLR [0F2H]
7-bit compare data
WDTIF
7
WDTR
[0F4H]
to reset CPU
Watchdog Timer interrupt
Watchdog Timer
Register
Internal bus line
Figure 12-1 Block Diagram of Watchdog Timer
Mar. 2005 Ver 0.2
41
MC80F0104/0204
Preliminary
Watchdog Timer Control
er output will become active at the rising overflow from
the binary counters unless the binary counter is cleared. At
this time, when WDTON=1, a reset is generated, which
drives the RESET pin to low to reset the internal hardware.
When WDTON=0, a watchdog timer interrupt (WDTIF) is
generated. The WDTON bit is in register CLKCTLR.
Figure 12-2 shows the watchdog timer control register.
The watchdog timer is automatically disabled after reset.
The CPU malfunction is detected during setting of the detection time, selecting of output, and clearing of the binary
counter. Clearing the binary counter is repeated within the
detection time.
The watchdog timer temporarily stops counting in the
STOP mode, and when the STOP mode is released, it automatically restarts (continues counting).
If the malfunction occurs for any cause, the watchdog timW
7
WDTR
W
6
W
5
W
4
W
3
W
2
W
1
W
0
ADDRESS: 0F4H
INITIAL VALUE: 0111 1111B
WDTCL
7-bit compare data
Clear count flag
0: Free-run count
1: When the WDTCL is set to “1”, binary counter
is cleared to “0”. And the WDTCL becomes “0” automatically
after one machine cycle. Counter count up again.
Figure 12-2 WDTR: Watchdog Timer Control Register
Example: Sets the watchdog timer detection time to 1 sec.
Within WDT
detection time
Within WDT
detection time
at 4.194304MHz
LDM
LDM
CKCTLR,#3FH
WDTR,#08FH
;Select 1/1024 clock source, WDTON ← 1, Clear Counter
LDM
:
:
:
:
LDM
:
:
:
:
LDM
WDTR,#08FH
;Clear counter
WDTR,#08FH
;Clear counter
WDTR,#08FH
;Clear counter
Enable and Disable Watchdog
Watchdog timer is enabled by setting WDTON (bit 4 in
CKCTLR) to “1”. WDTON is initialized to “0” during reset and it should be set to “1” to operate after reset is released.
Example: Enables watchdog timer for Reset
:
LDM
:
:
CKCTLR,#xxx1_xxxxB;WDTON ← 1
The watchdog timer is disabled by clearing bit 4 (WDTON) of CKCTLR. The watchdog timer is halted in STOP
mode and restarts automatically after STOP mode is released.
42
Watchdog Timer Interrupt
The watchdog timer can be also used as a simple 7-bit timer by clearing bit4 of CKCTLR to “0”. The interval of
watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is shown as below.
TWDT = (WDTR+1) × Interval of BIT
The stack pointer (SP) should be initialized before using
the watchdog timer output as an interrupt source.
Example: 7-bit timer interrupt set up.
LDM
LDM
CKCTLR,#xxx0_xxxxB;WDTON ←0
WDTR,#8FH
;WDTCL ←1
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
:
Source clock
BIT overflow
Binary-counter
2
1
3
0
1
2
3
Counter
Clear
WDTR
0
Counter
Clear
3
n
Match
Detect
WDTIF interrupt
WDTR ← “1000_0011B”
WDT reset
reset
Figure 12-3 Watchdog timer Timing
If the watchdog timer output becomes active, a reset is generated, which drives the RESET pin low to reset the internal hardware.
Mar. 2005 Ver 0.2
The main clock oscillator also turns on when a watchdog
timer reset is generated in sub clock mode.
43
MC80F0104/0204
Preliminary
13. TIMER/EVENT COUNTER
in response external or internal clock sources same with
timer or counter function. When external clock edge input,
the count register is captured into Timer data register correspondingly. When external clock edge input, the count
register is captured into capture data register CDRx.
TheMC80F0104/0204 has Four Timer/Counter registers.
Each module can generate an interrupt to indicate that an
event has occurred (i.e. timer match).
Timer 0 and Timer 1 are can be used either two 8-bit Timer/Counter or one 16-bit Timer/Counter with combine
them. Also Timer 2 and Timer 3 are same. Timer 4 is 16bit Timer/Counter.
Timer 0 and Timer 1 is shared with "PWM" function and
"Compare output" function. It has six operating modes: "8bit timer/counter", "16-bit timer/counter", "8-bit capture",
"16-bit capture", "8-bit compare output", and "10-bit
PWM" which are selected by bit in Timer mode register
TM0 and TM1 as shown in Table 13-1, Figure 13-1 .
In the “timer” function, the register is increased every internal clock input. Thus, one can think of it as counting internal clock input. Since a least clock consists of 2 and
most clock consists of 2048 oscillator periods, the count
rate is 1/2 to 1/2048 of the oscillator frequency.
Timer 2 and Timer 3 is shared with "PWM" function and
"Compare output" function. It has six operating modes: "8bit timer/counter", "16-bit timer/counter", "8-bit capture",
"16-bit capture", "8-bit compare output", and "10-bit
PWM" which are selected by bit in Timer mode register
TM2 and TM3 as shown in Table 13-2, Figure 13-2 .
In the “counter” function, the register is increased in response to a 0-to-1 (rising edge) transition at its corresponding external input pin, EC0 or EC1.
In addition the “capture” function, the register is increased
16BIT
CAP0
CAP1
PWM1E
T0CK
[2:0]
T1CK
[1:0]
PWM1O
0
0
0
0
XXX
XX
0
8-bit Timer
8-bit Timer
0
0
1
0
111
XX
0
8-bit Event counter
8-bit Capture
0
1
0
0
XXX
XX
1
8-bit Capture (internal clock)
8-bit Compare Output
0
X
0
1
XXX
XX
1
8-bit Timer/Counter
10-bit PWM
1
0
0
0
XXX
11
0
16-bit Timer
1
0
0
0
111
11
0
16-bit Event counter
1
1
1
0
XXX
11
0
16-bit Capture (internal clock)
TIMER 0
TIMER 1
Table 13-1 Operation Modes of Timer 0, 1
1. X means the value of “0” or “1” corresponds to user operation.
16BIT
CAP2
CAP3
PWM3E
T2CK
[2:0]
T3CK
[1:0]
PWM3O
0
0
0
0
XXX
XX
0
8-bit Timer
8-bit Timer
0
0
1
0
111
XX
0
8-bit Event counter
8-bit Capture
0
1
0
0
XXX
XX
1
8-bit Capture (internal clock)
8-bit Compare Output
0
X
0
1
XXX
XX
1
8-bit Timer/Counter
10-bit PWM
1
0
0
0
XXX
11
0
16-bit Timer
1
0
0
0
111
11
0
16-bit Event counter
1
1
1
0
XXX
11
0
16-bit Capture (internal clock)
TIMER 2
TIMER 3
Table 13-2 Operating Modes of Timer 2, 3
44
Mar. 2005 Ver 0.2
Preliminary
R/W
5
TM0
TM1
-
-
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
CAP0 T0CK2 T0CK1
BTCL T0CK0 T0CN
T0ST
MC80F0104/0204
ADDRESS: 0D0H
INITIAL VALUE: --00 0000B
Bit Name
Bit Position
Description
CAP0
TM0.5
0: Timer/Counter mode
1: Capture mode selection flag
T0CK2
T0CK1
T0CK0
TM0.4
TM0.3
TM0.2
000: 8-bit Timer, Clock source is fXIN ÷ 2
001: 8-bit Timer, Clock source is fXIN ÷ 4
010: 8-bit Timer, Clock source is fXIN ÷ 8
011: 8-bit Timer, Clock source is fXIN ÷ 32
100: 8-bit Timer, Clock source is fXIN ÷ 128
101: 8-bit Timer, Clock source is fXIN ÷ 512
110: 8-bit Timer, Clock source is fXIN ÷ 2048
111: EC0 (External clock)
T0CN
TM0.1
0: Timer count pause
1: Timer count start
T0ST
TM0.0
0: When cleared, stop the counting.
1: When set, Timer 0 Count Register is cleared and start again.
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
POL
16BIT PWM1E CAP1 T1CK1
BTCL T1CK0 T1CN T1ST
ADDRESS: 0D2H
INITIAL VALUE: 00H
Bit Name
Bit Position
Description
POL
TM1.7
0: PWM Duty Active Low
1: PWM Duty Active High
16BIT
TM1.6
0: 8-bit Mode
1: 16-bit Mode
PWM1E
TM1.5
0: Disable PWM
1: Enable PWM
CAP1
TM1.4
0: Timer/Counter mode
1: Capture mode selection flag
T1CK1
T1CK0
TM1.3
TM1.2
00: 8-bit Timer, Clock source is fXIN
01: 8-bit Timer, Clock source is fXIN ÷ 4
10: 8-bit Timer, Clock source is fXIN ÷ 16
11: 8-bit Timer, Clock source is Using the Timer 2 Clock
T1CN
TM1.1
0: Timer count pause
1: Timer count start
T1ST
TM1.0
0: When cleared, stop the counting.
1: When set, Timer 0 Count Register is cleared and start again.
TDR0
TDR1
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
ADDRESS: 0D1H
INITIAL VALUE: 0FFH
ADDRESS: 0D3H
INITIAL VALUE: 0FFH
Read: Count value read
Write: Compare data write
Figure 13-1 TM0, TM1 Registers
Mar. 2005 Ver 0.2
45
MC80F0104/0204
Preliminary
R/W
5
TM2
-
-
R/W
3
R/W
2
R/W
1
R/W
0
CAP2 T2CK2 T2CK1
BTCL T2CK0 T2CN
T2ST
ADDRESS: 0D6H
INITIAL VALUE: --00 0000B
Bit Name
Bit Position
Description
CAP2
TM2.5
0: Timer/Counter mode
1: Capture mode selection flag
T2CK2
T2CK1
T2CK0
TM2.4
TM2.3
TM2.2
000: 8-bit Timer, Clock source is fXIN ÷ 2
001: 8-bit Timer, Clock source is fXIN ÷ 4
010: 8-bit Timer, Clock source is fXIN ÷ 8
011: 8-bit Timer, Clock source is fXIN ÷ 16
100: 8-bit Timer, Clock source is fXIN ÷ 64
101: 8-bit Timer, Clock source is fXIN ÷ 256
110: 8-bit Timer, Clock source is fXIN ÷ 1024
111: EC1 (External clock)
T2CN
TM2.1
0: Timer count pause
1: Timer count start
T2ST
TM2.0
0: When cleared, stop the counting.
1: When set, Timer 0 Count Register is cleared and start again.
R/W
7
TM3
R/W
4
POL
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
16BIT PWM3E CAP3 T3CK1
BTCL T3CK0 T3CN T3ST
ADDRESS: 0D8H
INITIAL VALUE: 00H
Bit Name
Bit Position
Description
POL
TM3.7
0: PWM Duty Active Low
1: PWM Duty Active High
16BIT
TM3.6
0: 8-bit Mode
1: 16-bit Mode
PWM3E
TM3.5
0: Disable PWM
1: Enable PWM
CAP3
TM3.4
0: Timer/Counter mode
1: Capture mode selection flag
T3CK1
T3CK0
TM3.3
TM3.2
00: 8-bit Timer, Clock source is fXIN
01: 8-bit Timer, Clock source is fXIN ÷ 4
10: 8-bit Timer, Clock source is fXIN ÷ 16
11: 8-bit Timer, Clock source is Using the Timer 2 Clock
T3CN
TM3.1
0: Timer count pause
1: Timer count start
T3ST
TM3.0
0: When cleared, stop the counting.
1: When set, Timer 0 Count Register is cleared and start again.
TDR2
TDR3
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
ADDRESS: 0D7H
INITIAL VALUE: 0FFH
ADDRESS: 0D9H
INITIAL VALUE: 0FFH
Read: Count value read
Write: Compare data write
Figure 13-2 TM2, TM3 Registers
46
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
13.1 8-bit Timer / Counter Mode
cleared to "0" (Figure 13-3 ). These timers have each 8-bit
count register and data register. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide ratio option of 1, 2, 4, 8, 16,
32, 64, 128, 256, 512, 1024, 2048 or external clock (selected by control bits TxCK0, TxCK1, TxCK2 of register
TMx).
The MC80F0104/0204 has four 8-bit Timer/Counters,
Timer 0, Timer 1, Timer 2, Timer 3. The Timer 0, Timer 1
are shown in Figure 13-3 and Timer 2, Timer 3 are shown
in Figure 13-4 .
The “timer” or “counter” function is selected by control
registers TM0, TM1, TM2, TM3 as shown in Figure 13-1
. To use as an 8-bit timer/counter mode, bit CAP0, CAP1,
CAP2, or CAP3 of TMx should be cleared to “0” and
16BIT and PWM1E or PWM3E of TM1 or TM3 should be
TM0
7
6
-
-
-
-
5
4
3
2
1
0
ADDRESS: 0D0H
INITIAL VALUE: --00 0000B
CAP0 T0CK2 T0CK1
BTCL T0CK0 T0CN T0ST
0
X
X
X
X
X
X means don’t care
7
TM1
6
5
4
3
2
1
0
POL 16BIT PWM1E CAP1 T1CK1
BTCL T1CK0 T1CN T1ST
X
0
0
0
X
X
X
ADDRESS: 0D2H
INITIAL VALUE: 00H
X
X means don’t care
T0CK[2:0]
EDGE
DETECTOR
EC0 PIN
111
T0ST
÷2
000
XIN PIN
Prescaler
÷4
0: Stop
1: Clear and start
001
÷8
010
÷ 32
T0 (8-bit)
clear
011
÷ 128
100
÷ 512
÷ 2048
101
T0CN
T0IF
Comparator
110
MUX
TIMER 0
TDR0 (8-bit)
TIMER 0
INTERRUPT
F/F
R05 / T0O
T1CK[1:0]
T1ST
÷1
÷2
÷8
0: Stop
1: Clear and start
11
00
T1 (8-bit)
01
clear
10
MUX
T1CN
T1IF
Comparator
TIMER 1
TIMER 1
INTERRUPT
TDR1 (8-bit)
Figure 13-3 8-bit Timer/Counter 0, 1
Mar. 2005 Ver 0.2
47
MC80F0104/0204
TM2
Preliminary
7
6
-
-
-
-
5
4
3
2
1
0
ADDRESS: 0D6H
INITIAL VALUE: --000000B
CAP2 T2CK2 T2CK1
BTCL T2CK0 T2CN T2ST
0
X
X
X
X
X
X means don’t care
7
TM3
6
5
4
3
2
1
0
ADDRESS: 0D8H
INITIAL VALUE: 00H
POL 16BIT PWM3E CAP3 T3CK1
BTCL T3CK0 T3CN T3ST
X
0
0
0
X
X
X
X
X means don’t care
T2CK[2:0]
EDGE
DETECTOR
EC1 PIN
111
T2ST
÷2
000
XIN PIN
Prescaler
÷4
0: Stop
1: Clear and start
001
÷8
010
÷ 16
T2 (8-bit)
clear
011
÷ 64
100
÷ 256
÷ 1024
101
T2CN
T2IF
Comparator
110
MUX
TIMER 2
TDR2 (8-bit)
TIMER 2
INTERRUPT
F/F
R06 / T2O
T3CK[1:0]
T3ST
÷1
÷4
÷ 16
0: Stop
1: Clear and start
11
00
T3 (8-bit)
01
clear
10
MUX
T3CN
T3IF
Comparator
TIMER 3
TIMER 3
INTERRUPT
TDR3 (8-bit)
Figure 13-4 8-bit Timer/Counter 2, 3
48
Mar. 2005 Ver 0.2
Preliminary
ter. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide
ratio option of 2, 4, 8, 32, 128, 512, 2048 selected by control bits T0CK[2:0] of register TM0 or 1, 2, 8 selected by
control bits T1CK[1:0] of register TM1, or 2, 4, 8, 16, 64,
256, 1024 selected by control bits T2CK[2:0] of register
TM2, or 1, 4, 16 selected by control bits T3CK[1:0] of register TM3. In the Timer 0, timer register T0 increases from
00H until it matches TDR0 and then reset to 00H. The
match output of Timer 0 generates Timer 0 interrupt
(latched in T0IF bit).
Example 1:
Timer0 = 2ms 8-bit timer mode at 4MHz
Timer1 = 0.5ms 8-bit timer mode at 4MHz
Timer2 = 1ms 8-bit timer mode at 4MHz
Timer3 = 1ms 8-bit timer mode at 4MHz
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
SET1
SET1
SET1
SET1
EI
TDR0,#249
TDR1,#249
TDR2,#249
TDR3,#249
TM0,#0000_1111B
TM1,#0000_1011B
TM2,#0000_1111B
TM3,#0000_1011B
T0E
T1E
T2E
T3E
In counter function, the counter is increased every 0-to-1
(rising edge) transition of EC0 pin. In order to use counter
function, the bit EC0 of the Port Selection Register
(PSR0.4) is set to "1". The Timer 0 can be used as a counter
by pin EC0 input, but Timer 1 can not. Likewise, In order
to use Timer2 as counter function, the bit EC1 of the Port
Selection Register (PSR0.5) is set to "1". The Timer 2 can
be used as a counter by pin EC1 input, but Timer 3 can not.
Example 2:
Timer0 = 8-bit event counter mode
Timer1 = 0.5ms 8-bit timer mode at 4MHz
Timer2 = 8-bit event counter mode
Timer3 = 1ms 8-bit timer mode at 4MHz
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
SET1
SET1
SET1
SET1
EI
MC80F0104/0204
13.1.1 8-bit Timer Mode
TDR0,#249
TDR1,#249
TDR2,#249
TDR3,#249
TM0,#0001_1111B
TM1,#0000_1011B
TM2,#0001_1111B
TM3,#0000_1011B
T0E
T1E
T2E
T3E
In the timer mode, the internal clock is used for counting
up. Thus, you can think of it as counting internal clock input. The contents of TDRn are compared with the contents
of up-counter, Tn. If match is found, a timer n interrupt
(TnIF) is generated and the up-counter is cleared to 0.
Counting up is resumed after the up-counter is cleared.
As the value of TDRn is changeable by software, time interval is set as you want.
These timers have each 8-bit count register and data regis-
Start count
~
~
Source clock
~
~
Up-counter
n
2
3
~
~
n-2
n-1
n
0
1
2
3
4
Match
Detect
Counter
Clear
~
~
T1IF interrupt
1
~
~
TDR1
0
Figure 13-5 Timer Mode Timing Chart
Mar. 2005 Ver 0.2
49
MC80F0104/0204
Preliminary
Example: Make 1ms interrupt using by Timer0 at 4MHz
LDM
LDM
SET1
EI
TM0,#0FH
TDR0,#124
T0E
;
;
;
;
divide by 32
8us x (124+1)= 1ms
Enable Timer 0 Interrupt
Enable Master Interrupt
When
TM0 = 0000 1111B (8-bit Timer mode, Prescaler divide ratio = 32)
TDR0 = 124D = 7CH
fXIN = 4 MHz
1
INTERRUPT PERIOD =
× 32 × (124+1) = 1 ms
4 × 106 Hz
TDR0
MATCH
(TDR0 = T0)
Count Pulse
Period
7C
7C
8 µs
6
~~
~~
up
-c
ou
nt
~~
7B
7A
5
4
3
2
1
0
0
TIME
Interrupt period
= 8 µs x (124+1)
Timer 0 (T0IF)
Interrupt
Occur interrupt
Occur interrupt
Occur interrupt
Figure 13-6 Timer Count Example
13.1.2 8-bit Event Counter Mode
In order to use event counter function, the bit 4, 5 of the
Port Selection Register PSR0(address 0F8H) is required to
be set to “1”.
In this mode, counting up is started by an external trigger.
This trigger means rising edge of the EC0 or EC1 pin input.
Source clock is used as an internal clock selected with timer mode register TM0 or TM2. The contents of timer data
register TDRn (n = 0,1,2,3) are compared with the contents
of the up-counter Tn. If a match is found, an timer interrupt
request flag TnIF is generated, and the counter is cleared to
“0”. The counter is restart and count up continuously by
every falling edge of the EC0 or EC1 pin input. The maximum frequency applied to the EC0 or EC1 pin is fXIN/2
[Hz].
After reset, the value of timer data register TDRn is initialized to "0", The interval period of Timer is calculated as
below equation.
1
Period (sec) = ----------- × 2 × Divide Ratio × (TDRn+1)
f XIN
Start count
~
~
ECn pin input
~
~
1
0
2
~
~
Up-counter
n-1
n
0
1
2
~
~
~
~
T1IF interrupt
n
~
~
TDR1
Figure 13-7 Event Counter Mode Timing Chart
50
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
TDR1
disable
~~
clear & start
enable
up
-c
o
un
t
stop
~~
TIME
Timer 1 (T1IF)
Interrupt
Occur interrupt
Occur interrupt
T1ST
Start & Stop
T1CN
Control count
T1ST = 1
T1ST = 0
T1CN = 1
T1CN = 0
Figure 13-8 Count Operation of Timer / Event counter
Mar. 2005 Ver 0.2
51
MC80F0104/0204
Preliminary
13.2 16-bit Timer / Counter Mode
The Timer register is being run with all 16 bits. A 16-bit
timer/counter register T0, T1 are incremented from 0000H
until it matches TDR0, TDR1 and then resets to 0000H.
The match output generates Timer 0 interrupt.
The clock source of the Timer 2 is selected either internal
or external clock by bit T2CK[2:0]. In 16-bit mode, the bits
T3CK[1:0] and 16BIT of TM3 should be set to "1" respectively as shown in Figure 13-10 .
The clock source of the Timer 0 is selected either internal
or external clock by bit T0CK[2:0]. In 16-bit mode, the bits
T1CK[1:0] and 16BIT of TM1 should be set to "1" respectively as shown in Figure 13-9 .
Even if the Timer 0 (including Timer 1) is used as a 16-bit
timer, the Timer 2 and Timer 3 can still be used as either
two 8-bit timer or one 16-bit timer by setting the TM3. Reversely, even if the Timer 2 (including Timer 3) is used as
a 16-bit timer, the Timer 0 and Timer 1 can still be used as
8-bit timer independently.
Likewise, A 16-bit timer/counter register T2, T3 are incremented from 0000H until it matches TDR2, TDR3 and then
resets to 0000H. The match output generates Timer 2 interrupt.
TM0
7
6
-
-
-
-
5
4
3
2
1
0
ADDRESS: 0D0H
INITIAL VALUE: --00 0000B
CAP0 T0CK2 T0CK1
BTCL T0CK0 T0CN T0ST
0
X
X
X
X
X
X means don’t care
7
TM1
6
5
4
3
2
1
0
ADDRESS: 0D2H
INITIAL VALUE: 00H
POL 16BIT PWM1E CAP1 T1CK1
BTCL T1CK0 T1CN T1ST
X
1
0
0
1
1
X
X
X means don’t care
T0CK[2:0]
EDGE
DETECTOR
EC0 PIN
111
÷2
÷4
Prescaler
XIN PIN
÷8
÷ 32
÷ 128
÷ 512
÷ 2048
T0ST
0: Stop
1: Clear and start
000
001
T1 + T0
(16-bit)
010
011
100
101
T0CN
T0IF
Comparator
110
MUX
clear
TIMER 0
INTERRUPT
(Not Timer 1 interrupt)
TDR1 + TDR0
(16-bit)
Higher byte Lower byte
COMPARE DATA
TIMER 0 + TIMER 1 → TIMER 0 (16-bit)
Figure 13-9 16-bit Timer/Counter for Timer 0, 1
52
Mar. 2005 Ver 0.2
Preliminary
TM2
7
6
-
-
-
-
5
4
3
2
MC80F0104/0204
1
0
ADDRESS: 0D6H
INITIAL VALUE: --000000B
CAP2 T2CK2 T2CK1
BTCL T2CK0 T2CN T2ST
0
X
X
X
X
X
X means don’t care
7
TM3
6
5
4
3
2
1
0
ADDRESS: 0D8H
INITIAL VALUE: 00H
POL 16BIT PWM3E CAP3 T3CK1
BTCL T3CK0 T3CN T3ST
X
1
0
0
1
1
X
X
X means don’t care
T2CK[2:0]
EDGE
DETECTOR
EC1 PIN
111
÷2
÷4
Prescaler
XIN PIN
÷8
÷ 16
÷ 64
÷ 256
÷ 1024
T2ST
0: Stop
1: Clear and start
000
001
T3 + T2
(16-bit)
010
011
100
101
clear
T2CN
T2IF
Comparator
110
TIMER 2
INTERRUPT
(Not Timer 3 interrupt)
TDR3 + TDR2
(16-bit)
MUX
Higher byte Lower byte
COMPARE DATA
TIMER 2 + TIMER 3 → TIMER 2 (16-bit)
Figure 13-10 16-bit Timer/Counter for Timer 2, 3
13.3 8-bit Compare Output (16-bit)
TheMC80F0104/0204 has Timer Compare Output function. To pulse out, the timer match can goes to port pin(
T0O or T2O) as shown in Figure 13-3 or Figure 13-4 .
Thus, pulse out is generated by the timer match. These operation is implemented to pin, R05/AN5//T0O/TXD or
R06/AN6/T2O/ACK.
output the signal having a 50 : 50 duty square wave, and
output frequency is same as below equation.
Oscillation Frequency
f COMP = ------------------------------------------------------------------------------------------2 × Prescaler Value × ( TDR + 1 )
In this mode, the bit T0OE or T2OE bit of Port Selection
register1 (PSR1.0 or PSR1.1) should be set to "1". This pin
13.4 8-bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer
mode register TM0 (bit CAP1 of timer mode register TM1
for Timer 1) as shown in Figure 13-11 . Likewise, the Tim-
Mar. 2005 Ver 0.2
er 2 capture mode is set by bit CAP2 of timer mode register
TM2 (bit CAP3 of timer mode register TM3 for Timer 3)
as shown in Figure 13-12 .
53
MC80F0104/0204
Preliminary
The Timer/Counter register is increased in response internal or external input. This counting function is same with
normal timer mode, and Timer interrupt is generated when
timer register T0 (T1, T2, T3) increases and matches
TDR0 (TDR1, TDR2, TDR3).
This timer interrupt in capture mode is very useful when
the pulse width of captured signal is more wider than the
maximum period of Timer.
For example, in Figure 13-14 , the pulse width of captured
signal is wider than the timer data value (FFH) over 2
times. When external interrupt is occurred, the captured
value (13H) is more little than wanted value. It can be obtained correct value by counting the number of timer overflow occurrence.
54
Timer/Counter still does the above, but with the added feature that a edge transition at external input INTx pin causes
the current value in the Timer x register (T0,T1,T2,T3), to
be captured into registers CDRx (CDR0, CDR1, CDR2,
CDR3), respectively. After captured, Timer x register is
cleared and restarts by hardware. It has three transition
modes: "falling edge", "rising edge", "both edge" which
are selected by interrupt edge selection register IEDS. Refer to “18.4 External Interrupt” on page 86. In addition, the
transition at INTn pin generate an interrupt.
Note: The CDRn and TDRn are in same address.In the capture
mode, reading operation is read the CDRn, not TDRn because
path is opened to the CDRn.
Mar. 2005 Ver 0.2
Preliminary
TM0
7
6
-
-
-
-
5
4
3
2
MC80F0104/0204
1
0
ADDRESS: 0D0H
INITIAL VALUE: --00 0000B
CAP0 T0CK2 T0CK1
BTCL T0CK0 T0CN T0ST
1
X
X
X
X
X
X means don’t care
7
TM1
6
5
4
3
2
1
0
ADDRESS: 0D2H
INITIAL VALUE: 00H
POL 16BIT PWM1E CAP1 T1CK1
BTCL T1CK0 T1CN T1ST
X
0
0
1
X
X
X
X
X means don’t care
T0CK[2:0]
Edge
Detector
EC0 PIN
111
T0ST
÷2
000
÷4
Prescaler
XIN PIN
0: Stop
1: Clear and start
001
÷8
T0 (8-bit)
010
÷ 32
011
÷ 128
100
÷ 512
÷ 2048
101
clear
T0CN
Capture
110
CDR0 (8-bit)
MUX
IEDS[1:0]
“01”
“10”
INT0 PIN
INT0IF
T1CK[1:0]
INT0
INTERRUPT
“11”
T1ST
÷1
÷2
÷8
0: Stop
1: Clear and start
11
00
T1 (8-bit)
01
clear
10
MUX
T1CN
Capture
CDR1 (8-bit)
IEDS[3:2]
“01”
INT1 PIN
“10”
INT1IF
INT1
INTERRUPT
“11”
Figure 13-11 8-bit Capture Mode for Timer 0, 1
Mar. 2005 Ver 0.2
55
MC80F0104/0204
Preliminary
TM2
7
6
-
-
-
-
5
4
3
2
1
0
ADDRESS: 0D6H
INITIAL VALUE: --00 0000B
CAP2 T2CK2 T2CK1
BTCL T2CK0 T2CN T2ST
1
X
X
X
X
X
X means don’t care
7
TM3
6
5
4
3
2
1
0
ADDRESS: 0D8H
INITIAL VALUE: 00H
POL 16BIT PWM3E CAP3 T3CK1
BTCL T3CK0 T3CN T3ST
X
0
0
1
X
X
X
X
X means don’t care
T2CK[2:0]
Edge
Detector
EC1 PIN
111
T2ST
÷2
000
÷4
Prescaler
XIN PIN
0: Stop
1: Clear and start
001
÷8
T2 (8-bit)
010
÷ 16
011
÷ 64
100
÷ 256
÷ 1024
101
clear
T2CN
Capture
110
CDR2 (8-bit)
MUX
IEDS[5:4]
“01”
“10”
INT2 PIN
INT2IF
T3CK[1:0]
INT2
INTERRUPT
“11”
T3ST
÷1
÷4
÷ 16
0: Stop
1: Clear and start
11
00
T3 (8-bit)
01
10
MUX
clear
T3CN
Capture
CDR3 (8-bit)
IEDS[7:6]
“01”
INT3 PIN
“10”
INT3IF
INT3
INTERRUPT
“11”
Figure 13-12 8-bit Capture Mode for Timer 2, 3
56
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
This value is loaded to CDR0
n
T0
n-1
co
un
t
~~
~~
9
8
up
-
7
6
5
4
~~
3
2
1
0
TIME
Ext. INT0 Pin
Interrupt Request
( INT0IF )
Interrupt Interval Period
Ext. INT0 Pin
Interrupt Request
( INT0IF )
20nS
Capture
( Timer Stop )
5nS
Delay
Clear & Start
Figure 13-13 Input Capture Operation of Timer 0 Capture mode
Ext. INT0 Pin
Interrupt Request
( INT0IF )
Interrupt Interval Period=01H+FFH +01H+FFH +01H+13H=214H
Interrupt Request
( T0IF )
FFH
FFH
T0
13H
00H
00H
Figure 13-14 Excess Timer Overflow in Capture Mode
Mar. 2005 Ver 0.2
57
MC80F0104/0204
Preliminary
13.5 16-bit Capture Mode
The clock source of the Timer 2 is selected either internal
or external clock by bit T2CK[2:0]. In 16-bit mode, the bits
T3CK1,T3CK0, CAP3 and 16BIT of TM3 should be set to
"1" respectively as shown in Figure 13-16 .
16-bit capture mode is the same as 8-bit capture, except
that the Timer register is being run will 16 bits. The clock
source of the Timer 0 is selected either internal or external
clock by bit T0CK[2:0]. In 16-bit mode, the bits T1CK1,
T1CK0, CAP1 and 16BIT of TM1 should be set to "1" respectively as shown in Figure 13-15 .
TM0
7
6
-
-
-
-
5
4
3
2
1
0
ADDRESS: 0D0H
INITIAL VALUE: --00 0000B
CAP0 T0CK2 T0CK1
BTCL T0CK0 T0CN T0ST
1
X
X
X
X
X
X means don’t care
7
TM1
6
5
4
3
2
1
0
ADDRESS: 0D2H
INITIAL VALUE: 00H
POL 16BIT PWM1E CAP1 T1CK1
BTCL T1CK0 T1CN T1ST
X
1
0
1
1
1
X
X
X means don’t care
T0CK[2:0]
Edge
Detector
EC0 PIN
111
T0ST
÷2
÷4
Prescaler
XIN PIN
÷8
÷ 32
÷ 128
÷ 512
÷ 2048
0: Stop
1: Clear and start
000
001
TDR1 + TDR0
(16-bit)
010
011
100
clear
T0CN
101
Capture
110
CDR1 + CDR0
(16-bit)
MUX
IEDS[1:0]
Higher byte Lower byte
CAPTURE DATA
“01”
INT0 PIN
“10”
INT0IF
INT0
INTERRUPT
“11”
Figure 13-15 16-bit Capture Mode of Timer 0, 1
58
Mar. 2005 Ver 0.2
Preliminary
TM2
7
6
-
-
-
-
5
4
3
2
MC80F0104/0204
1
0
ADDRESS: 0D6H
INITIAL VALUE: --00 0000B
CAP2 T2CK2 T2CK1
BTCL T2CK0 T2CN T2ST
1
X
X
X
X
X
X means don’t care
7
TM3
6
5
4
3
2
1
0
ADDRESS: 0D8H
INITIAL VALUE: 00H
POL 16BIT PWM3E CAP3 T3CK1
BTCL T3CK0 T3CN T3ST
X
1
1
0
1
1
X
X
X means don’t care
T2CK[2:0]
Edge
Detector
EC1 PIN
111
T2ST
÷2
÷4
Prescaler
XIN PIN
÷8
÷ 16
÷ 64
÷ 256
÷ 1024
0: Stop
1: Clear and start
000
001
TDR3 + TDR2
(16-bit)
010
011
clear
100
T2CN
101
Capture
110
CDR3 + CDR2
(16-bit)
MUX
IEDS[5:4]
Higher byte Lower byte
CAPTURE DATA
“01”
“10”
INT2 PIN
INT2IF
INT2
INTERRUPT
“11”
Figure 13-16 16-bit Capture Mode of Timer 2, 3
Example 1:
Example 3:
Timer0 = 16-bit timer mode, 0.5s at 4MHz
Timer0 = 16-bit capture mode
LDM
LDM
LDM
LDM
SET1
EI
:
:
TM0,#0000_1111B;8uS
TM1,#0100_1100B;16bit Mode
TDR0,#<62499
;8uS X 62500
TDR1,#>62499
;=0.5s
T0E
Example 2:
LDM
LDM
LDM
LDM
LDM
LDM
SET1
EI
:
:
PSR0,#0000_0001B;INT0 set
TM0,#0010_1111B;CaptureMode
TM1,#0100_1100B;16bit Mode
TDR0,#<0FFH
;
TDR1,#>0FFH
;
IEDS,#01H;Falling Edge
T0E
Timer0 = 16-bit event counter mode
LDM
LDM
LDM
LDM
LDM
SET1
EI
:
:
PSR0,#0001_0000B;EC0 Set
TM0,#0001_1111B;CounterMode
TM1,#0100_1100B;16bit Mode
TDR0,#<0FFH
;
TDR1,#>0FFH
;
T0E
Mar. 2005 Ver 0.2
59
MC80F0104/0204
Preliminary
13.6 PWM Mode
TheMC80F0104/0204 has high speed PWM (Pulse Width
Modulation) functions which shared with Timer1 or
Timer3.
In PWM mode, R10 / PWM1O or R11 / PWM3O pin output up to a 10-bit resolution PWM output. These pins
should be configured as a PWM output by setting "1" bit
PWM1OE and PWM3OE in PSR0 register.
The period of the PWM1 output is determined by the
T1PPR (T1 PWM Period Register) and T1PWHR[3:2]
(bit3,2 of T1 PWM High Register) and the duty of the
PWM output is determined by the T1PDR (T1 PWM Duty
Register) and T3PWHR[1:0] (bit1,0 of T1 PWM High
Register).
The period of the PWM3 output is determined by the
T3PPR (T3 PWM Period Register) and T3PWHR[3:2]
(bit3,2 of T3 PWM High Register) and the duty of the
PWM output is determined by the T3PDR (T3 PWM Duty
Register) and T3PWHR[1:0] (bit1,0 of T3 PWM High
Register).
The user writes the lower 8-bit period value to the
T1(3)PPR( and the higher 2-bit period value to the
T1(3)PWHR[3:2]. And writes duty value to the T1(3)PDR
and the T1(3)PWHR[1:0] same way.
The T1(3)PDR is configured as a double buffering for
glitchless PWM output. In Figure 13-18 , the duty data is
transferred from the master to the slave when the period
data matched to the counted value. (i.e. at the beginning of
next duty cycle)
PWM1(3) Period = [PWM1(3)HR[3:2]T(2)3PPR] X
Source Clock
PWM1(3) Duty = [PWM3HR[1:0]T3PDR] X Source
Clock
The relation of frequency and resolution is in inverse proportion. Table 13-3 shows the relation of PWM frequency
vs. resolution.
reduced resolution.
Frequency
Resolution
T1CK[1:0]
= 00(250nS)
T1CK[1:0]
= 01(500nS)
T1CK[1:0]
= 10(2uS)
10-bit
3.9kHz
0.98kHz
0.49kHz
9-bit
7.8kHz
1.95kHz
0.97kHz
8-bit
15.6kHz
3.90kHz
1.95kHz
7-bit
31.2kHz
7.81kHz
3.90kHz
Table 13-3 PWM Frequency vs. Resolution at 4MHz
The bit POL of TM1 or TM3 decides the polarity of duty
cycle.
If the duty value is set same to the period value, the PWM
output is determined by the bit POL (1: High, 0: Low). And
if the duty value is set to "00H", the PWM output is determined by the bit POL (1: Low, 0: High).
It can be changed duty value when the PWM output. However the changed duty value is output after the current period is over. And it can be maintained the duty value at
present output when changed only period value shown as
Figure 13-20 . As it were, the absolute duty time is not
changed in varying frequency. But the changed period value must greater than the duty value.
Note: If changing the Timer1 to PWM function, it should be stop
the timer clock firstly, and then set period and duty register value.
If user writes register values while timer is in operation, these register could be set with certain values.
Ex) Sample Program @4MHz 2uS
LDM
LDM
LDM
LDM
LDM
TM1,#1010_1000b ; Set Clock & PWM3E
T1PPR,#199
; Period :400uS=2uSX(199+1)
T1PDR,#99
; Duty:200uS=2uSX(99+1)
PWM1HR,00H
TM1,#1010_1011b ; Start timer1
If it needed more higher frequency of PWM, it should be
60
Mar. 2005 Ver 0.2
Preliminary
R/W
7
TM1
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
ADDRESS: 0D2H
INITIAL VALUE: 00H
POL 16BIT PWM1E CAP3 T3CK1
BTCL T3CK0 T3CN T3ST
T1PWHR
X
0
1
0
X
X
X
X
7
6
5
4
W
3
W
2
W
1
W
0
-
-
-
-
-
-
-
-
X:The value "0" or "1" corresponding your operation.
ADDRESS: 0D5H
INITIAL VALUE: ---- 0000B
T3PWHR3
BTCL T3PWHR2 T3PWHR1 T3PWHR0
X
X
X
MC80F0104/0204
Bit Manipulation Not Available
X
X:The value "0" or "1" corresponding your operation.
Period High
W
7
W
6
W
5
W
4
T1PPR
W
3
Duty High
W
2
W
1
W
0
R/W
2
R/W
1
R/W
0
ADDRESS: 0D3H
INITIAL VALUE: 0FFH
BTCL
R/W
7
R/W
6
R/W
5
R/W
4
T1PDR
R/W
3
ADDRESS: 0D4H
INITIAL VALUE: 00H
BTCL
T1PWHR[1:0]
T0 clock source
[T0CK]
T1CK[1:0]
0 : Stop
1 : Clear and Start
Prescaler
XIN PIN
÷2
÷8
Clear
00
R10 / PWM1O PIN
R
2-bit
01
T1(8-bit)
10
MUX
S Q
Comparator
11
÷1
PWM1OE
[PSR0.6]
T1PPR(8-bit)
T1ST
POL
T1CN
Comparator
Slave
T1PDR(8-bit)
T1PWHR[1:0]
Master
T1PDR(8-bit)
Figure 13-17 PWM1 Mode
Mar. 2005 Ver 0.2
61
MC80F0104/0204
Preliminary
R/W
7
TM3
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
ADDRESS: 0D8H
INITIAL VALUE: 00H
POL 16BIT PWM3E CAP3 T3CK1
BTCL T3CK0 T3CN T3ST
T3PWHR
X
0
1
0
X
X
X
X
7
6
5
4
W
3
W
2
W
1
W
0
-
-
-
-
-
-
-
-
X:The value "0" or "1" corresponding your operation.
ADDRESS: 0DBH
INITIAL VALUE: ---- 0000B
T3PWHR3
BTCL T3PWHR2 T3PWHR1 T3PWHR0
X
X
X
Bit Manipulation Not Available
X
X:The value "0" or "1" corresponding your operation.
Period High
W
7
W
6
W
5
W
4
T3PPR
W
3
Duty High
W
2
W
1
W
0
R/W
2
R/W
1
R/W
0
ADDRESS: 0D9H
INITIAL VALUE: 0FFH
BTCL
R/W
7
R/W
6
R/W
5
R/W
4
T3PDR
R/W
3
ADDRESS: 0DAH
INITIAL VALUE: 00H
BTCL
T3PWHR[1:0]
T2 clock source
[T2CK]
T3CK[1:0]
0 : Stop
1 : Clear and Start
Prescaler
XIN PIN
÷4
÷ 16
Clear
00
R
2-bit
01
R11 / PWM3O PIN
T3(8-bit)
10
MUX
S Q
Comparator
11
÷1
PWM3O
[PSR0.7]
T3PPR(8-bit)
T3ST
POL
T3CN
Comparator
Slave
T3PDR(8-bit)
T3PWHR[1:0]
Master
T3PDR(8-bit)
Figure 13-18 PWM3 Mode
62
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
~
~
~
~
Source
clock
01
02
03
04
PWM1E
7E
7F
~
~ ~
~
00
~
~ ~
~ ~
~
T1
80
3FF
00
01
02
~
~
T1ST
~
~
T1CN
~
~
PWM1O
[POL=1]
~
~
~
~
~
~
PWM1O
[POL=0]
Duty Cycle [ (1+7Fh) x 250nS = 32uS ]
Period Cycle [ (3FFh+1) x 250nS = 256uS, 3.9KHz ]
T1CK[1:0] = 00 ( XIN )
T1PWHR = 0CH
Period
T1PWHR3
1
T1PWHR2
T1PPR (8-bit)
1
FFH
T1PWHR0
T1PDR (8-bit)
0
7FH
T1PPR = FFH
T1PDR = 7FH
Duty
T1PWHR1
0
Figure 13-19 Example of PWM1 at 4MHz
T1CK[1:0] = 10 ( 1us )
PWM1HR = 00H
T1PPR = 0DH
Write T1PPR to 09H
T1PDR = 04H
Source
clock
T1
00 01 02 03 04 05 06 07 08
09 0A 0B 0C 0D
00 01 02 03 04 05 06 07 08 09
00 01 02 03
04
PWM1O
POL=1
Duty Cycle
[ (04h+1) x 2uS = 10uS ]
Period Cycle [ (1+0Dh) x 2uS = 28uS, 35.5KHz ]
Duty Cycle
[ (04h+1) x 2uS = 10uS ]
Duty Cycle
[ (04h+1) x 2uS = 10uS ]
Period Cycle [ (1+09h) x 2uS = 20uS, 50KHz ]
Figure 13-20 Example of Changing the PWM1 Period in Absolute Duty Cycle (@4MHz)
Mar. 2005 Ver 0.2
63
MC80F0104/0204
Preliminary
14. ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion
of an analog input signal to a corresponding 10-bit digital
value. The A/D module has ten (eight for MC80F0104) analog inputs, which are multiplexed into one sample and
hold. The output of the sample and hold is the input into the
converter, which generates the result via successive approximation.
The analog reference voltage is selected to VDD or AVref
by setting of the bit AVREFS in PSR1 register. If external
analog reference AVref is selected, the analog input channel 0 (AN0) should not be selected to use. Because this pin
is used to an analog reference of A/D converter.
The A/D module has three registers which are the control
register ADCM and A/D result register ADCRH and ADCRL. The ADCRH[7:6] is used as ADC clock source selection bits too. The register ADCM, shown in Figure 144 , controls the operation of the A/D converter module. The
port pins can be configured as analog inputs or digital I/O.
It is selected for the corresponding channel to be converted
by setting ADS[3:0]. The A/D port is set to analog input
port by ADEN and ADS[3:0] regardless of port I/O direction register. The port unselected by ADS[3:0] operates as
normal port.
Enable A/D Converter
How to Use A/D Converter
The processing of conversion is start when the start bit
ADST is set to “1”. After one cycle, it is cleared by hardware. The register ADCRH and ADCRL contains the results of the A/D conversion. When the conversion is
completed, the result is loaded into the ADCRH and ADCRL, the A/D conversion status bit ADSF is set to “1”, and
the A/D interrupt flag ADCIF is set. See Figure 14-1 for
operation flow.
The block diagram of the A/D module is shown in Figure
14-3 . The A/D status bit ADSF is set automatically when
A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes 13 times of
conversion source clock. The conversion source clock
should selected for the conversion time being more than
25µs.
A/D Converter Cautions
(1) Input range of AN0 ~ AN7, AN14 and AN15
The input voltage of A/D input pins should be within the
specification range. In particular, if a voltage above VDD
(or AVref) or below VSS is input (even if within the absolute maximum rating range), the conversion value for that
channel can not be indeterminate. The conversion values
of the other channels may also be affected.
(2) Noise countermeasures
In order to maintain 10-bit resolution, attention must be
paid to noise on pins VDD (or AVref) and analog input pins
(AN0 ~ AN7, AN14, AN15). Since the effect increases in
proportion to the output impedance of the analog input
source, it is recommended in some cases that a capacitor be
connected externally as shown in Figure 14-2 in order to
reduce noise. The capacitance is user-selectable and appropriately determined according to the target system.
A/D Input Channel Select
Conversion Source Clock Select
A/D Start (ADST = 1)
Analog
Input
NOP
0~1000pF
User Selectable
AN0~AN7
AN14, AN15
ADSF = 1
NO
YES
Read ADCR
Figure 14-2 Analog Input Pin Connecting Capacitor
Figure 14-1 A/D Converter Operation Flow
64
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
(3) I/O operation
the pin undergoing A/D conversion.
The analog input pins AN0 ~ AN7,AN14 and AN15 also
have function as input/output port pins. When A/D conversion is performed with any pin, be sure not to execute a
PORT input instruction with the selected pin while conversion is in progress, as this may reduce the conversion resolution.
(4) AVDD pin input impedance
A series resistor string of approximately 5KΩ is connected
between the AVREF pin and the VSS pin. Therefore, if the
output impedance of the analog power source is high, this
will result in parallel connection to the series resistor string
between the AVREF pin and the VSS pin, and there will be
a large analog supply voltage error
Also, if digital pulses are applied to a pin adjacent to the
pin in the process of A/D conversion, the expected A/D
conversion value may not be obtainable due to coupling
noise. Therefore, avoid applying pulses to pins adjacent to
AVREFS (PSR1.3)
ADEN
0
VDD
Resistor Ladder Circuit
1
AN0 / AVREF
AN1
Successive
MUX
Sample & Hold
ADC
INTERRUPT
ADCIF
Approximation
Circuit
AN7
AN14
ADC8
AN15
0
1
10-bit Mode
8-bit Mode
ADS[3:0] (ADCM[5:2])
98
98
ADCRADCR
(10-bit)
10-bit
32
10-bit ADCR
0 0
ADCRH
ADCRL (8-bit)
1 0
ADC Result Register
ADCRH
ADCRL (8-bit)
1 0
ADC Result Register
Figure 14-3 A/D Block Diagram
Mar. 2005 Ver 0.2
65
MC80F0104/0204
Preliminary
R/W R/W R/W
R
3
2
1
0
ADEN ADCK ADS3 ADS2 BTCL
ADS1 ADS0 ADST ADSF
R/W
7
ADCM
R/W
6
R/W
5
R/W
4
ADDRESS: 0EFH
INITIAL VALUE: 0000 0001B
A/D status bit
0: A/D conversion is in progress
1: A/D conversion is completed
A/D start bit
Setting this bit starts an A/D conversion.
After one cycle, bit is cleared to “0” by hardware.
Analog input channel select
0000: Channel 0 (AN0) 0110: Channel 6 (AN6)
0001: Channel 1 (AN1) 0111: Channel 7 (AN7)
0010: Channel 2 (AN2) 1000 ~ 1101: Not available
0011: Channel 3 (AN3) 1110: Channel 14 (AN14)
0100: Channel 4 (AN4) 1111: Channel 15 (AN15)
0101: Channel 5 (AN5)
A/D converter Clock Source Divide Ratio Selection bit
0: Clock Source fPS
1: Clock Source fPS ÷ 2
A/D converter Enable bit
0: A/D converter module turn off and current is not flow.
1: Enable A/D converter
ADCRH
W
W
7
6
W
5
PSSEL1 PSSEL0 ADC8
-
-
-
R
R
4
3
BTCL
-
2
1
0
-
-
ADDRESS: 0F0H
INITIAL VALUE: 010- ----B
A/D Conversion High Data
ADC 8-bit Mode select bit
0: 10-bit Mode
1: 8-bit Mode
R
7
R
5
R
6
ADCRL
R
4
R
3
BTCL
R
2
R
1
R
0
A/D Conversion Clock (fPS) Source Selection
00: fXIN ÷ 4
01: fXIN ÷ 8
10: fXIN ÷ 16
11: fXIN ÷ 32
ADDRESS: 0F1H
INITIAL VALUE: Undefined
A/D Conversion Low Data
ADCK
PSSEL1
PSSEL0
PS Clock Selection
0
0
0
PS = fXIN ÷ 4
0
0
1
PS = fXIN ÷ 8
0
0
0
PS = fXIN ÷ 16
0
0
1
PS = fXIN ÷ 32
1
1
0
PS = fXIN ÷ 8
1
1
1
PS = fXIN ÷ 16
1
1
0
PS = fXIN ÷ 32
1
1
1
PS = fXIN ÷ 64
PS : Conversion Clock
Figure 14-4 A/D Converter Control & Result Register
66
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
15. SERIAL INPUT/OUTPUT (SIO)
circuit as illustrated in Figure 15-1 . The SO pin is designed
to input and output. So the Serial I/O(SIO) can be operated
with minimum two pin. Pin R00/SCK, R01/SI, and R02/
SO pins are controlled by the Serial Mode Register. The
contents of the Serial I/O data register can be written into
or read out by software. The data in the Serial Data Register can be shifted synchronously with the transfer clock
signal.
The serial Input/Output is used to transmit/receive 8-bit
data serially. The Serial Input/Output (SIO) module is a serial interface useful for communicating with other peripheral of microcontroller devices. These peripheral devices
may be serial EEPROMs, shift registers, display drivers,
A/D converters, etc. This SIO is 8-bit clock synchronous
type and consists of serial I/O data register, serial I/O mode
register, clock selection circuit, octal counter and control
SIOST
SIOSF
clear
XIN PIN
Prescaler
SCK[1:0]
÷4
÷ 16
Timer0
Overflow
POL
Complete
Start
00
01
“0”
10
“1”
Clock
SIO
CONTROL
CIRCUIT
Clock
11
SCK PIN
“11”
MUX
overflow
Octal
Counter
(3-bit)
SIOIF
Serial communication
Interrupt
not “11”
SCK[1:0]
SM0
SO PIN
IOSW
SOUT
IOSW
1
SI PIN
Input shift register
0
Shift
SIOR
Internal Bus
Figure 15-1 SIO Block Diagram
Mar. 2005 Ver 0.2
67
MC80F0104/0204
Preliminary
Serial I/O Mode Register (SIOM) controls serial I/O function. According to SCK1 and SCK0, the internal clock or
external clock can be selected.
R/W
7
SIOM
R/W
6
R/W
5
POL IOSW SM1
R/W
4
Serial I/O Data Register (SIOR) is an 8-bit shift register.
First LSB is send or is received.
R/W R/W R/W R
3
2
1
0
SM0 BTCL
SCK1 SCK0 SIOST SIOSF
ADDRESS: 0E2H
INITIAL VALUE: 0000 0001B
Serial transmission status bit
0: Serial transmission is in progress
1: Serial transmission is completed
Serial transmission start bit
Setting this bit starts an Serial transmission.
After one cycle, bit is cleared to “0” by hardware.
Serial transmission Clock selection
00: fXIN ÷ 4
01: fXIN ÷ 16
10: TMR0OV(Timer0 Overflow)
11: External Clock
Serial transmission Operation Mode
00: Normal Port(R42,R43,R44)
01: Sending Mode(SCK,R43,SO)
10: Receiving Mode(SCK,SI,R44)
11: Sending & Receiving Mode(SCK,SI,SO)
Serial Input Pin Selection bit
0: SI Pin Selection
1: SO Pin Selection
Serial Clock Polarity Selection bit
0: Data Transmission at Falling Edge
Received Data Latch at Rising Edge
1: Data Transmission at Rising Edge
Received Data Latch at Falling Edge
SIOR
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
BTCL
ADDRESS: 0E3H
INITIAL VALUE: Undefined
Sending Data at Sending Mode
Receiving Data at Receiving Mode
Figure 15-2 SIO Control Register
15.1 Transmission/Receiving Timing
The serial transmission is started by setting SIOST(bit1 of
SIOM) to “1”. After one cycle of SCK, SIOST is cleared
automatically to “0”. At the default state of POL bit clear,
the serial output data from 8-bit shift register is output at
falling edge of SCLK, and input data is latched at rising
68
edge of SCLK pin (Refer to Figure 15-3 ). When transmission clock is counted 8 times, serial I/O counter is cleared
as ‘0”. Transmission clock is halted in “H” state and serial
I/O interrupt (SIOIF) occurred.
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
SIOST
SCK [R42]
(POL=0)
SO [P44]
D0
D1
D2
D3
D4
D5
D6
D7
SI [R43]
(IOSW=0)
D0
D1
D2
D3
D4
D5
D6
D7
IOSWIN [P44]
(IOSW=1)
D0
D1
D2
D3
D4
D5
D6
D7
SIOSF
(SIO Status)
SIOIF
(SIO Int. Req)
Figure 15-3 Serial I/O Timing Diagram at POL=0
SIOST
SCK [R42]
(POL=1)
SO [R44]
D0
D1
D2
D3
D4
D5
D6
D7
SI [R43]
(IOSW=0)
D0
D1
D2
D3
D4
D5
D6
D7
IOSWIN [R44]
(IOSW=1)
D0
D1
D2
D3
D4
D5
D6
D7
SIOSF
(SIO Status)
SIOIF
(SIO Int. Req)
Figure 15-4 Serial I/O Timing Diagram at POL=1
Mar. 2005 Ver 0.2
69
MC80F0104/0204
Preliminary
15.2 The usage of Serial I/O
1. Select transmission/receiving mode.
LDM
LDM
NOP
LDM
2. In case of sending mode, write data to be send to SIOR.
3. Set SIOST to “1” to start serial transmission.
4. The SIO interrupt is generated at the completion of SIO
and SIOIF is set to “1”. In SIO interrupt service routine,
correct transmission should be tested.
SIOR,#0AAh
SIOM,#0011_1100b
;set tx data
;set SIO mode
SIOM,#0011_1110b
;SIO Start
Note: When external clock is used, the frequency should be less
than 1MHz and recommended duty is 50%. If both transmission
mode is selected and transmission is performed simultaneously,
error may be occur.
5. In case of receiving mode, the received data is acquired
by reading the SIOR.
15.3 The Method to Test Correct Transmission
Serial I/O Interrupt
Service Routine
SIOSF
0
1
Abnormal
SIOE = 0
Write SIOM
SIOIF
0
1
Normal Operation
Overrun Error
- SIOE: Interrupt Enable Register High IENH(Bit1)
- SIOIF: Interrupt Request Flag Register High IRQH(Bit1)
Figure 15-5 Serial IO Method to Test Transmission
70
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
16. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)
16.1 UART Serial Interface Functions
The Universal Asynchronous Receiver / Transmitter
(UART) enables full-duplex operation wherein one byte of
data after the start bit is transmitted and received. The onchip baud rate generator dedicated to UART enables communications using a wide range of selectable baud rates. In
addition, a baud rate can also be defined by dividing clocks
input to the ACLK pin.
The UART driver consists of RXR, TXR, ASIMR, ASISR
and BRGCR register. Universal asynchronous serial I/O
mode (UART) can be selected by ASIMR register. Figure
16-1 shows a block diagram of the UART driver.
Internal Data Bus
Receive Buffer Register
(RXR)
RxE
Receive Shift Register
(RX)
RxD PIN
TxE
2
1
0
PE
FE
OVE
Transmit Shift Register
(TXR)
(ASISR)
Transmit Controller
(Parity Addition)
TxD PIN
Receive Controller
(Parity Check)
ACLK PIN
fXIN ÷2 ~ fXIN÷128
INT_TX
(UART tramsmit interrupt)
INT_RX
(UART receive interrupt)
Baud Rate
Generator
Figure 16-1 UART Block Diagram
Mar. 2005 Ver 0.2
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MC80F0104/0204
Preliminary
RECEIVE
RxE
ACLK PIN
MUX
5-bit counter
fXIN÷2 ~ fXIN÷128
match
÷2
(Divider)
Tx_Clock
÷2
(Divider)
Rx_Clock
Decoder
match
-
TPS2
TPS1 TPS0
MDL3 MDL2
MDL1 MDL0
(BRGCR)
5-bit counter
TxE
Internal Data Bus
SEND
Figure 16-2 Baud Rate Generator Block Diagram
16.2 Serial Interface Configuration
The UART interface consists of the following hardware.
Item
Configuration
Register
Transmit shift register (TXR)
Receive buffer register (RXR)
Receive shift register
Control
register
Serial interface mode register (ASIMR)
Serial interface status register (ASISR)
Baud rate generator control register (BRGCR)
Table 16-1 Serial Interface Configuration
Transmit shift register (TXR)
data is received, one byte of new receive data is transferred
from the receive shift register (RXSR). When the data
length is set as 7 bits, receive data is sent to bits 0 to 6 of
RXR. In this case, the MSB of RXR always becomes 0.
RXR can be read by an 8 bit memory manipulation instruction. It cannot be written. The RESET input sets RXR to
00H.
Receive shift register
This register converts serial data input via the RXD pin to
paralleled data. When one byte of data is received at this
register cannot be manipulated directly by a program.
Asynchronous serial interface mode register
(ASIMR)
This is the register for setting transmit data. Data written to
TXR is transmitted as serial data. When the data length is
set as 7 bit, bit 0 to 6 of the data written to TXR are transferred as transmit data. Writing data to TXR starts the
transmit operation.
TXR can be written by an 8 bit memory manipulation instruction. It cannot be read. The RESET input sets TXR to
0FFH.
This is an 8 bit register that controls UART serial transfer
operation. ASIMR is set by a 1 bit or 8 bit memory manipulation intruction. The RESET input sets ASIMR to
0000_-00-B. Figure 16-3 shows the format of ASIMR The
RXD / R04 and TXD / R05 pin function selection is shown
in Table 16-2.
Receive buffer register (RXR)
Note: Do not switch the operation mode until the current serial
This register is used to hold receive data. When one byte of
72
transmit/receive operation has stopped.
Mar. 2005 Ver 0.2
Preliminary
R/W
7
ASIMR
R/W
6
TXE
RXE
R/W
5
PS1
R/W
4
3
PS0 BTCL
-
R/W
2
SL
R/W
1
ISRM
0
-
MC80F0104/0204
ADDRESS: 0E6H
INITIAL VALUE: 0000 -00-B
UART Receive interrupt request is issued when an error occurs bit
0: Receive Completion Interrupt Control When Error occurs
1: Receive completion interrupt request is not issued when an error occur
UART Stop Bit Length for Specification for Transmit Data bit
0: 1 bit
1: 2 bit
UART Parity Bit Specification bit
00: No parity
01: Zero parity always added during transmission.
No parity detection during reception (parity errors do not occur)
10: Odd parity
11: Even parity
UART Tx/Rx Enable bit
00: Not used UART
01: UART Receive only Mode
10: UART Transmit only Mode
11: UART Receive & Transmit Mode
Figure 16-3 Asynchronous Serial Interface Mode register (ASIMR) Format
TXE (ASIMR.7)
RXE(ASIMR.6)
EC0(PSR0.4)
Operation Mode
RXD/R04
TXD/R05
0
0
X1
Operation Stop
R04
R05
0
1
0
UART mode (Receive only)
RXD
R05
1
0
X
UART mode (Transmit only)
R04
TXD
1
1
0
UART mode (Transmit and receive)
RXD
TXD
Table 16-2 UART mode and RXD/TXD pin function
1. X:The value "0" or "1" corresponding your operation
Mar. 2005 Ver 0.2
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MC80F0104/0204
Preliminary
Asynchronous serial interface status register (ASISR)
When a receive error occurs during UART mode, this register indicates the type of error. ASISR can be read by an 8
bit memory manipulation instruction. The RESET input
ASISR
7
6
5
4
-
-
-
-
3
BTCL
-
sets ASISR to ----_-000B. Figure 16-4 shows the format
of ASISR..
R
2
R
1
PE
FE
R
0
OVE
ADDRESS: 0E7H
INITIAL VALUE: ---- -000B
UART Parity Error Flag
0: No parity error
1: Parity error (Transmit data parity not matched)
UART Frame Error Flag
0: No Frame error
1: Framing errorNote1 (stop bit not detected)
UART Overrun Error Flag
0: No overrun error
1: Overrun errorNote2
(Next receive operation was completed before data was read
from receive buffer register (RXR))
Note 1. Even if a stop bit length is set to 2 bits by setting bit2(SL) in
ASIMR, stop bit detection during a recive operation only applies
to a stop bit length of 1bit.
2. Be sure to read the contents of the receive buffer register(RXR)
when an overrun error has occurred.
Until the contents of RXR are read, futher overrun errors will
occur when receiving data.
Figure 16-4 Asynchronous Serial Interface Status Register (ASISR) Format
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Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
Baud rate generator control register (BRGCR)
This register sets the serial clock for serial interface.
BRGCR is set by an 8 bit memory manipulation instruction. The RESET input sets BRGCR to -001_0000B.
7
BRGCR
-
R/W
6
R/W
5
R/W
4
Figure 16-5 shows the format of BRGCR.
R/W R/W R/W
R/W
3
2
1
0
TPS2 TPS1 TPS0 BTCL
MDL3 MDL2 MDL1 MDL0
ADDRESS: 0E8H
INITIAL VALUE: -001 0000B
UART Input Clock Selection
0000: fSCK ÷ 16
0001: fSCK ÷ 17
0010: fSCK ÷ 18
0011: fSCK ÷ 19
0100: fSCK ÷ 20
0101: fSCK ÷ 21
0110: fSCK ÷ 22
0111: fSCK ÷ 23
1000: fSCK ÷ 24
1001: fSCK ÷ 25
1010: fSCK ÷ 26
1011: fSCK ÷ 27
1100: fSCK ÷ 28
1101: fSCK ÷ 29
1110: fSCK ÷ 30
1111: Setting prohibited
UART Source Clock Selection for 5 bit count
000: ACLK
001: fXIN ÷ 2
010: fXIN ÷ 4
011: fXIN ÷ 8
100: fXIN ÷ 16
101: fXIN ÷ 32
110: fXIN ÷ 64
111: fXIN ÷ 128
Caution Writing to BRGCR during a communication operation may cause abnormal output from the baud rate generator and
disable further communication operations. Therefore, do not write to BRGCR during a communication operation.
Remarks 1. fSCK : Source clock for 5 bit counter
Figure 16-5 Baud Rate Generator Control Register (BRGCR) Format
Mar. 2005 Ver 0.2
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MC80F0104/0204
Preliminary
16.3 Communication operation
Once reception of one data frame is completed, a receive
completion interrupt request (INT_RX) occurs. Even if an
error has occurred, the receive data in which the error occurred is still transferred to RXR. When ASIMR bit 1 (ISRM) is cleared to 0 upon occurrence of an error, and
INT_RX occurs. When ISRM bit is set to 1, INT_RX does
not occur in case of error occurrence. Figure 16-6 shows
the timing of the asynchronous serial interface receive
completion interrupt request.
The transmit operation is enabled when bit 7 (TXE) of the
asynchronous serial interface mode register (ASIMR) is
set to 1. The transmit operation is started when transmit
data is written to the transmit shift register (TXR). The timing of the transmit completion interrupt request is shown in
Figure 16-6 .
The receive operation is enabled when bit 6 (RXE) of the
asynchronous serial interface mode register (ASIMR) is
set to 1, and input via the RxD pin is sampled. The serial
clock specified by ASIMR is used to sample the RxD pin.
1. Stop bit Length : 1 bit
TxD
RxD
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
D6
D7
Parity
D6
D7
Stop
Stop
character bits
TX
INTERRUPT
RX
INTERRUPT
2. Stop bit Length : 2 bit
TxD
RxD
1 data frame
Start
D0
D1
D2
D3
D4
D5
Stop
character bits
TX
INTERRUPT
RX
INTERRUPT
3. Stop bit Length : 1 bit, No parity
1 data frame
TxD
RxD
Start
D0
D1
D2
D3
D4
D5
character bits
TX
INTERRUPT
RX
INTERRUPT
1 data frame consists of following bits.
- Start bit : 1 bit
- Character bits : 8 bits
- Parity bit : Even parity, Odd parity, Zero parity, No parity
- Stop bit(s) : 1 bit or 2 bits
Figure 16-6 UART data format and interrupt timing diagram
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Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
16.4 Relationship between main clock and baud rate
The transmit/receive clock that is used to generate the baud
rate is obtained by dividing the main system clock. Transmit/Receive clock generation for baud rate is made by us-
Baud Rate
(bps)
600
fXIN=11.05
92M
fXIN=10.0M
ing main system clock which is divided. The baud rate
generated from the main system clock is determined according to the following formula.
fXIN=8.0M
fXIN=4.0M
fXIN=2.0M
BRGCR
ERR(%)
BRGCR
ERR(%)
BRGCR
ERR(%)
BRGCR
ERR
(%)
BRGCR
ERR(%)
-
-
-
-
-
-
7AH
0.16
6AH
0.16
1200
-
-
-
-
7AH
0.16
6AH
0.16
5AH
0.16
2400
72H
0.00
70H
1.73
6AH
0.16
5AH
0.16
4AH
0.16
4800
62H
0.00
60H
1.73
5AH
0.16
4AH
0.16
3AH
0.16
9600
52H
0.00
50H
1.73
4AH
0.16
3AH
0.16
2AH
0.16
19200
42H
0.00
40H
1.73
3AH
0.16
2AH
0.16
1AH
0.16
31250
36H
0.53
34H
0.00
30H
0.00
20H
0.00
10H
0.00
38400
32H
0.00
30H
1.73
2AH
0.16
1AH
0.16
-
-
57600
28H
0.00
26H
1.35
21H
2.11
11H
2.12
-
-
76800
22H
0.00
20H
1.73
1AH
0.16
-
-
-
-
115200
18H
0.00
16H
1.36
11H
2.12
-
-
-
-
Baud Rate = fXIN ÷ ( 2n+1(k+16) )
Remarks 1. fXIN : Main system clock oscillation frequency
When ACLK is selected as the source clock of the 5-bit counter,
substitute the input clock frequency to ACLK pin for in the above expression.
2. fSCK : Source clock for 5 bit counter
3. n : Value set via TPS0 to TPS2 ( 0 ≤ n ≤ 7 )
4. k : Source clock for 5 bit counter ( 0 ≤ k ≤ 14 )
Figure 16-7 Relationship between main clock and Baud Rate
Mar. 2005 Ver 0.2
77
MC80F0104/0204
Preliminary
17. BUZZER FUNCTION
The buzzer driver block consists of 6-bit binary counter,
buzzer register BUZR, and clock source selector. It generates square-wave which has very wide range frequency
(488Hz ~ 250kHz at fXIN= 4MHz) by user software.
The bit 0 to 5 of BUZR determines output frequency for
buzzer driving.
Equation of frequency calculation is shown below.
f XIN
f BUZ = -------------------------------------------------------------------------------2 × DivideRatio × ( BUR + 1 )
A 50% duty pulse can be output to R13 / BUZO pin to use
for piezo-electric buzzer drive. Pin R13 is assigned for output port of Buzzer driver by setting the bit 2 of PSR1(address 0F9H) to “1”. For PSR1 register, refer to Figure 17-2
.
fBUZ: Buzzer frequency
fXIN: Oscillator frequency
Divide Ratio: Prescaler divide ratio by BUCK[1:0]
BUR: Lower 6-bit value of BUZR. Buzzer period value.
Example: 5kHz output at 4MHz.
LDM
LDM
BUZR,#0011_0001B
PSR1,#XXXX_X1XXB
The frequency of output signal is controlled by the buzzer
control register BUZR. The bit 0 to bit 5 of BUZR determine output frequency for buzzer driving.
X means don’t care
R13 port data
Prescaler
÷8
XIN PIN
6-BIT BINARY
COUNTER
00
÷ 16
01
÷ 32
MUX
0
10
÷ 64
F/F
11
R12/BUZO PIN
1
Comparator
MUX
2
Compare data
BUZO
6
PSR1
BUR
Port selection register 1
[0F9H]
[0E0H]
Internal bus line
Figure 17-1 Block Diagram of Buzzer Driver
ADDRESS: 0E0H
RESET VALUE: 0FFH
W
BUZR
W
W
W
W
W
W
ADDRESS: 0F9H
RESET VALUE: ---- 0000B
W
PSR1
BUCK1 BUCK0
-
-
BUR[5:0]
Buzzer Period Data
Source clock select
00: fXIN ÷ 8
01: fXIN ÷ 16
10: fXIN ÷ 32
11: fXIN ÷ 64
-
-
-
BUZO
-
-
R12 / BUZO Selection
0: R12 port (Turn off buzzer)
1: BUZO port (Turn on buzzer)
Figure 17-2 Buzzer Register & PSR1
78
Mar. 2005 Ver 0.2
Preliminary
The 6-bit counter is cleared and starts the counting by writing signal at BUZR register. It is incremental from 00H until it matches 6-bit BUR value.
BUR
[5:0]
BUR[7:6]
00
01
10
11
MC80F0104/0204
When main-frequency is 4MHz, buzzer frequency is
shown as below Table 17-1.
BUR
[5:0]
BUR[7:6]
00
01
10
11
00
01
02
03
04
05
06
07
250.000
125.000
83.333
62.500
50.000
41.667
35.714
31.250
125.000
62.500
41.667
31.250
25.000
20.833
17.857
15.625
62.500
31.250
20.833
15.625
12.500
10.417
8.929
7.813
31.250
15.625
10.417
7.813
6.250
5.208
4.464
3.906
20
21
22
23
24
25
26
27
7.576
7.353
7.143
6.944
6.757
6.579
6.410
6.250
3.788
3.676
3.571
3.472
3.378
3.289
3.205
3.125
1.894
1.838
1.786
1.736
1.689
1.645
1.603
1.563
0.947
0.919
0.893
0.868
0.845
0.822
0.801
0.781
08
09
0A
0B
0C
0D
0E
0F
27.778
25.000
22.727
20.833
19.231
17.857
16.667
15.625
13.889
12.500
11.364
10.417
9.615
8.929
8.333
7.813
6.944
6.250
5.682
5.208
4.808
4.464
4.167
3.906
3.472
3.125
2.841
2.604
2.404
2.232
2.083
1.953
28
29
2A
2B
2C
2D
2E
2F
6.098
5.952
5.814
5.682
5.556
5.435
5.319
5.208
3.049
2.976
2.907
2.841
2.778
2.717
2.660
2.604
1.524
1.488
1.453
1.420
1.389
1.359
1.330
1.302
0.762
0.744
0.727
0.710
0.694
0.679
0.665
0.651
10
11
12
13
14
15
16
17
14.706
13.889
13.158
12.500
11.905
11.364
10.870
10.417
7.353
6.944
6.579
6.250
5.952
5.682
5.435
5.208
3.676
3.472
3.289
3.125
2.976
2.841
2.717
2.604
1.838
1.736
1.645
1.563
1.488
1.420
1.359
1.302
30
31
32
33
34
35
36
37
5.102
5.000
4.902
4.808
4.717
4.630
4.545
4.464
2.551
2.500
2.451
2.404
2.358
2.315
2.273
2.232
1.276
1.250
1.225
1.202
1.179
1.157
1.136
1.116
0.638
0.625
0.613
0.601
0.590
0.579
0.568
0.558
18
19
1A
1B
1C
1D
1E
1F
10.000
9.615
9.259
8.929
8.621
8.333
8.065
7.813
5.000
4.808
4.630
4.464
4.310
4.167
4.032
3.906
2.500
2.404
2.315
2.232
2.155
2.083
2.016
1.953
1.250
1.202
1.157
1.116
1.078
1.042
1.008
0.977
38
39
3A
3B
3C
3D
3E
3F
4.386
4.310
4.237
4.167
4.098
4.032
3.968
3.907
2.193
2.155
2.119
2.083
2.049
2.016
1.984
1.953
1.096
1.078
1.059
1.042
1.025
1.008
0.992
0.977
0.548
0.539
0.530
0.521
0.512
0.504
0.496
0.488
Table 17-1 buzzer frequency (kHz unit)
Mar. 2005 Ver 0.2
79
MC80F0104/0204
Preliminary
18. INTERRUPTS
tored to only if the interrupt was transition-activated.
TheMC80F0104/0204 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags
of IRQH, IRQL, Priority circuit, and Master enable flag
(“I” flag of PSW). Fifteen interrupt sources are provided.
The configuration of interrupt circuit is shown in Figure
18-1 and interrupt priority is shown in Table 18-1.
The Timer 0 ~ Timer 3 Interrupts are generated by T0IF,
T1IF, T2IF and T3IF which is set by a match in their respective timer/counter register.
The Basic Interval Timer Interrupt is generated by BITIF
which is set by an overflow in the timer register.
The External Interrupts INT0 ~ INT3 each can be transition-activated (1-to-0 or 0-to-1 transition) by selection
IEDS register.
The flags that actually generate these interrupts are bit
INT0IF, INT1IF, INT2IF and INT3IF in register IRQH.
When an external interrupt is generated, the generated flag
is cleared by the hardware when the service routine is vec-
The AD converter Interrupt is generated by ADCIF which
is set by finishing the analog to digital conversion.
The Watchdog timer is generated by WDTIF and WTIF
which is set by a match in Watchdog timer register.
Internal bus line
[0EAH]
IENH
IRQH
[0ECH]
INT0
INT0IF
INT1
INT1IF
INT2
INT2IF
INT3
Interrupt Enable
Register (Higher byte)
Release STOP/SLEEP
UARTRIF
UART Tx
UARTTIF
Serial
Communication
Timer 0
Priority Control
INT3IF
UART Rx
SIOIF
T0IF
IRQL
[0EDH]
Timer 1
T1IF
Timer 2
T2IF
Timer 3
T3IF
A/D Converter
ADCIF
Watchdog Timer
WDTIF
BIT
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction. When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
To CPU
I-flag
Interrupt Master
Enable Flag
Interrupt
Vector
Address
Generator
BITIF
[0EBH]
IENL
Interrupt Enable
Register (Lower byte)
Internal bus line
Figure 18-1 Block Diagram of Interrupt
80
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
The Basic Interval Timer Interrupt is generated by BITIF
which is set by a overflow in the timer counter register.
Reset/Interrupt
The UART receive or transmit interrupts are generated by
UARTRIF or UARTTIF are set by completion of UART
data reception or transmission.
Hardware Reset
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
UART Rx Interrupt
UART Tx Interrupt
Serial Input/Output
Timer/Counter 0
Timer/Counter 1
Timer/Counter 2
Timer/Counter 3
ADC Interrupt
Watchdog Timer
Basic Interval Timer
The SIO interrupt is generated by SIOIF which is set by
completion of SIO data reception or transmission.
The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW on Figure 8-3 ), the interrupt enable register (IENH, IENL), and the interrupt request flags
(in IRQH and IRQL) except Power-on reset and software
BRK interrupt. The Table 18-1 shows the Interrupt priority.
Vector addresses are shown in Figure 8-6 . Interrupt enable
registers are shown in Figure 18-2 . These registers are
composed of interrupt enable flags of each interrupt source
and these flags determines whether an interrupt will be accepted or not. When enable flag is “0”, a corresponding interrupt source is prohibited. Note that PSW contains also a
master enable bit, I-flag, which disables all interrupts at
once.
R/W
IENH
INT0E
R/W
R/W
R/W
R/W
R/W
Symbol
Priority
RESET
INT0
INT1
INT2
INT3
INT_RX
INT_TX
SIO
Timer 0
Timer 1
Timer 2
Timer 3
ADC
WDT
BIT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Table 18-1 Interrupt Priority
R/W
INT1E INT2E INT3E UARTRE UARTTE SIOE
R/W
ADDRESS: 0EAH
INITIAL VALUE: 0000 0000B
T0E
MSB
LSB
Timer/Counter 0 interrupt enable flag
Serial Communication interrupt enable flag
UART Tx interrupt enable flag
UART Rx interrupt enable flag
External interrupt 0 enable flag
External interrupt 1 enable flag
External interrupt 2 enable flag
External interrupt 3 enable flag
IENL
R/W
R/W
R/W
R/W
T1E
T2E
T3E
-
MSB
R/W
R/W
ADCE WDTE
R/W
R/W
-
BITE
LSB
ADDRESS: 0EBH
INITIAL VALUE: 000- 00-0B
Basic Interval Timer interrupt enable flag
Watchdog timer interrupt enable flag
A/D Converter interrupt enable flag
Timer/Counter 3 interrupt enable flag
Timer/Counter 2 interrupt enable flag
Timer/Counter 1 interrupt enable flag
Figure 18-2 Interrupt Enable Flag Register
Mar. 2005 Ver 0.2
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MC80F0104/0204
Preliminary
R/W
IRQH
R/W
R/W
R/W
R/W
R/W
R/W
INT0IF INT1IF INT2IF INT3IF UARTRIF UARTTIF SIOIF
R/W
T0IF
MSB
LSB
ADDRESS: 0ECH
INITIAL VALUE: 0000 0000B
Timer/Counter 0 interrupt request flag
Serial Communication interrupt request flag
UART Txx interrupt request flag
UART Rx interrupt request flag
External interrupt 3 request flag
External interrupt 2 request flag
External interrupt 1 request flag
External interrupt 0 request flag
IRQL
R/W
R/W
R/W
-
T1IF
T2IF
T3IF
-
R/W
R/W
ADCIF WDTIF
-
R/W
-
BITIF
LSB
MSB
ADDRESS: 0EDH
INITIAL VALUE: 000- 00-0B
Basic Interval Timer interrupt request flag
Watchdog timer interrupt request flag
A/D Converter interrupt request flag
Timer/Counter 3 interrupt request flag
Timer/Counter 2 interrupt request flag
Timer/Counter 1 interrupt request flag
Figure 18-3 Interrupt Request Flag Register
18.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted
or the interrupt latch is cleared to “0” by a reset or an instruction. Interrupt acceptance sequence requires 8 cycles
of fXIN (2µs at fXIN=4MHz) after the completion of the
current instruction execution. The interrupt service task is
terminated upon execution of an interrupt return instruction [RETI].
18.1.1 Interrupt acceptance
1. The interrupt master enable flag (I-flag) is cleared to
“0” to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following
interrupts is temporarily disabled.
2. Interrupt request flag for the interrupt source accepted is
cleared to “0”.
and the program status word are saved (pushed) onto the
stack area. The stack pointer decreases 3 times.
4. The entry address of the interrupt service program is
read from the vector table address and the entry address
is loaded to the program counter.
5. The instruction stored at the entry address of the interrupt service program is executed.
3. The contents of the program counter (return address)
82
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
System clock
Instruction Fetch
SP
Address Bus
PC
Data Bus
Not used
SP-1
PCH
PCL
SP-2
PSW
V.L.
V.L.
V.H.
ADL
New PC
ADH
OP code
Internal Read
Internal Write
Interrupt Processing Step
Interrupt Service Task
V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.
Figure 18-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
Basic Interval Timer
Vector Table Address
0FFE0H
0FFE1H
012H
0E3H
Entry Address
0E312H
0E313H
0EH
2EH
A interrupt request is not accepted until the I-flag is set to
“1” even if a requested interrupt has higher priority than
that of the current interrupt being serviced.
When nested interrupt service is required, the I-flag should
be set to “1” by “EI” instruction in the interrupt service
program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
Correspondence between vector table address for BIT interrupt
and the entry address of the interrupt service program.
18.1.2 Saving/Restoring General-purpose Register
During interrupt acceptance processing, the program
counter and the program status word are automatically
saved on the stack, but accumulator and other registers are
not saved itself. These registers are saved by the software
if necessary. Also, when multiple interrupt services are
nested, it is necessary to avoid using the same data memory
area for saving registers.
The following method is used to save/restore the generalpurpose registers.
Example: Register save using push and pop instruc-
tions
INTxx:
PUSH
PUSH
PUSH
A
X
Y
;SAVE ACC.
;SAVE X REG.
;SAVE Y REG.
interrupt processing
POP
POP
POP
RETI
Y
X
A
;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN
General-purpose register save/restore using push and pop
instructions;
Mar. 2005 Ver 0.2
83
MC80F0104/0204
Preliminary
main task
acceptance of
interrupt
interrupt
service task
saving
registers
restoring
registers
interrupt return
18.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction,
which has the lowest priority order.
Interrupt vector address of BRK is shared with the vector
of TCALL 0 (Refer to Program Memory Section). When
BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0.
Each processing step is determined by B-flag as shown in
Figure 18-5 .
=0
B-FLAG
BRK or
TCALL0
=1
BRK
INTERRUPT
ROUTINE
TCALL0
ROUTINE
RETI
RET
Figure 18-5 Execution of BRK/TCALL0
18.3 Multi Interrupt
If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same
time simultaneously, an internal polling sequence determines by hardware which request is serviced. However,
84
multiple processing through software for special features is
possible. Generally when an interrupt is accepted, the Iflag is cleared to disable any further interrupt. But as user
sets I-flag in interrupt routine, some further interrupt can
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
be serviced even if certain interrupt is in progress.
Main Program
service
TIMER 1
service
enable INT0
disable other
INT0
service
EI
Occur
TIMER1 interrupt
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable “EI” in the TIMER1 routine.
Occur
INT0
enable INT0
enable other
Figure 18-6 Execution of Multi Interrupt
Example: During Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend.
TIMER1: PUSH
PUSH
PUSH
LDM
LDM
EI
:
:
A
X
Y
IENH,#80H
IENL,#0
Mar. 2005 Ver 0.2
;Enable INT0 only
;Disable other int.
;Enable Interrupt
:
:
:
:
LDM
LDM
POP
POP
POP
RETI
IENH,#0FFH ;Enable all interrupts
IENL,#0FFH
Y
X
A
85
MC80F0104/0204
Preliminary
18.4 External Interrupt
The external interrupt on INT0, INT1, INT2 and INT3 pins
are edge triggered depending on the edge selection register
IEDS (address 0EEH) as shown in Figure 18-7 .
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, and both edge.
01
INT0 pin
10
INT0IF
INT0 INTERRUPT
INT1IF
INT1 INTERRUPT
INT2IF
INT2 INTERRUPT
INT3IF
INT3 INTERRUPT
11
01
INT1 pin
10
11
01
INT2 pin
10
11
01
INT3 pin
10
11
2
2
2
IEDS
2
Edge selection
Register
[0EEH]
Figure 18-7 External Interrupt Block Diagram
INT0 ~ INT3 are multiplexed with general I/O ports (R11,
R12, R03, R00). To use as an external interrupt pin, the bit
of port selection register PSR0 should be set to “1” correspondingly.
Example: To use as an INT0 and INT2
:
;**** Set external interrupt port as pull-up state.
LDM
PU1,#0000_0101B
;
;**** Set port as an external interrupt port
LDM
PSR0,#0000_0101B
;
;**** Set Falling-edge Detection
LDM
IEDS,#0001_0001B
:
max. 12 fXIN
Interrupt Interrupt
goes
latched
active
Response Time
The INT0 ~ INT3 edge are latched into INT0IF ~ INT3IF
at every machine cycle. The values are not actually polled
by the circuitry until the next machine cycle. If a request is
active and conditions are right for it to be acknowledged, a
hardware subroutine call to the requested service routine
will be the next instruction to be executed. The DIV itself
takes twelve cycles. Thus, a minimum of twelve complete
machine cycles elapse between activation of an external
interrupt request and the beginning of execution of the first
instruction of the service routine.
Figure 18-8 shows interrupt response timings.
8 fXIN
Interrupt
processing
Interrupt
routine
Figure 18-8 Interrupt Response Timing Diagram
86
Mar. 2005 Ver 0.2
Preliminary
MSB
W
IEDS
W
W
W
W
W
MC80F0104/0204
W
LSB
W
IED3H IED3L IED2H IED2L IED1H
BTCL IED1L IED0H IED0L
INT3
INT2
INT1
ADDRESS: 0EEH
INITIAL VALUE: 00H
INT0
Edge selection register
00: Reserved
01: Falling (1-to-0 transition)
10: Rising (0-to-1 transition)
11: Both (Rising & Falling)
W
PSR0
W
W
PWM3O PWM1O EC1E
MSB
0: R11
1: PWM3O
W
W
W
W
W
EC0E BTCL
INT3E INT2E INT1E INT0E
ADDRESS: 0F8H
INITIAL VALUE: 00H
LSB
0: R11
1: INT0
0: R10
1: PWM1O
0: R07
1: EC1
0: R12
1: INT1
0: R04
1: EC0
0: R00
1: INT3
0: R03
1: INT2
Figure 18-9 IEDS register and Port Selection Register PSR0
Mar. 2005 Ver 0.2
87
MC80F0104/0204
Preliminary
19. POWER SAVING OPERATION
shows the status of each Power Saving Mode. SLEEP
mode is entered by the SSCR register to “0Fh”., and STOP
mode is entered by STOP instruction after the SSCR register to “5Ah”.
TheMC80F0104/0204 has two power-down modes. In
power-down mode, power consumption is reduced
considerably. For applications where power consumption
is a critical factor, device provides two kinds of power saving functions, STOP mode and SLEEP mode. Table 19-1
19.1 Sleep Mode
released by interrupt, interrupt should be enabled before
SLEEP mode.
In this mode, the internal oscillation circuits remain active.
Oscillation continues and peripherals are operate normally
but CPU stops. Movement of all peripherals is shown in
Table 19-1. SLEEP mode is entered by setting the SSCR
register to “0Fh”. It is released by Reset or interrupt. To be
W
7
W
6
W
5
W
4
W
3
SSCR
W
2
W
1
W
0
ADDRESS: 0F5H
INITIAL VALUE: 0000 0000B
Power Down Control
5AH: STOP mode
0FH: SLEEP mode
NOTE :
To get into STOP mode, SSCR must be set to 5AH just before STOP instruction execution.
At STOP mode, Stop & Sleep Control Register (SSCR) value is cleared automatically when released.
To get into SLEEP mode, SSCR must be set to 0FH.
Figure 19-1 STOP and SLEEP Control Register
Release the SLEEP mode
The exit from SLEEP mode is hardware reset or all interrupts. Reset re-defines all the Control registers but does not
change the on-chip RAM. Interrupts allow both on-chip
RAM and Control registers to retain their values.
If I-flag = 1, the normal interrupt response takes place. If Iflag = 0, the chip will resume execution starting with the
instruction following the SLEEP instruction. It will not
vector to interrupt service routine. (refer to Figure 19-4 )
When exit from SLEEP mode by reset, enough oscillation
88
stabilizing time is required to normal operation. Figure 193 shows the timing diagram. When released from the
SLEEP mode, the Basic interval timer is activated on
wake-up. It is increased from 00H until FFH. The count
overflow is set to start normal operation. Therefore, before
SLEEP instruction, user must be set its relevant prescaler
divide ratio to have long enough time (more than 20msec).
This guarantees that oscillator has started and stabilized.
By interrupts, exit from SLEEP mode is shown in Figure
19-2 . By reset, exit from SLEEP mode is shown in Figure
19-3 .
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
.
~
~
~ ~
~
~
Internal Clock
~ ~
~
~
~ ~
~
~
Oscillator
(XIN pin)
SLEEP Instruction
Executed
Normal Operation
SLEEP Operation
~
~
External Interrupt
Normal Operation
Figure 19-2 SLEEP Mode Release Timing by External Interrupt
~
~
~
~
Oscillator
(XIN pin)
~
~
CPU
Clock
~
~
Internal
RESET
~
~
~
~
RESET
~
~
SLEEP Instruction
Execution
Normal Operation
Stabilization Time
tST = 65.5mS @4MHz
Normal Operation
SLEEP Operation
Figure 19-3 Timing of SLEEP Mode Release by Reset
19.2 Stop Mode
In the Stop mode, the main oscillator, system clock and peripheral clock is stopped, but RC-oscillated watchdog timer continue to operate. With the clock frozen, all functions
are stopped, but the on-chip RAM and Control registers are
held. The port pins out the values held by their respective
port data register, port direction registers. Oscillator stops
and the systems internal operations are all held up.
• The states of the RAM, registers, and latches valid
immediately before the system is put in the STOP
state are all held.
• The program counter stop the address of the
instruction to be executed after the instruction
Mar. 2005 Ver 0.2
"STOP" which starts the STOP operating mode.
Note: The Stop mode is activated by execution of STOP instruction after setting the SSCR to “5AH”. (This register should be written by byte operation. If this register is set by bit manipulation
instruction, for example "set1" or "clr1" instruction, it may be undesired operation)
In the Stop mode of operation, VDD can be reduced to minimize power consumption. Care must be taken, however,
to ensure that VDD is not reduced before the Stop mode is
invoked, and that VDD is restored to its normal operating
level, before the Stop mode is terminated.
89
MC80F0104/0204
Preliminary
The reset should not be activated before VDD is restored to
its normal operating level, and must be held active long
enough to allow the oscillator to restart and stabilize.
Note: After STOP instruction, at least two or more NOP instruction should be written.
Ex)
LDM CKCTLR,#0FH ;more than 20ms
LDM SSCR,#5AH
STOP
NOP ;for stabilization time
NOP ;for stabilization time
pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation
of the STOP feature. This point should be little current
flows when the input level is stable at the power voltage
level (VDD/VSS); however, when the input level gets higher than the power voltage level (by approximately 0.3 to
0.5V), a current begins to flow. Therefore, if cutting off the
output transistor at an I/O port puts the pin signal into the
high-impedance state, a current flow across the ports input
transistor, requiring to fix the level by pull-up or other
means.
In the STOP operation, the dissipation of the power associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the
Peripheral
STOP Mode
SLEEP Mode
CPU
Stop
Stop
RAM
Retain
Retain
Basic Interval Timer
Halted
Operates Continuously
Watchdog Timer
Stop (Only operates in RC-WDT mode)
Stop
Timer/Counter
Halted (Only when the event counter mode
is enabled, timer operates normally)
Operates Continuously
Buzzer, ADC
Stop
Stop
SIO
Only operate with external clock
Only operate with external clock
UART
Only operate with external clock
Only operate with external clock
Oscillator
Stop (XIN=L, XOUT=H)
Oscillation
I/O Ports
Retain
Retain
Control Registers
Retain
Retain
Internal Circuit
Stop mode
Sleep mode
Prescaler
Retain
Active
Address Data Bus
Retain
Retain
Release Source
Reset, Timer(EC0,1), SIO, UART(using
ACLK), Watchdog Timer (RC-WDT mode),
External Interrupt
Reset, All Interrupts
Table 19-1 Peripheral Operation During Power Saving Mode
Release the STOP mode
The source for exit from STOP mode is hardware reset, external interrupt, Timer(EC0,1), Watch Timer, WDT, SIO
or UART. Reset re-defines all the Control registers but
does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their
values.
If I-flag = 1, the normal interrupt response takes place. If Iflag = 0, the chip will resume execution starting with the
instruction following the STOP instruction. It will not vec-
90
tor to interrupt service routine. (refer to Figure 19-4 )
When exit from Stop mode by external interrupt, enough
oscillation stabilizing time is required to normal operation.
Figure 19-5 shows the timing diagram. When released
from the Stop mode, the Basic interval timer is activated on
wake-up. It is increased from 00H until FFH. The count
overflow is set to start normal operation. Therefore, before
STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec).
This guarantees that oscillator has started and stabilized.
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
By reset, exit from Stop mode is shown in Figure 19-6 .
STOP
INSTRUCTION
STOP Mode
Interrupt Request
Corresponding Interrupt
Enable Bit (IENH, IENL)
=0
IENH or IENL ?
=1
STOP Mode Release
Master Interrupt
Enable Bit PSW[2]
I-FLAG
=0
=1
Interrupt Service Routine
Next
INSTRUCTION
Figure 19-4 STOP Releasing Flow by Interrupts
.
~ ~
~
~
~
~
Oscillator
(XIN pin)
~
~
~
~
Internal Clock
~
~
STOP Instruction
Executed
n+1 n+2
n+3
0
Clear
Normal Operation
Stop Operation
1
~
~
~ ~
n
~ ~
~
~
BIT Counter
~
~
External Interrupt
FE
Stabilization Time
tST > 20ms
by software
FF
0
1
2
Normal Operation
Before executing Stop instruction, Basic Interval Timer must be set
properly by software to get stabilization time which is longer than 20ms.
Figure 19-5 STOP Mode Release Timing by External Interrupt
Mar. 2005 Ver 0.2
91
MC80F0104/0204
Preliminary
STOP Mode
~
~
~
~
~ ~
~
~
Oscillator
(XI pin)
~
~
~ ~
~
~
Internal
Clock
RESET
~
~
Internal
RESET
~
~
STOP Instruction Execution
Time can not be control by software
Stabilization Time
tST = 65.5mS @4MHz
Figure 19-6 Timing of STOP Mode Release by Reset
19.3 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode
In the Internal RC-Oscillated Watchdog Timer mode, the
on-chip oscillator is stopped. But internal RC oscillation
circuit is oscillated in this mode. The on-chip RAM and
Control registers are held. The port pins out the values held
by their respective port data register, port direction registers.
The Internal RC-Oscillated Watchdog Timer mode is activated by execution of STOP instruction after setting the bit
RCWDT of CKCTLR to "1". (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction,
it may be undesired operation)
Note: Caution: After STOP instruction, at least two or more NOP
instruction should be written
Ex)
LDM WDTR,#1111_1111B
LDM CKCTLR,#0010_1110B
LDM SSCR,#0101_1010B
STOP
NOP
;for stabilization time
NOP
;for stabilization time
The exit from Internal RC-Oscillated Watchdog Timer
mode is hardware reset or external interrupt or watchdog
timer interrupt (at RC-watchdog timer mode). Reset re-de-
92
fines all the Control registers but does not change the onchip RAM. External interrupts allow both on-chip RAM
and Control registers to retain their values.
If I-flag = 1, the normal interrupt response takes place. In
this case, if the bit WDTON of CKCTLR is set to "0" and
the bit WDTE of IENH is set to "1", the device will execute
the watchdog timer interrupt service routine(Figure 8-6 ).
However, if the bit WDTON of CKCTLR is set to "1", the
device will generate the internal Reset signal and execute
the reset processing(Figure 19-8 ). If I-flag = 0, the chip
will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.(refer to Figure 19-4 )
When exit from Stop mode at Internal RC-Oscillated
Watchdog Timer mode by external interrupt, the oscillation stabilization time is required to normal operation. Figure 19-7 shows the timing diagram. When release the
Internal RC-Oscillated Watchdog Timer mode, the basic
interval timer is activated on wake-up. It is increased from
00H until FFH. The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be
set its relevant prescaler divide ratio to have long enough
time (more than 20msec). This guarantees that oscillator
has started and stabilized. By reset, exit from internal RCOscillated Watchdog Timer mode is shown in Figure 19-8
.
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
~
~
~
~
~
~
Oscillator
(XIN pin)
Internal
RC Clock
~
~
~
~
Internal
Clock
~
~
External
Interrupt
( or WDT Interrupt )
~
~
STOP Instruction Execution
~
~
N-2
N-1
N
N+1
N+2
00
01
FE
FF
00
00
~
~
BIT
Counter
Clear Basic Interval Timer
Normal Operation
STOP mode
at RC-WDT Mode
Stabilization Time
tST > 20mS
Normal Operation
Figure 19-7 Stop Mode Release at Internal RC-WDT Mode by External Interrupt or WDT Interrupt
RCWDT Mode
~
~
~
~
~
~
Oscillator
(XIN pin)
Internal
RC Clock
~
~
RESET by WDT
~
~
STOP Instruction Execution
Time can not be control by software
~
~
Internal
RESET
~
~
~
~
RESET
~
~
Internal
Clock
Stabilization Time
tST = 65.5mS @4MHz
Figure 19-8 Internal RC-WDT Mode Releasing by Reset
Mar. 2005 Ver 0.2
93
MC80F0104/0204
Preliminary
19.4 Minimizing Current Consumption
The Stop mode is designed to reduce power consumption.
To minimize current drawn during Stop mode, the user
should turn-off output drivers that are sourcing or sinking
current, if it is practical.
VDD
INPUT PIN
INPUT PIN
VDD
VDD
internal
pull-up
VDD
i=0
OPEN
O
i
GND
O
i
Very weak current flows
VDD
X
X
i=0
O
OPEN
Weak pull-up current flows
GND
O
When port is configured as an input, input level should
be closed to 0V or 5V to avoid power consumption.
Figure 19-9 Application Example of Unused Input Port
OUTPUT PIN
OUTPUT PIN
VDD
ON
OPEN
OFF
ON
OFF
OFF
i
VDD
GND
X
ON
O
ON
OFF
L
OFF
ON
i
GND
X
O
VDD
L
i=0
GND
O
In the left case, Tr. base current flows from port to GND.
To avoid power consumption, there should be low output
to the port .
In the left case, much current flows from port to GND.
Figure 19-10 Application Example of Unused Output Port
Note: In the STOP operation, the power dissipation associated
with the oscillator and the internal hardware is lowered; however,
the power dissipation associated with the pin interface (depending
on the external circuitry and program) is not directly determined by
the hardware operation of the STOP feature. This point should be
little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level becomes higher than the power voltage level (by approximately 0.3V), a current
begins to flow. Therefore, if cutting off the output transistor at an I/
94
O port puts the pin signal into the high-impedance state, a current
flow across the ports input transistor, requiring it to fix the level by
pull-up or other means.
It should be set properly in order that current flow through
port doesn't exist.
First consider the port setting to input mode. Be sure that
there is no current flow after considering its relationship
with external circuit. In input mode, the pin impedance
Mar. 2005 Ver 0.2
Preliminary
viewing from external MCU is very high that the current
doesn’t flow.
But input voltage level should be VSS or VDD. Be careful
that if unspecified voltage, i.e. if uncertain voltage level
(not VSS or VDD) is applied to input pin, there can be little
current (max. 1mA at around 2V) flow.
MC80F0104/0204
output mode considering there is no current flow. The port
setting to High or Low is decided by considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to
High, and if there is external pull-down register, it is set to
low.
If it is not appropriate to set as an input mode, then set to
Mar. 2005 Ver 0.2
95
MC80F0104/0204
Preliminary
20. RESET
The MC80F0104/0204 supports various kinds of reset as
below.
• Watchdog Timer Timeout Reset
• Power-On Reset (POR)
• Address Fail Reset
• Power-Fail Detection (PFD) Reset
• RESET (external reset circuitry)
RESET
Noise Canceller
POR
(Power-On Reset)
S
Address Fail reset
Overflow
PFD
(Power-Fail Detection)
Q
Internal
RESET
R
Clear
WDT
(WDT Timeout Reset)
BIT
Figure 20-1 RESET Block Diagram
The on-chip POR circuit holds down the device in RESET
until VDD has reached a high enough level for proper operation. It will eliminate external components such as reset
IC or external resistor and capacitor for external reset circuit. In addition that the RESET pin can be used to normal
input port R35 by setting “POR” and “R35EN” bit ConfigOn-chip Hardware
Program counter
RAM page register
G-flag
Operation mode
Initial Value
uration Area(20FFH) in the Flash programming. When the
device starts normal operation, its operating parmeters
(voltage, frequency, temperature...etc) must be met.
.Table 20-1 shows on-chip hardware initialization by reset
action.
On-chip Hardware
Initial Value
(FFFFH) - (FFFEH)
Peripheral clock
Off
(RPR)
0
Watchdog timer
Disable
(G)
0
Control registers
Refer to Table 8-1 on page 25
(PC)
Main-frequency clock
Power fail detector
Disable
Table 20-1 Initializing Internal Status by Reset Action
The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin low for at least 8 oscillator periods, within the
operating voltage range and oscillation stable, it is applied,
and the internal state is initialized. After reset, 65.5ms (at
4 MHz) add with 7 oscillator periods are required to start
execution as shown in Figure 20-2 .
Internal RAM is not affected by reset. When VDD is turned
96
on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before read or tested it.
When the RESET pin input goes to high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH - FFFFH.
A connection for simple power-on-reset is shown in Figure
20-1 .
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
VCC
10kΩ
to the RESET pin
7036P
+
10uF
Figure 20-1 Simple Power-on-Reset Circuit
1
?
?
4
5
6
7
~
~
?
FFFE FFFF Start
?
~
~ ~
~
?
?
?
?
FE
ADL
ADH
OP
~
~
DATA
BUS
3
~
~
RESET
ADDRESS
BUS
2
~
~
Oscillator
(XIN pin)
Stabilization Time
tST =65.5mS at 4MHz
Reset Process Step
tST =
1
fXIN ÷1024
MAIN PROGRAM
x 256
Figure 20-2 Timing Diagram after Reset
The Address Fail Reset is the function to reset the system
by checking code access of abnormal and unwished address caused by erroneous program code itself or external
noise, which could not be returned to normal operation and
would become malfunction state. If the CPU tries to fetch
Mar. 2005 Ver 0.2
the instruction from ineffective code area or RAM area, the
address fail reset is occurred. Please refer to Figure 11-2
for setting address fail option.
97
MC80F0104/0204
Preliminary
21. POWER FAIL PROCESSOR
on page 98.
TheMC80F0104/0204 has an on-chip power fail detection
circuitry to immunize against power noise. A configuration register, PFDR, can enable or disable the power fail
detect circuitry. Whenever VDD falls close to or below
power fail voltage for 100ns, the power fail situation may
reset or freeze MCU according to PFDM bit of PFDR. Refer to “Figure 21-1 Power Fail Voltage Detector Register”
PFDR
7
-
6
-
5
-
4
-
3
-
R/W
2
In the in-circuit emulator, power fail function is not implemented and user can not experiment with it. Therefore, after final development of user program, this function may
be experimented or evaluated.
R/W
1
R/W
0
PFDEN PFDM PFDS
ADDRESS: 0F7H
INITIAL VALUE: ---- -000B
Power Fail Status
0: Normal operate
1: Set to “1” if power fail is detected
PFD Operation Mode
0 : MCU will be frozen by power fail detection
1 : MCU will be reset by power fail detection
* Cautions :
PFD Enable Bit
0: Power fail detection disable
1: Power fail detection enable
Be sure to set bits 3 through 7 to “0”.
Figure 21-1 Power Fail Voltage Detector Register
RESET VECTOR
PFDS =1
YES
NO
RAM Clear
Initialize RAM Data
Initialize All Ports
Initialize Registers
PFDS = 0
Skip the
initial routine
Function
Execution
Figure 21-2 Example S/W of Reset flow by Power fail
98
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
VDD
Internal
RESET
VPFDMAX
VPFDMIN
65.5mS
VDD
When PFDM = 1
Internal
RESET
t < 65.5mS
65.5mS
VDD
Internal
RESET
65.5mS
VPFDMAX
VPFDMIN
VPFDMAX
VPFDMIN
Figure 21-3 Power Fail Processor Situations (at 4MHz operation)
Mar. 2005 Ver 0.2
99
MC80F0104/0204
Preliminary
22. COUNTERMEASURE OF NOISE
22.1 Oscillation Noise Protector
by high frequency noise.
- Change system clock to the internal oscillation clock
when the high frequency noise is continuing.
- Change system clock to the internal oscillation clock
when the XIN/XOUT is shorted or opened, the main
oscillation is stopped except by stop instruction and
the low frequency noise is entered.
The Oscillation Noise Protector (ONP) is used to supply
stable internal system clock by excluding the noise which
could be entered into oscillator and recovery the oscillation
fail. This function could be enabled or disabled by the
“ONP” bit of the Device configuration area (20FFH) for
the MC80F0204, “ONP” option bits MASK option.
The ONP function is like below.
- Recovery the oscillation wave crushed or loss caused
XIN
OFP
1
HF Noise
Canceller
HF Noise
Observer
XIN_NF
Mux
0S
0
CLK
Changer
Internal
OSC
1
FINTERNAL
S
en
INT_CLK
ONP
OFP
LF Noise
Observer
CLK_CHG
ONP
IN4(2)MCLK(XO)
en
o/f
PS10
ONPb = 0
CK
en
OFP
(8-Bit counter)
LF_on = 1
IN_CLK = 0
High Frq. Noise
INT_CLK 8 periods
(250ns × 8 =2us)
PS10(INT_CLK/512) 256 periods
(250ns × 512 × 256 =33 ms)
~
~
~
~
Low Frq. Noise or
Oscillation Fail
~
~
~
~
INT_CLK reset
Noise Cancel
~
~
XIN_NF
~
~
XIN
~
~
~ ~
~
~
INT_CLK
OFP_EN
~
~ ~
~
CHG_END
CLK_CHG
Clock Change Start(XIN to INT_CLK)
~
~
~
~
fINTERNAL
Clock Change End(INT_CLK to XIN))
Figure 22-1 Block Diagram of ONP & OFP and Respective Wave Forms
100
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
22.2 Oscillation Fail Processor
The oscillation fail processor (OFP) can change the clock
source from external to internal oscillator when the oscillation fail occured. This function could be enabled or disabled by the “OFP” bit of the Device Configuration Area
(MASK option for MC80C0104/0204).
And this function can recover the external clock source
when the external clock is recovered to normal state.
vice Configuration Area (MASK option for MC80C0104/
0204) enables the function to operate the device by using
the internal oscillator clock in ONP block as system clock.
There is no need to connect the x-tal, resonator, RC and R
externally. The user only to connect the XIN pin to VDD.
After selecting the this option, the period of internal oscillator clock could be checked by XOUT outputting clock divided the internal oscillator clock by 4.
IN4(2)MCLK/CLKXO(XO) Option
The “IN4MCLK(XO)”, “IN2MCLK(XO)” bit of the De-
Mar. 2005 Ver 0.2
101
MC80F0104/0204
Preliminary
23. Device Configuration Area
The Device Configuration Area can be programmed or left
unprogrammed to select device configuration such as
POR, ONP, CLK option and security bit. This area is not
Configuration Option Bits
7
ONP
accessible during normal execution but is readable and
writable during FLASH program / verify mode.
6
5
4
3
2
1
0
OFP LOCK POR R35EN CLK2 CLK1 CLK0
ADDRESS: 20FFH
INITIAL VALUE: 00H
Oscillation confuguration
000 : IN4MCLK (Internal 4MHz Oscillation & R33/R34 Enable)
001 : IN2MCLK (Internal 2MHz Oscillation & R33/R34 Enable)
010 : EXRC (External R/RC Oscillation & R34 Enable)
011 : X-tal (Crystal or Resonator Oscillation)
100 : IN4MCLKXO (internal 4MHz Oscillation & R33 Enable
& XOUT = fSYS ÷ 4)
101 : IN2MCLKXO (internal 2MHz Oscillation & R33 Enable
& XOUT = fSYS ÷ 4)
110 : EXRCXO (External R/RC Oscillation & XOUT = fSYS ÷ 4)
111 : Prohibited
RESET/R35 Port configuration
0 : R35 Port Disable (Use RESET)
1 : R35 Port Ensable (Disable RESET)
POR Use
0 : Disable POR Reset
1 : Ensable POR Reset
Security Bit
0 : Enable reading User Code
1 : Disable reading User Code
OFP use
0 : Disable OFP (Clock Changer)
1 : Enable OFP (Clock Changer)
ONP disable
0 : Enable ONP (Enable OFP, Internal 4MHz/2MHz oscillation)
1 : Disable ONP (Disable OFP, Internal 4MHz/2MHz oscillation)
Figure 23-1 Device Configuration Area
102
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
24. MASK Option (MC80C0104/0204)
The MC80C0104/0204 has several MASK option which
configures the package type or use of some special features
of the device. The Mask option of the MASK order sheet
should be checked to select device configuration such as
Option
Package
ONP
Check
POR
R35EN
CLK
option
Operation
16 PDIP
16PDIP type package select
16SOP
16SOP type package select
Yes
ONP Enable
No
ONP Disable
Yes
Enables Oscillation Fail Processor (ONP clock
changer)
No
Disables Oscillation Fail Processor (ONP clock
changer )
Yes
Enables POR
No
Disables POR
Yes
R35 port Enable (Disable RESET)
No
R35 port Disable (Use RESET)
OFP
MASK
Option
package type, Oscillation selection, oscillation noise protector, oscillation fail protector, internal 4MHz, amount of
noise to be cancelled.
Crystal
Crystal Oscillation
EXRC
External R/RC oscillation & R33 Enable
IN4MCLK
Internal 4MHz Oscillation & R33/R34 Enable
IN2MCLK
Internal 2MHz Oscillation & R33/R34 Enable
EXRCXO
External R/RC oscillation & R33 Enable
XOUT Pin : System clock ÷ 4
IN4MCLKXO
Internal 4MHz Oscillation & R33 Enable
XOUT Pin : System clock ÷ 4
IN2MCLKXO
Internal 2MHz Oscillation & R33 Enable
XOUT Pin : System clock ÷ 4
Remark
This option is valid only for the
MC80C0104
OSC Noise Protector (ONP)
Operation En/Disable Bit
Change the Inter clock when
oscillation failed
To select Power-on Reset
To use R35 port as normal input
port
To select Oscillation Type
Table 24-1 MASK options
Mar. 2005 Ver 0.2
103
MC80F0104/0204
Preliminary
25. Emulator EVA. Board Setting
➎
➊
➏
➐
➌
➍
➋
104
Mar. 2005 Ver 0.2
Preliminary
DIP Switch and VR Setting
Before execute the user program, keep in your mind the beDIP S/W, VR
➊
➋
MC80F0104/0204
low configuration
Description
ON/OFF Setting
-
This connector is only used for a device over 32 PIN.
For the MC80F0104/0204.
-
This connector is only used for a device under 32 PIN.
For the MC80F0208/0216/0224.
Must be OFF position.
OFF
1
ON : For the MC80F0208/0216/0224.
OFF : For the MC80F0104/0204.
Eva. select switch
2
3
ON
OFF
OFF
ON
Use Eva. VDD
➌
Use User’s VDD
These switches select the AVDD source.
ON & OFF : Use Eva. VDD
OFF & ON : Use User AVDD
AVDD pin select switch
This switch select the /Reset source.
Normally OFF.
EVA. chip can be reset by external user target board.
ON : Reset is available by either user target
system board or Emulator RESET switch.
OFF : Reset the MCU by Emulator RESET
switch. Does not work from user target
board.
This switch select the Xout signal on/off.
Normally OFF.
MCU XOUT pin is disconnected internally
in the Emulator. Some circumstance user
may connect this circuit.
ON : Output XOUT signal
OFF : Disconnect circuit
SW2
4
5
This switch select Eva. B/D Power supply source.
MDS
➍
SW3
MDS
Normally MDS.
This switch select Eva. B/D Power supply
source.
1
USER
Use MDS Power
➎
SW4
1
2
USER
Use User’s Power
This switch select the R22 or SXOUT.
This switch select the R21 or SXIN.
Mar. 2005 Ver 0.2
These switchs select the Normal I/O port
(off) or Sub-Clock (on).
It is reserved for the MC80F0448.
ON : SXOUT, SXIN
OFF : R22, R21
Don’t care.
105
MC80F0104/0204
DIP S/W, VR
Preliminary
Description
ON/OFF Setting
SW5
1
2
3
4
5
6
(switch 1 & 2)
These switches select the R33 or XIN
(switch 3 & 4)
These switches select the R34 or XOUT
(switch 5 & 6)
These switches select the R35 or /Reset
This switch select the Normal I/O port (off)
or special function select (on).
ON & OFF : R33,R34,R35 Port selected.
OFF & ON : XIN, XOUT, /Reset selected.
➐
-
This is External oscillation socket (CAN Type. OSC)
This is for External Clock (CAN Type.
OSC).
➏
106
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
26. IN-SYSTEM PROGRAMMING (ISP)
26.1 Getting Started / Installation
The following section details the procedure for accomplishing the
installation procedure.
3. Turn your target B/D power switch ON. Your target B/
D must be configured to enter the ISP mode.
1. Connect the serial(RS-232C) cable between a target
board and the COM port of your PC.
4. Run the MagnaChip ISP software.
2. Configure the COM port of your PC as following.
Baudrate
Data bit
Parity
Stop bit
Flow control
5. Press the Reset Button in the ISP S/W. If the status windows shows a message as "Connected", all the conditions for ISP are provided.
115,200
8
No
1
No
26.2 Basic ISP S/W Information
Mar. 2005 Ver 0.2
107
MC80F0104/0204
Preliminary
Function
Description
Load HEX File
Load the data from the selected file storage into the memory buffer.
Save HEX File
Save the current data in your memory buffer to a disk storage by using the Intel Motorolla HEX
format.
Erase
Erase the data in your target MCU before programming it.
Blank Check
Verify whether or not a device is in an erased or unprogrammed state.
Program
This button enables you to place new data from the memory buffer into the target device.
Read
Read the data in the target MCU into the buffer for examination. The checksum will be displayed
on the checksum box.
Verify
Assures that data in the device matches data in the memory buffer. If your device is secured, a
verification error is detected.
Option Write
Progam the configuration data of target MCU. The security locking is performed with this button.
Option
Set the configuration data of target MCU. The security locking is set with this button.
AUTO
Erase & Program & Verify.
Auto Option Write
If selected with check mark, the option write is performed after erasure and write.
Edit Buffer
Modify the data in the selected address in your buffer memory
Fill Buffer
Fill the selected area with a data.
Goto
Display the selected page.
OSC. ______ MHz
Enter your target system’s oscillator value with discarding below point.
Start ______
Starting address
End ______
End address
Checksum
Display the checksum(Hexdecimal) after reading the target device.
Com Port
Select serial port.
Baud Rate
Select UART baud rate.
Select Device
Select target device.
Page Up Key
Display the previous page of your memory buffer.
Page Down Key
Display the higher page than the current location.
Table 26-1 ISP Function Description
108
Mar. 2005 Ver 0.2
Preliminary
MC80F0104/0204
26.3 Hardware Conditions to Enter the ISP Mode
bedded application possible with a minimum of additional
expense in components and circuit board area. The boot
loader can be executed by holding ALE high, RESET /VPP
as +9V, and ACLK with the OSC. 1.8432MHz. The ISP
function uses five pins: TxD, RxD, ALE, ACLK and RESET/VPP.
The In-System Programming (ISP) is performed without
removing the microcontroller from the system. The InSystem Programming (ISP) facility consists of a series of
internal hardware resources coupled with internal firmware through the serial port. The In-System Programming
(ISP) facility has made in-circuit programming in an em-
VDD(+5V)
MCU_RxD
1
20
R05 / TxD
2
19
ACLK_CLK
R05 / ACLK
3
18
4
17
High(1)
ALE
VDD
5
R10
6
MC80F0204
R04 / RxD
MCU_TxD
16
VSS
15
RESET RESET / VPP
14
XOUT
8
13
XIN
9
12
10
11
7
+9V
X-TAL
2MHz~12MHz
ISP Configuration
Note: Considerations to implement ISP function in a user
target board
• The ACLK must be connected to the specifed
oscillator.
• Connect the +9V to RESET/Vpp pin directly.
• The ALE pin must be pulled high.
• The main clk must be higher than 2MHz.
Mar. 2005 Ver 0.2
109
MC80F0104/0204
Preliminary
26.4 Reference ISP Circuit Diagram and MagnaChip Supplied ISP Board
The ISP software and hardware circuit diagram are provided at
www.magnachipmcu.com . To get a ISP B/D, contact to sales de-
partment. The following circuit diagram is for reference use..
2Ν2907 100Ω
DTR
TxD
+
1uF
RxD
+
1uF
T1IN 11
10
T2IN
12
R1OUT
R2OUT 9
1
C1+
+
1uF
3
C14
C2+
+
1uF
5
C2-
10uF
14
T1OUT
7 T2OUT
13
R1IN
8 R2IN
2
V+
16
VCC
6
V15
GND
GND
0.1uF
To PC
5
9
4
8
3
7
2
6
1
10kΩ
CON1
Female DB9
10kΩ
MAX232
VDD(+5V)
1.2kΩ
VDD
VSS
+
VSS
J2
RESET/VPP
VDD
VSS
ACLK_CLK
MCU_TxD
MCU_RxD
1
2
3
4
5
6
To MCU
VSS
VSS
VSS
* VDD : +4.5 ~ +5.5V
J3
VDD(+5V)
22Ω
* VPP : VDD + 4V
X1
Vcc
0.1uF
+
0.1uF
VDD
VSS
10uF/16V
VDD(+5V)
100Ω
Out
Gnd
OSC
1.8432MHz
VSS
VSS
VSS
External VDD
The ragne of VDD must be from 4.5 to 5.5V and ISP function is not supported under 2MHz system clock.
If the user supplied VDD is out of range, the external power is needed instead of the target system VDD.
For the ISP operation, power consumption required is minimum 30mA.
Figure 26-1 Reference ISP Circuit Diagram
Figure 26-2 MagnaChip supplied ISP Board
110
Mar. 2005 Ver 0.2
APPENDIX
MC80F0104/0204
Preliminary
A. INSTRUCTION MAP
LOW 00000
HIGH
00
00001
01
SET1
dp.bit
00010
02
00011
03
BBS
BBS
A.bit,rel dp.bit,rel
00100
04
00101
05
00110
06
00111
07
01000
08
01001
09
ADC
#imm
ADC
dp
ADC
dp+X
ADC
!abs
ASL
A
ASL
dp
01010
0A
01011
0B
01100
0C
01101
0D
01110
0E
01111
0F
TCALL SETA1
0
.bit
BIT
dp
POP
A
PUSH
A
BRK
000
-
001
CLRC
SBC
#imm
SBC
dp
SBC
dp+X
SBC
!abs
ROL
A
ROL
dp
TCALL CLRA1
2
.bit
COM
dp
POP
X
PUSH
X
BRA
rel
010
CLRG
CMP
#imm
CMP
dp
CMP
dp+X
CMP
!abs
LSR
A
LSR
dp
TCALL
4
NOT1
M.bit
TST
dp
POP
Y
PUSH
Y
PCALL
Upage
011
DI
OR
#imm
OR
dp
OR
dp+X
OR
!abs
ROR
A
ROR
dp
TCALL
6
OR1
OR1B
CMPX
dp
POP
PSW
PUSH
PSW
RET
100
CLRV
AND
#imm
AND
dp
AND
dp+X
AND
!abs
INC
A
INC
dp
TCALL AND1
8
AND1B
CMPY
dp
CBNE
dp+X
TXSP
INC
X
101
SETC
EOR
#imm
EOR
dp
EOR
dp+X
EOR
!abs
DEC
A
DEC
dp
TCALL EOR1
10
EOR1B
DBNE
dp
XMA
dp+X
TSPX
DEC
X
110
SETG
LDA
#imm
LDA
dp
LDA
dp+X
LDA
!abs
TXA
LDY
dp
TCALL
12
LDC
LDCB
LDX
dp
LDX
dp+Y
XCN
DAS
EI
LDM
dp,#imm
STA
dp
STA
dp+X
STA
!abs
TAX
STY
dp
TCALL
14
STC
M.bit
STX
dp
STX
dp+Y
XAX
STOP
10011
13
10100
14
10101
15
10110
16
10111
17
11000
18
11001
19
11010
1A
11011
1B
11100
1C
11101
1D
11110
1E
11111
1F
ADC
{X}
ADC
!abs+Y
ADC
[dp+X]
ADC
[dp]+Y
ASL
!abs
ASL
dp+X
TCALL
1
JMP
!abs
BIT
!abs
ADDW
dp
LDX
#imm
JMP
[!abs]
TEST
!abs
SUBW
dp
LDY
#imm
JMP
[dp]
TCLR1 CMPW
!abs
dp
CMPX
#imm
CALL
[dp]
111
LOW 10000
HIGH
10
10001
11
10010
12
000
BPL
rel
001
BVC
rel
SBC
{X}
SBC
!abs+Y
SBC
[dp+X]
SBC
[dp]+Y
ROL
!abs
ROL
dp+X
TCALL
3
CALL
!abs
010
BCC
rel
CMP
{X}
CMP
!abs+Y
CMP
[dp+X]
CMP
[dp]+Y
LSR
!abs
LSR
dp+X
TCALL
5
MUL
011
BNE
rel
OR
{X}
OR
!abs+Y
OR
[dp+X]
OR
[dp]+Y
ROR
!abs
ROR
dp+X
TCALL
7
DBNE
Y
CMPX
!abs
LDYA
dp
CMPY
#imm
RETI
100
BMI
rel
AND
{X}
AND
!abs+Y
AND
[dp+X]
AND
[dp]+Y
INC
!abs
INC
dp+X
TCALL
9
DIV
CMPY
!abs
INCW
dp
INC
Y
TAY
101
BVS
rel
EOR
{X}
EOR
!abs+Y
EOR
[dp+X]
EOR
[dp]+Y
DEC
!abs
DEC
dp+X
TCALL
11
XMA
{X}
XMA
dp
DECW
dp
DEC
Y
TYA
110
BCS
rel
LDA
{X}
LDA
!abs+Y
LDA
[dp+X]
LDA
[dp]+Y
LDY
!abs
LDY
dp+X
TCALL
13
LDA
{X}+
LDX
!abs
STYA
dp
XAY
DAA
111
BEQ
rel
STA
{X}
STA
!abs+Y
STA
[dp+X]
STA
[dp]+Y
STY
!abs
STY
dp+X
TCALL
15
STA
{X}+
STX
!abs
CBNE
dp
XYX
NOP
CLR1
BBC
BBC
dp.bit
A.bit,rel
dp.bit,rel
Mar. 2005 Ver 0.2
i
MC80F0104/0204
Preliminary
B. INSTRUCTION SET
1. ARITHMETIC/ LOGIC OPERATION
NO.
1
ii
MNEMONIC
ADC #imm
OP BYTE CYCLE
CODE NO
NO
04
2
2
Add with carry.
2
ADC dp
05
2
3
3
ADC dp + X
06
2
4
4
ADC !abs
07
3
4
5
ADC !abs + Y
15
3
5
6
ADC [ dp + X ]
16
2
6
7
ADC [ dp ] + Y
17
2
6
8
ADC { X }
14
1
3
9
AND #imm
AND dp
84
2
2
10
85
2
3
11
AND dp + X
86
2
4
12
AND !abs
87
3
4
13
AND !abs + Y
95
3
5
14
AND [ dp + X ]
96
2
6
15
AND [ dp ] + Y
97
2
6
16
AND { X }
94
1
3
17
ASL A
08
1
2
18
19
ASL dp
ASL dp + X
09
19
2
2
4
5
20
ASL !abs
18
3
5
21
CMP #imm
44
2
2
22
CMP dp
45
2
3
23
CMP dp + X
46
2
4
24
CMP !abs
47
3
4
25
CMP !abs + Y
55
3
5
26
CMP [ dp + X ]
56
2
6
27
CMP [ dp ] + Y
57
2
6
28
CMP { X }
54
1
3
29
CMPX #imm
5E
2
2
30
CMPX dp
6C
2
3
31
CMPX !abs
7C
3
4
FLAG
NVGBHIZC
OPERATION
A←(A)+(M)+C
NV--H-ZC
Logical AND
A← (A)∧(M)
N-----Z-
Arithmetic shift left
C
7
6
5
4
3
2
1
N-----ZC
0
“0”
Compare accumulator contents with memory contents
(A) -(M)
N-----ZC
Compare X contents with memory contents
(X)-(M)
N-----ZC
32
CMPY #imm
7E
2
2
33
CMPY dp
8C
2
3
34
CMPY !abs
9C
3
4
35
COM dp
2C
2
4
1’S Complement : ( dp ) ← ~( dp )
N-----Z-
36
DAA
DF
1
3
Decimal adjust for addition
N-----ZC
37
DAS
CF
1
3
Decimal adjust for subtraction
N-----ZC
38
DEC A
A8
1
2
Decrement
N-----Z-
39
DEC dp
A9
2
4
40
DEC dp + X
B9
2
5
5
41
DEC !abs
B8
3
42
DEC X
AF
1
2
43
DEC Y
BE
1
2
44
DIV
9B
1
12
Compare Y contents with memory contents
(Y)-(M)
N-----ZC
M← (M)-1
N-----Z-
Divide : YA / X Q: A, R: Y
NV--H-Z-
Mar. 2005 Ver 0.2
MC80F0104/0204
NO.
MNEMONIC
Preliminary
FLAG
NVGBHIZC
OP BYTE CYCLE
OPERATION
CODE NO
NO
A4
2
2
Exclusive OR
A5
2
3
A← (A)⊕(M)
45
EOR #imm
46
EOR dp
47
EOR dp + X
A6
2
4
48
EOR !abs
A7
3
4
49
EOR !abs + Y
B5
3
5
50
EOR [ dp + X ]
B6
2
6
51
EOR [ dp ] + Y
B7
2
6
52
EOR { X }
B4
1
3
53
INC A
88
1
2
54
INC dp
89
2
4
N-----Z-
N-----Z-
Increment
M← (M)+1
55
INC dp + X
99
2
5
56
INC !abs
98
3
5
57
INC X
8F
1
2
58
INC Y
9E
1
2
59
LSR A
48
1
2
60
LSR dp
49
2
4
61
LSR dp + X
59
2
5
62
LSR !abs
58
3
5
63
MUL
5B
1
9
Multiply : YA ← Y × A
64
OR #imm
64
2
2
Logical OR
N-----Z-
Logical shift right
7
6
5
4
3
2
1
0
C
N-----ZC
“0”
N-----Z-
65
OR dp
65
2
3
66
OR dp + X
66
2
4
67
OR !abs
67
3
4
68
OR !abs + Y
75
3
5
69
OR [ dp + X ]
76
2
6
70
OR [ dp ] + Y
77
2
6
71
OR { X }
74
1
3
72
ROL A
28
1
2
73
ROL dp
29
2
4
74
ROL dp + X
39
2
5
75
ROL !abs
38
3
5
76
ROR A
68
1
2
77
ROR dp
69
2
4
78
ROR dp + X
79
2
5
79
ROR !abs
78
3
5
80
SBC #imm
24
2
2
81
SBC dp
25
2
3
82
SBC dp + X
26
2
4
83
SBC !abs
27
3
4
84
SBC !abs + Y
35
3
5
85
SBC [ dp + X ]
36
2
6
86
SBC [ dp ] + Y
37
2
6
87
SBC { X }
34
1
3
88
TST dp
4C
2
3
Test memory contents for negative or zero
( dp ) - 00H
N-----Z-
89
XCN
CE
1
5
Exchange nibbles within the accumulator
A7~A4 ↔ A3~A0
N-----Z-
Mar. 2005 Ver 0.2
A ← (A)∨(M)
N-----Z-
Rotate left through carry
C
7
6
5
4
3
2
1
0
N-----ZC
Rotate right through carry
7
6
5
4
3
2
1
0
C
N-----ZC
Subtract with carry
A ← ( A ) - ( M ) - ~( C )
NV--HZC
iii
MC80F0104/0204
Preliminary
2. REGISTER / MEMORY OPERATION
NO.
iv
MNEMONIC
OP
BYTE CYCLE
CODE NO
NO
C4
2
2
1
LDA #imm
2
LDA dp
C5
2
3
3
LDA dp + X
C6
2
4
4
LDA !abs
C7
3
4
Load accumulator
A←(M)
5
LDA !abs + Y
D5
3
5
6
LDA [ dp + X ]
D6
2
6
7
LDA [ dp ] + Y
D7
2
6
8
LDA { X }
D4
1
3
9
LDA { X }+
DB
1
4
X- register auto-increment : A ← ( M ) , X ← X + 1
10
LDM dp,#imm
E4
3
5
Load memory with immediate data : ( M ) ← imm
11
LDX #imm
1E
2
2
Load X-register
12
LDX dp
CC
2
3
13
LDX dp + Y
CD
2
4
14
LDX !abs
DC
3
4
15
LDY #imm
3E
2
2
16
LDY dp
C9
2
3
17
LDY dp + X
D9
2
4
18
LDY !abs
D8
3
4
19
STA dp
E5
2
4
20
STA dp + X
E6
2
5
21
STA !abs
E7
3
5
22
STA !abs + Y
F5
3
6
23
STA [ dp + X ]
F6
2
7
24
STA [ dp ] + Y
F7
2
7
25
STA { X }
F4
1
4
FLAG
NVGBHIZC
OPERATION
N-----Z-
--------
X ←(M)
N-----Z-
Load Y-register
Y←(M)
N-----Z-
Store accumulator contents in memory
(M)←A
--------
26
STA { X }+
FB
1
4
X- register auto-increment : ( M ) ← A, X ← X + 1
27
STX dp
EC
2
4
Store X-register contents in memory
28
STX dp + Y
ED
2
5
29
STX !abs
FC
3
5
30
STY dp
E9
2
4
31
STY dp + X
F9
2
5
32
STY !abs
F8
3
5
33
TAX
E8
1
2
Transfer accumulator contents to X-register : X ← A
N-----Z-
34
TAY
9F
1
2
Transfer accumulator contents to Y-register : Y ← A
N-----Z-
35
TSPX
AE
1
2
Transfer stack-pointer contents to X-register : X ← sp
N-----Z-
36
TXA
C8
1
2
Transfer X-register contents to accumulator: A ← X
N-----Z-
37
TXSP
8E
1
2
Transfer X-register contents to stack-pointer: sp ← X
N-----Z-
38
TYA
BF
1
2
Transfer Y-register contents to accumulator: A ← Y
N-----Z-
39
XAX
EE
1
4
(M)← X
--------
Store Y-register contents in memory
(M)← Y
--------
40
XAY
DE
1
4
Exchange X-register contents with accumulator :X ↔ A -------Exchange Y-register contents with accumulator :Y ↔ A --------
41
XMA dp
BC
2
5
Exchange memory contents with accumulator
42
XMA dp+X
AD
2
6
43
XMA {X}
BB
1
5
44
XYX
FE
1
4
(M)↔A
N-----Z-
Exchange X-register contents with Y-register : X ↔ Y
--------
Mar. 2005 Ver 0.2
MC80F0104/0204
Preliminary
3. 16-BIT OPERATION
NO.
MNEMONIC
OP BYTE CYCLE
CODE NO
NO
OPERATION
FLAG
NVGBHIZC
1
ADDW dp
1D
2
5
16-Bits add without carry
YA ← ( YA ) + ( dp +1 ) ( dp )
NV--H-ZC
2
CMPW dp
5D
2
4
Compare YA contents with memory pair contents :
(YA) − (dp+1)(dp)
N-----ZC
3
DECW dp
BD
2
6
Decrement memory pair
( dp+1)( dp) ← ( dp+1) ( dp) - 1
N-----Z-
4
INCW dp
9D
2
6
Increment memory pair
( dp+1) ( dp) ← ( dp+1) ( dp ) + 1
N-----Z-
5
LDYA dp
7D
2
5
Load YA
YA ← ( dp +1 ) ( dp )
N-----Z-
6
STYA dp
DD
2
5
Store YA
( dp +1 ) ( dp ) ← YA
--------
7
SUBW dp
3D
2
5
16-Bits substact without carry
YA ← ( YA ) - ( dp +1) ( dp)
NV--H-ZC
4. BIT MANIPULATION
NO.
MNEMONIC
OP BYTE CYCLE
OPERATION
CODE NO
NO
8B
3
4
Bit AND C-flag : C ← ( C ) ∧ ( M .bit )
FLAG
NVGBHIZC
-------C
1
AND1 M.bit
2
AND1B M.bit
8B
3
4
Bit AND C-flag and NOT : C ← ( C ) ∧ ~( M .bit )
-------C
3
BIT dp
0C
2
4
Bit test A with memory :
MM----Z-
4
BIT !abs
1C
3
5
Z ← ( A ) ∧ ( M ) , N ← ( M7 ) , V ← ( M 6 )
2
4
Clear bit : ( M.bit ) ← “0”
5
CLR1 dp.bit
y1
6
CLRA1 A.bit
2B
2
2
Clear A bit : ( A.bit )← “0”
--------
7
CLRC
20
1
2
Clear C-flag : C ← “0”
-------0
--------
8
CLRG
40
1
2
Clear G-flag : G ← “0”
--0-----
9
CLRV
80
1
2
Clear V-flag : V ← “0”
-0--0---
10
-------C
EOR1 M.bit
AB
3
5
Bit exclusive-OR C-flag : C ← ( C ) ⊕ ( M .bit )
11
EOR1B M.bit
AB
3
5
12
LDC M.bit
CB
3
4
Bit exclusive-OR C-flag and NOT : C ← ( C ) ⊕ ~(M .bit) -------C
Load C-flag : C ← ( M .bit )
-------C
13
LDCB M.bit
CB
3
4
Load C-flag with NOT : C ← ~( M .bit )
-------C
14
NOT1 M.bit
4B
3
5
Bit complement : ( M .bit ) ← ~( M .bit )
--------
15
OR1 M.bit
6B
3
5
Bit OR C-flag : C ← ( C ) ∨ ( M .bit )
-------C
16
OR1B M.bit
6B
3
5
Bit OR C-flag and NOT : C ← ( C ) ∨ ~( M .bit )
-------C
17
SET1 dp.bit
x1
2
4
Set bit : ( M.bit ) ← “1”
--------
18
SETA1 A.bit
0B
2
2
Set A bit : ( A.bit ) ← “1”
--------
19
SETC
A0
1
2
Set C-flag : C ← “1”
-------1
20
SETG
C0
1
2
Set G-flag : G ← “1”
--1-----
21
STC M.bit
EB
3
6
Store C-flag : ( M .bit ) ← C
--------
22
TCLR1 !abs
5C
3
6
Test and clear bits with A :
A - ( M ) , ( M ) ← ( M ) ∧ ~( A )
N-----Z-
23
TSET1 !abs
3C
3
6
Test and set bits with A :
A-(M), (M)← (M)∨(A)
N-----Z-
Mar. 2005 Ver 0.2
v
MC80F0104/0204
Preliminary
5. BRANCH / JUMP OPERATION
NO.
OP BYTE CYCLE
OPERATION
CODE NO
NO
y2
2
4/6
Branch if bit clear :
y3
3
5/7
if ( bit ) = 0 , then pc ← ( pc ) + rel
FLAG
NVGBHIZC
--------
1
BBC A.bit,rel
2
BBC dp.bit,rel
3
BBS A.bit,rel
x2
2
4/6
BBS dp.bit,rel
x3
3
5/7
if ( bit ) = 1 , then pc ← ( pc ) + rel
--------
4
vi
MNEMONIC
Branch if bit set :
--------
5
BCC rel
50
2
2/4
Branch if carry bit clear
if ( C ) = 0 , then pc ← ( pc ) + rel
6
BCS rel
D0
2
2/4
Branch if carry bit set
if ( C ) = 1 , then pc ← ( pc ) + rel
--------
7
BEQ rel
F0
2
2/4
Branch if equal
if ( Z ) = 1 , then pc ← ( pc ) + rel
--------
8
BMI rel
90
2
2/4
Branch if minus
if ( N ) = 1 , then pc ← ( pc ) + rel
--------
9
BNE rel
70
2
2/4
Branch if not equal
if ( Z ) = 0 , then pc ← ( pc ) + rel
--------
10
BPL rel
10
2
2/4
Branch if minus
if ( N ) = 0 , then pc ← ( pc ) + rel
--------
11
BRA rel
2F
2
4
Branch always
pc ← ( pc ) + rel
--------
12
BVC rel
30
2
2/4
Branch if overflow bit clear
if (V) = 0 , then pc ← ( pc) + rel
--------
13
BVS rel
B0
2
2/4
Branch if overflow bit set
if (V) = 1 , then pc ← ( pc ) + rel
--------
14
CALL !abs
3B
3
8
15
CALL [dp]
5F
2
8
16
CBNE dp,rel
FD
3
5/7
17
CBNE dp+X,rel
8D
3
6/8
18
DBNE dp,rel
AC
3
5/7
Decrement and branch if not equal :
19
DBNE Y,rel
7B
2
4/6
if ( M ) ≠ 0 , then pc ← ( pc ) + rel.
20
Subroutine call
M( sp)←( pcH ), sp←sp - 1, M(sp)← (pcL), sp ←sp - 1,
-------if !abs, pc← abs ; if [dp], pcL← ( dp ), pcH← ( dp+1 ) .
-------Compare and branch if not equal :
if ( A ) ≠ ( M ) , then pc ← ( pc ) + rel.
--------
JMP !abs
1B
3
3
21
JMP [!abs]
1F
3
5
22
JMP [dp]
3F
2
4
23
PCALL upage
4F
2
6
U-page call
M(sp) ←( pcH ), sp ←sp - 1, M(sp) ← ( pcL ),
sp ← sp - 1, pcL ← ( upage ), pcH ← ”0FFH” .
--------
24
TCALL n
nA
1
8
Table call : (sp) ←( pcH ), sp ← sp - 1,
M(sp) ← ( pcL ),sp ← sp - 1,
pcL ← (Table vector L), pcH ← (Table vector H)
--------
Unconditional jump
pc ← jump address
--------
Mar. 2005 Ver 0.2
MC80F0104/0204
Preliminary
6. CONTROL OPERATION & etc.
NO.
MNEMONIC
OP BYTE CYCLE
CODE NO
NO
OPERATION
FLAG
NVGBHIZC
1
BRK
0F
1
8
Software interrupt : B ← ”1”, M(sp) ← (pcH), sp ←sp-1,
M(s) ← (pcL), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1, ---1-0-pcL ← ( 0FFDEH ) , pcH ← ( 0FFDFH) .
2
DI
60
1
3
Disable interrupts : I ← “0”
-----0--
3
EI
E0
1
3
Enable interrupts : I ← “1”
-----1--
4
NOP
FF
1
2
No operation
--------
5
POP A
0D
1
4
sp ← sp + 1, A ← M( sp )
6
sp ← sp + 1, X ← M( sp )
POP X
2D
1
4
7
POP Y
4D
1
4
sp ← sp + 1, Y ← M( sp )
8
POP PSW
6D
1
4
sp ← sp + 1, PSW ← M( sp )
9
PUSH A
0E
1
4
M( sp ) ← A , sp ← sp - 1
10
PUSH X
2E
1
4
M( sp ) ← X , sp ← sp - 1
11
PUSH Y
4E
1
4
M( sp ) ← Y , sp ← sp - 1
12
PUSH PSW
6E
1
4
M( sp ) ← PSW , sp ← sp - 1
-------restored
--------
13
RET
6F
1
5
Return from subroutine
-------sp ← sp +1, pcL ← M( sp ), sp ← sp +1, pcH ← M( sp )
14
RETI
7F
1
6
Return from interrupt
sp ← sp +1, PSW ← M( sp ), sp ← sp + 1,
pcL ← M( sp ), sp ← sp + 1, pcH ← M( sp )
restored
15
STOP
EF
1
3
Stop mode ( halt CPU, stop oscillator )
--------
Mar. 2005 Ver 0.2
vii
MC80F0104/0204
viii
Preliminary
Mar. 2005 Ver 0.2
MASK ORDER SHEET
MASK ORDER & VERIFICATION SHEET
MC80C0104
-
Customer should write inside thick line box.
1. Customer Information
Company Name
2. Device Information
Package
16PDIP
16SOP
POR
Yes
No
R35 Use
Yes
No
ONP Use
Yes
No
OFP Use
Yes
No
Application
YYYY
Order Date
Tel:
MM
DD
Fax:
Name &
Signature:
Crystal
CLK
3. Marking Specification
Mask Data
MC80C0104x-xxx
YYWW KOREA
IN4M
IN4MXO
IN2M
IN2MXO
EXRC
EXRCXO
File Name: (
.OTP)
Check Sum: (
)
0000H
Notice : Unused user
ROM area should
be filled with “00H”
#1 index mark
Set “00” in
this area
EFFFH
F000H
.OTP file data
FFFFH
(Please check mark into
4. Delivery Schedule
Quantity
Date
Customer Sample
Risk Order
YYYY
MM
DD
YYYY
MM
DD
5. ROM Code Verification
Verification Date:
YYYY
Please confirm our verification data.
Tel:
Name &
Signature:
pcs
pcs
DD
Approval Date:
Fax:
YYYY
MM
DD
I agree with your verification data and confirm
you to make mask set.
Tel:
Check Sum:
MagnaChip Confirmation
This box is written after “5.Verification”.
MM
Name &
Signature:
)
Fax:
MASK ORDER SHEET
MASK ORDER & VERIFICATION SHEET
MC80C0204
-
Customer should write inside thick line box.
1. Customer Information
Company Name
2. Device Information
Package
20PDIP
20SOP
POR
Yes
No
R35 Use
Yes
No
ONP Use
Yes
No
OFP Use
Yes
No
Application
YYYY
Order Date
Tel:
MM
DD
Fax:
Name &
Signature:
Crystal
CLK
3. Marking Specification
Mask Data
MC80C0204x-xxx
YYWW KOREA
IN4M
IN4MXO
IN2M
IN2MXO
EXRC
EXRCXO
File Name: (
.OTP)
Check Sum: (
)
0000H
Notice : Unused user
ROM area should
be filled with “00H”
#1 index mark
Set “00” in
this area
EFFFH
F000H
.OTP file data
FFFFH
(Please check mark into
4. Delivery Schedule
Quantity
Date
Customer Sample
Risk Order
YYYY
MM
DD
YYYY
MM
DD
5. ROM Code Verification
Verification Date:
YYYY
Please confirm our verification data.
Tel:
Name &
Signature:
pcs
pcs
DD
Approval Date:
Fax:
YYYY
MM
DD
I agree with your verification data and confirm
you to make mask set.
Tel:
Check Sum:
MagnaChip Confirmation
This box is written after “5.Verification”.
MM
Name &
Signature:
)
Fax: