HD49801FB Preliminary Digital Signal Processing IC for CCD Cameras Description The HD49801FB is an IC that integrates all the functions re q u i red for CCD camera signal processing (except the CDS and AGC blocks) in a single chip. • Allows microprocessor control (over a serial interface) of all image quality controls. • Handles all fo rm ats; NTSC, PAL, SECAM ( h oweve r, does not include a SECAM encoder). Features • Handles 510H/760H CCD image sensors. • Generates high quality chroma and luminance signals using three-line mat rix pro c e s s i n g supported by a built-in line memory (1H × 2). 1 HD49801FB HD49801FB Pin Functions Pin No. Pin Name Signal I/O 1 PLLPO PLL posi out O 2 PLLNO PLL nega out O 3 VRI Vertical reset in I External reset input for the vertical synchronization signal; high = reset 4 CBLKO Composite blanking out O Composite horizontal and vertical blanking signal 5 CSYNCO Composite SYNC out O Composite horizontal and vertical synchronization and blanking signal 6 VDO Vertical driving out O Vertical synchronization signal 7 FVO Field vertical out O Field vertical synchronization signal 8 BFO Burst flag out O Burst flag output 9 IDO Line ID out O Line ID PAL: High = (R-Y) +, low = (R-Y) – SECAM: High = B-Y, low = R-Y 10 SSG VSS VSS for SSG VSS SSG (SYNC signal generator) ground 11 FF SCO 4fsc out O 4fsc output 12 PAD VSS VSS for PAD VSS PAD VSS 13 X4FSCI 4fsc osc in osc 4fsc oscillator circuit input (NTSC: 4fsc = 14.31818 MHz) 14 X4FSCO 4fsc osc out osc 4fsc oscillator circuit output (PAL/SECAM: 4fsc = 17.734475 MHz) 15 SCO Sub carrier out O fsc output 16 CCK C clock for DAC O Clock output for chroma signal (C) D/A converter; frequency = 4fsc Chroma signal (C) output (Data format: offset binary) 17 CO (8) Chroma out (8): MSB O 18 CO (7) Chroma out (7) O 19 CO (6) Chroma out (6) O 20 CO (5) Chroma out (5) O 21 CO (4) Chroma out (4) O 22 CO (3) Chroma out (3) O Function Description In PAL/SECAM modes, the fsc and fH gen lock phase detection output 23 CO (2) Chroma out (2) O 24 CO (1) Chroma out (1): LSB O 25 TEST1 Test 1 I Test pin: Fix at the low level 26 YCK Y clock for DAC O Clock output for luminance signal (Y) D/A converter; frequency = 4fsc 27 YO (8) Y out (8): MSB O Luminance signal (Y) output 28 YO (7) Y out (7) O 29 YO (6) Y out (6) O 30 YO (5) Y out (5) O 31 YO (4) Y out (4) O 32 YO (3) Y out (3) O 33 YO (2) Y out (2) O 34 YO (1) Y out (1): LSB O 2 HD49801FB HD49801FB Pin Functions (cont) Pin No. Pin Name Signal I/O 35 YPO (8) Y pararell out (8): MSB O 36 YPO (7) Y pararell out (7) O 37 YPO (6) Y pararell out (6) O 38 CORE VDD VDD for core VDD Function Description Y digital interface output Outputs the post-gamma compensation Y signal VDD for core, VDD = 5 V +0.25 V –0.50 V 39 YPO (5) Y pararell out (5) O 40 YPO (4) Y pararell out (4) O 41 YPO (3) Y pararell out (3) O 42 YPO (2) Y pararell out (2) O 43 YPO (1) Y pararell out (1): LSB O 44 YPI (8) Y pararell in (8): MSB I 45 YPI (7) Y pararell in (7) I 46 YPI (6) Y pararell in (6) I 47 YPI (5) Y pararell in (5) I 48 YPI (4) Y pararell in (4) I 49 YPI (3) Y pararell in (3) I 50 YPI (2) Y pararell in (2) I 51 YPI (1) Y pararell in (1): LSB I 52 CPO (4) C pararell out (4): MSB O 53 CPO (3) C pararell out (3) O 54 CPO (2) C pararell out (2) O 55 CPO (1) C pararell out (1): LSB O 56 CPI (4) C pararell in (4): MSB I Y digital interface output Y digital interface input C digital interface output (data format: two’s complement) Color difference signals R-Y and B-Y Upper to lower order C digital interface input (data format: two’s complement) 57 CPI (3) C pararell in (3) I 58 CPI (2) C pararell in (2) I 59 CPI (1) C pararell in (1): LSB I 60 NRYBYO R-Y, B-Y phase out O 61 DICKO Digital interface clock out O 62 CORE VSS VSS for core VSS VSS for core 63 HREFI Horizontal reference in I Horizontal scan reference signal Reference for memory start/stop, BF, CBLK, and CSYNC 64 HGI Horizontal gate in I Line signals (two types) determination input; high = a, b; low = c, d (state data A7) 65 SCKI Sensor clock in I Sensor clock (system clock) fs input 66 ADI (9) AD in (9): MSB I A/D input 67 ADI (8) AD in (8) I 68 ADI (7) AD in (7) I C digital interface phase output; high = (B-Y) phase, low = (R-Y) phase Digital interface clock output, frequency = fs 3 HD49801FB HD49801FB Pin Functions (cont) Pin No. Pin Name Signal I/O Function Description 69 ADI (6) AD in (6) I A/D input 70 ADI (5) AD in (5) I 71 ADI (4) AD in (4) I 72 ADI (3) AD in (3) I 73 ADI (2) AD in (2) I 74 ADI (1) AD in (1): LSB I 75 ADI (0) AD in (0) I Fix at the low level 76 OBPI Optical black pulse in I Sensor optical black period input; high during the OB period 77 CPREFO Clamp reference out O Feedback clamp OBP detection output (0 V to 5 V) 78 KNEEO Knee point out O 79 EP3O Iris V edge pulse 3 out O 80 EP2O Iris V edge pulse 2 out O Knee point setting output; high = iris region 6 V direction iris setting region Iris V-window pulse 3 output Iris V-window pulse 2 81 EP1O Iris V edge pulse 1 out O Iris V-window pulse 1 82 TBI Titler B in I Title color setting signal 83 TGI Titler G in I 84 TRI Titler R in I 85 TKEYI Titler key in I Title on/off signal; high = on, low = off 86 NMEI Memory enable bar in I Line memory R/W enable signal; high = disable, low = enable 87 IWNI Iris/white balance in I DETSO function selection (iris/WB) input; high = iris, low = WB 88 PAD VDD VDD for PAD VDD 89 DETLDI DET load in I Iris/WB load pulse 90 DETCKI DET clock in I Iris/WB clock pulse 91 DETSO DET serial out O Iris: Average value (22b)/peak value (11b) WB: Mg-G (11b), R-B (11b) 92 SLDI State load in I Image quality control data (state data) load pulse 93 STCKI State clock in I Image quality control data (state data) clock pulse 94 SDI State data in I Image quality control data (state data) input 95 IDSI Line ID reset in I In PAL/SECAM mode, line ID reset input; high = reset 96 TGSYNCO TG sync out O TG CSYNC output 97 CHDO Camera HD out O Camera horizontal synchronization output 98 SSG VDD VDD for SSG VDD 99 XHCKI H osc in osc H oscillator input (NTSC: 260 fH = 4.090908 MHz) 100 XHCKO H osc out osc H oscillator output (PAL/SECAM: 282 fH = 4.40625 MHz) 4 VDD for pad, VDD = 5 V +0.25 V –0.50 V VDD for SSG, VDD = 5 V +0.25 V –0.50 V HD49801FB HD49801FB CO CCK YO YCK Block Diagram 8 (D1 to D18) 8 (A1 to A16) A9 Modulator A8 Title fade inversion State data interface SDI STCKI SLDI Titler in TBI TGI TRI TKEYI C-Y C-YW gain gain A6 C-Y matrix A5 A4 γ compensation 4 Digital interface RGB gain A5 RGB set up + CPI CPO YPI YPO NRYBYO DICKO 4 8 8 γ compensation A12 A1 to A3 RGB matrix A7 W/B detection + A10 C clip level Y setup DETSO Iris/WB interface DETLDI DETCKI IWNI Iris detection Color distribution A13 H clip, enhancer V clip, enhancer EP1O EP2O EP3O KNEEO C filter 1 C filter 2 A11 H Y filter V + A15 1HDL A14 1HDL (fs block) Control Internal TG SSG (4fsc block) OBP detect IDO BFO CSYNCO CBLKO TGSYNCO CHDO VDO FVO 3 3 VDD V SS ADI0 X4FSCI X4FSCO FFSCO SCO HOSCI HOSCO PLLPO PLLNO VRI IDSI HREFI HGI SCKI TESTI OBPI CPREFO ADII-9 NMEI 9 Note: A1 to A15 indicate state data. 5 HD49801FB HD49801FB Standard External Circuits Y interface outputs Y interface outputs Y signal outputs Y DAC clock output + – 100 µF/6.3 V 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 Y interface inputs C interface inputs C interface outputs C digital interface phase output Digital interface clock output Synchronization pulse inputs A/D inputs 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 HD49801FB 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Y interface input Iris pulse output + – 10 µF/ 6.3 V OBP input Iris/WB control pulse inputs 47 µF Image quality control pulse outputs 5V DET SO selection DET SO Synchronization pulse outputs + 100 µF/ 6.3 V Units: R: Ω C: F L: H NTSC Standard External Circuits 6 0.1 µF 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Color signal outputs 1 MΩ CDAC clock output fsc output 15 pF X’tal 14.31818 MHz 25 pF 4fsc output Synchronization pulse outputs HD49801FB HD49801FB Standard External Circuits (cont) Y interface outputs Y interface outputs + – Y DAC clock output Y signal outputs 100 µF/6.3 V 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 Y interface inputs C interface outputs C digital interface phase output Digital interface clock output Synchronization pulse inputs A/D inputs HD49801FB Iris pulse output + – 10 µF/ 6.3 V OBP input Iris/WB control pulse inputs 47 µF Image quality control pulse outputs 5V DET SO selection DET SO 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Synchronization pulse outputs 1500 pF + 100 µF/ 6.3 V 1M C interface inputs 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Y interface input Color signal outputs CDAC clock output fsc output 1 MΩ 15 pF X’tal 17.73 MHz 25 pF 4fsc output Synchronization pulse outputs X’tal 4.406 MHz 0.1 µF 56 kΩ 470 kΩ 0.1 µF 50 pF 100 kΩ 0.1 µF Units: R: Ω C: F L: H PAL Standard External Circuits 7 HD49801FB HD49801FB Absolute Maximum Ratings (Ta = 25°C) Item Symbol Rated Value Unit Power supply voltage VCC –0.3 to +6.7 V Pin voltage Vti –0.3 to VCC + 0.3 V Pin voltage Vto –0.3 to VCC + 0.3 V Corresponding to one output Io –16 to +16 mA Corresponding to one GND to VCC Iot –70 to +70 mA Operating temperature Topr –10 to +75 °C Storage temperature Tstg –55 to +125 °C Output voltages Notes: 1. This IC can be permanently damaged by operating at values in excess of its absolute maximum ratings. Furthermore, it is desirable to operate this IC within the conditions for the electrical characteristics specifications during normal operation. Exceeding those conditions can result in incorrect operation and a reduction in reliability. 2. All voltages are specified with GND = 0 V as the reference. 3. This IC is for use in consumer products. It should not be used in industrial products, or in products that will be used outdoors for extended periods. +0.25 V Electrical Characteristics (VCC = 5 V –0.50V Ta = –10°C to +75°C) Item Symbol Min Typ Max Unit Test Conditions Input voltages* VIHC VCC × 0.7 — — V CMOS levels VILC — — VCC × 0.3 V CMOS levels VOH 2.4 — — V IOH = 2/4 mA VOL — — 0.4 V IOL = –2/–4 mA Input leakage current ILI –1.0 — 1.0 µA VIN = 0 to VCC Output leakage current ILO –1.0 — 1.0 µA Output high impedance state Current dissipation ICC — — 110 mA With VCC = 5 V, and no load, Ta = 25°C, fCLK = 14.3 MHz Output voltages* Note: * I/O voltage levels are measured in steady state. 8 HD49801FB HD49801FB Crystal Oscillator Circuit • Test conditions VCC = 5 V ± 5% Cin, Cout = 22 pF Rf = 10 MΩ • Test method Test at fmin = 8 MHz and fmax = 20 MHz under the above conditions. Note that the oscillator start time (tosc max) is 250 ms. To the internal oscillator Rf Xin Xout Divider counter Cin Monitor pin Cout Counter Test Circuit 9 HD49801FB HD49801FB Overview of Pixel Mixing CCD-RGB Simultaneous Processing G Mg G Mg G Mg Cy Ye Cy Ye Cy Ye Mg G Mg G Mg G Cy Ye Cy Ye Cy Ye G + Cy Mg + Ye G + Cy Mg + Ye Mg + Cy G + Ye Mg + Cy G + Ye G + Cy = G + (G + B) = 2G + B = Gb Mg + Ye = (R + B) + (R + G) = (R + G + B) + R = Wr Mg + Cy = (R + B) + (G + B) = (R + G + B) + B = Wb G + Ye = G + (G + B) = 2G + R = Gr Pixel Mixing CCD Mode Figure RGB matrix R K Gb.r K Wr.r K Wb.r G = K Gb.g K Wr.g K Wb.g K Gr.g B K Wr.b K Wb.b K Gr.b K Gb.b K Gr.r Gb Wr Wb Gr Y matrix • Line N Y = Gb + Wr = (2G + B) + (2R + G + B) = 2R + 3G + 2B • Line (N + 1) Y = Wb + Gr = (R + G + 2B) + (2G + R) = 2R + 3G + 2B 10 Line N Line (N + 1) HD49801FB HD49801FB Line Signal Processing RGB matrix Rn + 1 Gn + 1 =A Bn + 1 Gbn Wrn (Wbn – 1 + Wbn + 1)/2 (Grn – 1 + Grn + 1)/2 C-Y matrix (R-Y)n + 1 (B-Y)n + 1 Rn + 1 =C Gn + 1 = CA Bn + 1 Gbn Wrn (Wbn – 1 + Wbn + 1)/2 (Grn – 1 + Grn + 1)/2 Three line signal processing n–1 Sensor output 1 HDL memory n 1 HDL memory n+1 C processing • RGB matrix • Gamma, C-Y Y processing • Enhancer • Gamma R-Y B-Y Y CCD Camera RGB Simultaneous Processing 11 12 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A State Data 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 Address H 0 Address H 0 Address H 1 Address H 1 Address H 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Notes Sign KcR Sign KbR Sign KaR Sign KcG Sign KbG Sign KaG B gain Exponent Sign Mantissa G gain KcB Exponent Sign Mantissa R gain KbB Exponent Sign Cr dark clip Yr control R-Y gain C base clip c base clip b base clip a base clip Data Data Setup data H base clip V enhancer gain V base clip H enhancer noise coefficient Data Count value Data (timing) D1 D2 D3 D4 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Address L D1 D2 D3 D4 D1 D2 D3 D4 D5 Address L D1 D2 D3 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 Address L D1 D2 D3 D4 D5 D1 D2 D3 D4 D1 D2 D3 D4 D5 D1 D2 D3 D4 D1 D2 D3 D4 D5 D1 D2 H enhancer gain D1 D2 D1 D2 D3 D4 D5 D6 D7 D8 D9 Address L D1 D2 D1 D2 D3 D4 D5 D6 D7 Address L D1 D2 D3 D1 D2 D3 D4 D5 D6 D7 D8 Address L H enhancer frequency characteristics D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 D2 D3 D4 D5 D6 D7 D8 D9 d base clip D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 B-Y gain D1 D2 D3 D1 D2 D3 D1 D2 D3 Cr control D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 Mantissa KdB KaB Mode, test H synchronization pulse timing Iris detection W/B detection Y enhancer base clip Y, R, G, B setup Encoder (MOD) Encoder (FAD) Clip level: 9 bits Color difference gain: 7 bits Burst level: 7 bits Burst clip: 3 bits γ control: 3 bits 8 stages (0 to 1) W/B RGB gain Mantissa: 3 bits Exponent: 8 bits B matrix coefficients Sign (11 bits × 4 channels) 10 bits + 1 sign bit D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 KdG G matrix coefficients Sign (11 bits × 4 channels) 10 bits + 1 sign bit D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 KdR R matrix coefficients Sign (11 bits × 4 channels) 10 bits + 1 sign bit D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 Address HD49801FB HD49801FB State Data Table HD49801FB HD49801FB State Data Details The following items describe the state data (A1 to A16) in detail. State Data A1 to A3: RGB matrix This data specifies color reproducibility and moire pattern suppression. Coefficient K Gb , j Coefficient K Wr, j Coefficient K Wb, j Coefficient K Gr , j Address DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD DD 0 0 1110 9 8 7 6 5 4 3 2 1 1110 9 8 7 6 5 4 3 2 1 1110 9 8 7 6 5 4 3 2 1 1110 9 8 7 6 5 4 3 2 1 2 1 Mantissa (j = RGB) Exponent Address Matrix Gb 0 0 0 0 R Wr 0 0 0 1 G Wb 0 0 1 0 B Gr R G = A (Kij) B Gb Wr Wb Gr R G B Kij Kij = (–1)D11 · 2–(D10 × 2 + D9 × 2 ) · (D8 × 2–1 + D7 × 2–2 + D6 × 2–3 + D5 × 2–4 + D4 × 2–5 + D3 × 2–6 + D2 × 2–7 + D1 × 2–8) 1 0 Where: i = Gb, Wr, Wb, Gr j = R, G, B Determine the size of the coefficients so that MAX (KGbj, KWrj, KWbj, KGrj) = 255/256(00011111111). State Data A4: W/B RGB gain This data adjusts the amplitude of the color signal and determines the color reproducibility. It also adjusts the white balance for images of white objects. R gain: GR G gain: G G B gain: GB Address DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 0 0 1 1 1110 9 8 7 6 5 4 3 2 1 1110 9 8 7 6 5 4 3 2 1 1110 9 8 7 6 5 4 3 2 1 Mantissa Exponent Gi = 2 (D11 × 22 + D10 × 21 + D9 × 20 + 1) · (D8 × 2–1 + D7 × 2–2 + D6 × 2–3 + D5 × 2–4 + D4 × 2–5 + D3 × 2–6 + D2 × 2–7 + D1 × 2–8) 13 HD49801FB Max HD49801FB D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Gi 1 0 1 1. .. 1 1. .. 0 1. .. 0 1. .. 0 1. .. 0 1. .. 0 1. .. 0 1. .. 0 26 × 255/256 .. . 26 × 128/256 1 0 0 1. .. 1 1. .. 0 1. .. 0 1. .. 0 1. .. 0 1. .. 0 1. .. 0 1. .. 0 25 × 255/256 .. . 25 × 128/256 0 0 1 1. .. 1 1. .. 0 1. .. 0 1. .. 0 1. .. 0 1. .. 0 1. .. 0 1. .. 0 22 × 255/256 .. . 22 × 128/256 0 0 0 1. .. 0 1. .. 0 1. .. 0 1. .. 0 1. .. 0 1. .. 0 1. .. 0 1. .. 0 255/256 .. . 0 Min • Setting the gains — Set up the RGB matrix. — Adjust the black level for the above matrix. — Hold G R and G B at 0, and increase GG. Determine the gain at which the output signal is saturated, and take half of that gain to be the rated gain. — Determine GR and GB for the gain GG determined above. 14 HD49801FB HD49801FB State Data A5: γ characteristics One of eight different curves can be selected for the γ characteristics by specifying the value (0 to 7) of this state data item. (output) 256 0123 4 5 6 7 192 128 64 256 0 512 768 1023 (input) (1) Y- γ I/O characteristics (state data values 0 to 7) (output) 255 192 7 128 0 64 0 512 1023 (input) (2) C- γ I/O characteristics (state data values 0 to 7) (output) (output) 64 64 7 a 6 1 0 a 0 128 256 (input) (3) CL- γ I/O characteristics (state data values 0, 2, 4, and 6) C-γ state data value 0 (shifted by only the amount a from the output level of (2)) 0 128 256 (input) (4) CL- γ I/O characteristics (state data values 1, 3, 5, and 7) C-γ state data value 0 (shifted by only the amount a from the output level of (2)) 15 HD49801FB HD49801FB State Data A6: Color difference gain, base clip This data determines the signal levels of the color difference signals. C clip CLC R-Y gain G R-Y Address R-Y gain G R-Y D3 D2 D1 D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1 • 0 1 0 1 Color difference gain control characteristics R-Y – 8 GR-Y –CL C × +CL C 127 128 to + 256 256 Out 8 (R-Y)' In Base clip B-Y 8 GB-Y –CL C × +CL C – 8 (B-Y)' 127 128 to + 256 256 0 to 7 256 CL C GR-Y, GB-Y = D7 × 20 + D6 × 2–1 + D5 × 2–2 + D4 × 2–3 + D3 × 2–4 + D2 × 2–5 + D1 × 2–6 (0 to 2) • Base clip level control characteristics CLC max = 7/256 = 0.0273437 CLC = D3 × 2–6 + D2 × 2–7 + D1 × 2–8 • Setting the gains (a) The ratio of the gains R-Y and B-Y is determined by the color reproduction. (b) Increase the color difference gain from the gain ratio from item (a) above. (c) Set the gain to have a 10% to 20% margin from the gain at the point the output signal clips in item (b) above. I.e., (set gain) = (clipping gain) × 0.8 to 0.9 16 HD49801FB HD49801FB State Data A7: C clip level This data varies the clip levels for the complementary color signals Wr, Wb, Gr, and Gb, and determines the color reproduction. HGI pin For example: (Wrn Gbn Grn Wbn) an Sn From the line delay C filter 1 C filter 2 bn cn dn an + 1 bn + 1 cn + 1 dn + 1 Limiter Color distribution Out Sn – 1 + Sn + 1 2 Address data A7 state a level b level c level d level MPX Clip a b c d a b Data c d Address DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 2019181716151413121110 9 8 7 6 5 4 3 2 1 a clip level b clip level c clip level d clip level DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 0 1 1 0 9 8 7 6 5 4 3 2 1 9 8 7 6 5 4 3 2 1 9 8 7 6 5 4 3 2 1 9 8 7 6 5 4 3 2 1 • Setting the clip levels — When saturation occurs within the ADC D range: Let A be the level of a saturated pixel, and taking the white light signal levels to be Wa, Wb, Wc, and Wd, (clip level) = A × Wi/Wmax (Wmax = max {Wi}, i = a, b, c, d) — When saturation occurs above the ADC D range: White light signal levels to be Wa, Wb, Wc, and Wd, (clip level) = 511/512 × Wi/Wmax (Wmax = max {Wi}, i = a, b, c, d) 17 HD49801FB HD49801FB State Data A8 (1 to 3): Encoder (FADE) This data determines the fade level for the luminance and chroma signals. Address H Data Address D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Y fade 1 1 1 1 0 0 0 0 D1 D2 D3 D4 D5 D6 D7 D8 C fade 2 1 1 1 0 1 0 0 D1 D2 D3 D4 D5 D6 D7 D8 Y inversion 3 1 1 1 0 0 1 0 C inversion D1 D2 1: Y fade D8 = 1: Through When D8 = 0, the following weighting formula is used. D7 × 2–1 + D6 × 2–2 + D5 × 2–3 + D4 × 2–4 + D3 × 2–5 + D2 × 2–6 D1 is fixed at 0. Note: However, since the encoder fade precision is inadequate, improved fading characteristics can be obtained by using the iris function for Y fading. 2: C fade D8 × 20 + D7 × 2–1 + D6 × 2–2 + D5 × 2–3 + D4 × 2–4 + D3 × 2–5 + D2 × 2–6 + D1 × 2–7 Range: 1 to 255/128 3: Y and C inversion D1 = 0; D2 = 0: Normal D1 = 1; D2 = 1: Inversion 18 HD49801FB HD49801FB State Data A9: 1 to 4 (MOD) Determines the luminance signal black level and the chroma signal burst level. These four data items determine the (R-Y) burst level for PAL format TV signals. Address H Address Data D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 BLK level 1 0 0 0 1 0 0 D1 D2 D3 D4 D5 D6 D7 D8 Pedestal * 2 0 0 0 1 1 0 D1 D2 D3 D4 D5 D6 D7 D1 Burst level (B-Y) 3 0 0 0 1 0 1 D1 D2 D3 D4 D5 D6 D7 Burst level (R-Y) 4 0 0 0 1 1 1 D1 D2 D3 D4 D5 D6 D7 Note: Set D1 according to the delay sensor clock as follows. 14.3 MHz: D1 = 1 9.5 MHz: D1 = 0 • State data A9 (1 to 4): Encoder (MOD) control characteristics 1: Setup (D7 × 26 + D6 × 25 + D5 × 24 + D4 × 23 + D3 × 22 + D2 × 21 + D1) × 2/256 2: Pedestal D7 × 26 + D6 × 25 + D5 × 24 + D4 × 23 + D3 × 22 + D2 × 21 + D1/256 Note: However, when the A9 to A2 D8 bit (delay) is set to 1, the Y data is delayed by one fs clock cycle. 3: Burst level (B-Y) D7 × 26 + D6 × 25 + D5 × 24 + D4 × 23 + D3 × 22 + D2 × 21 + D1/256 4: Burst level (R-Y) • Used in PAL mode • In NTSC mode, used for phase adjustment Rating A 192 Pedestal Display period 256 . . . . . . . . B .. . . . . . . . . 0 Output D range (B/A) × 100% The D range can be set by changing the pedestal and BLK levels. BLK level 19 HD49801FB HD49801FB State Data A10 (1 to 4): Y, R, G, B setup This data determines the black color when black objects are imaged, and the color reproduction. Address H Data Address D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Y setup 1 1 0 0 1 0 0 D1 D2 D3 D4 D5 D6 D7 B setup 2 1 0 0 1 1 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 G setup 3 1 0 0 1 0 1 D1 D2 D3 D4 D5 D6 D7 D8 D9 R setup 4 • 1 0 0 1 1 1 D1 D2 D3 D4 D5 D6 D7 D8 D9 State data A10: Y, R, G, B setup 1: Y setup D7 × 2–4 + D6 × 2–5 + D5 × 2–6 + D4 × 2–7 + D3 × 2–8 + D2 × 2–9 + D1 × 2–10 Note: The Y setup is the initial state Y level minus the value calculated above. 2 to 4: R, G, B setup –D9 × 2–4 + D8 × 2–5 + D7 × 2–6 + D6 × 2–7 + D5 × 2–8 + D4 × 2–9 + D3 × 2–10 + D2 × 2–11 + D1 × 2–12 Note: D9 is the sign bit. This is a two’s complement value. • Notes on setup level adjustment Adjust the black level after setting the RGB matrix. The iris detection block can be used to adjust the black level. When a color difference signal is input to the iris detection block the difference with the setup target value for the specified area can be detected. Processing this detection output allows, for example, the black level to be adjusted by adjusting the R, G, B setup levels. The color difference signal is input to the iris detection block using the following method. D1 D2 D3 D4 State data A13 to A15 Address L Data D9 20 0 High 1 1 1 HD49801FB HD49801FB State Data A11: H and V enhancer This data specifies boundary compensation on video signals. H enhancer frequency characteristics H enhancer noise coefficient: KH1 V base clip CLV V enhancer noise coefficient: KV H base clip CLH H enhancer coefficient: KH2 D2 D1 D5 D4 D3 D2 D1 D4 D3 D2 D1 D5 D4 D3 D2 D1 D4 D3 D2 D1 D5 D4 D3 D2 D1 1 Address 0 1 0 Out CLH CLH KH2 In KH1 KH1, KH2, KV = D5 × 2–1 + D4 × 2–2 + D3 × 2–3 + D2 × 2–4 + D1 × 2–5 (0 to 1) CLV, CLH = D4 × 23 + D3 × 22 + D2 × 21 + D2 × 20/1024 H Enhancer: Frequency characteristics D2 D1 Peak Frequency 0 0 0.25 fs 0 1 0.25 fs 1 0 0.275 fs 1 1 0.3 fs 21 HD49801FB HD49801FB State Data A12 (1 to 5): White balance detection This data determines the white balance detection region, sets the dead band, and determines the control range. Address H Address Data D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 R-Y gain 1 1 1 0 1 0 0 0 D1 D2 D3 D4 D1 D2 D3 D4 Y level 1 2 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 1 1 1 0 1 1 0 1 0 0 1 C level 1 – D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 D4 D5 D6 D7 C level 2 + 5 Offset – D1 D2 D3 D4 D5 D6 D1 D2 D3 D4 D5 D6 C level 1 + 4 Y level 2 D1 D2 D3 D4 D1 D2 D3 D4 Offset + 3 B-Y gain C level 2 – D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 D4 D5 D6 D7 1: R-Y gain, B-Y gain These adjust the R-B/Mg-g detection axis. Gain = D4 × 2–1 + D3 × 2–2 + D2 × 2–3 + D1 × 2–4 2: Y level 1, Y level 2 When the Y signal is used as the white detection area data, the Y signal detection range is set by Y level 1 (lower bits) and Y level 2 (upper bits). The data consists of 8 bits, and the upper 4 bits (D1 to D4) can be changed. 3: Offset The control center can be shifted by setting the offset. Of the 8 bits of this data, the data that can be changed consists of 6 bits (64/256 = 1/4), and the offset level can be changed over up to 1/4 of the full data range. 22 HD49801FB HD49801FB 4, 5: C levels This data specifies the white detection region. Of all 8 bits of this data, the data that can be changed consists of 7 bits (128/256 = 1/2), and the white detection region can be changed over up to 1/2 of the full data range. The C level data correspondences are as follows: C level 1 + → The down direction of the (Mg-G) signal. C level 1 – → The down direction of the (R-B) signal. C level 2 + → The up direction of the (Mg-G) signal. C level 2 – → The up direction of the (R-B) signal. R-Y R-B (256) 94% Mg-G Color temperature variation 100% Variable width (16 divisions) B-Y 6% (0) 0% Y Detection Variable Width R-Y/B-Y R, G, B gain Parallelserial conversion White detection U/D counter White detection range +/– Offset Mg-G/R-B R-Y/B-Y gain adjustment (detection axis adjustment) Y level detection Y Microprocessor White Balance Detection Block Diagram 23 HD49801FB HD49801FB State Data A13 (1 to 16): Iris This data determines the regions required for iris control, and selects the type of iris data to be extracted. Address H Data Address D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 H count 1 1 0 0 1 1 0 0 0 0 D1 D2 D3 D4 D5 H count 2 2 0 0 1 1 1 0 0 0 D1 D2 D3 D4 D5 H count 3 3 0 0 1 1 0 1 0 0 D1 D2 D3 D4 D5 H count 4 4 0 0 1 1 1 1 0 0 D1 D2 D3 D4 D5 H count 5 5 0 0 1 1 0 0 1 0 D1 D2 D3 D4 D5 H count 6 6 0 0 1 1 1 0 1 0 7 0 0 1 1 0 1 1 0 8 0 0 1 1 1 1 1 0 D1 D2 D3 D4 D5 V count 1 9 0 0 1 1 0 0 0 1 D1 D2 D3 D4 D5 V count 2 10 0 0 1 1 1 0 0 1 D1 D2 D3 D4 D5 V count 3 11 0 0 1 1 0 1 0 1 D1 D2 D3 D4 D5 V count 4 12 0 0 1 1 1 1 0 1 D1 D2 D3 D4 D5 V count 5 13 0 0 1 1 0 0 1 1 D1 D2 D3 D4 D5 Peak detection region 14 0 0 1 1 1 0 1 1 D1 D2 D3 Knee 15 0 0 1 1 0 1 1 1 D1 D2 Iris region 16 24 0 0 1 1 1 1 1 1 D1 D2 D3 HD49801FB • HD49801FB Iris Pattern 1 is selected if the H count 6 is in the blanking period, and pattern 2 is selected otherwise. H count 2 3 4 5 V count 1 1 2 3 4 5 6' 1 2 6 5 3 3 — However, the detection region can be set to an arbitrary region (regions 1 to 6). Each region can be changed in units of 32 fs-1 horizontally, and 16 lines vertically. 5 1' 5 3 4 3' Pattern 2 State Data — Also, once for each field, the peak value for region 1 is detected. 6 6 Pattern 1 — The full integrated value (the average value of Y following γ processing) for each region is calculated for each field. 4 2 1 2 3 4 5 4 The screen is divided into 6 regions 2 1 V count 1 H count D3 D2 D1 Region 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 Peak data Note: For the peak data, the region is specified by the A13 to A14 peak detection region. Iris control is performed with the average value acquired by adding the weighted average values for each region. 6 Σ Y i · ki Y = i=1 6 Σ ki Where: Y: The average value for a single field. Yi: The average value for each region. ki: The weighting for each region. i=1 25 HD49801FB • HD49801FB The meaning and use of EP1O, EP2O, and EP3O These operate as the iris V window pulses, and output V direction edge pulses for the iris detection region. EP1O 26 EP2O EP3O HD49801FB HD49801FB State Data A14 (1 to 16): H synchronization pulse timing This data specifies both the data acquisition timing conforming to that required by the CCD sensor as well as the horizontal synchronization pulse generation. Address H Data Address D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 Memory R/W start 1 1 0 1 1 0 0 0 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Memory R/W stop 2 1 0 1 1 1 0 0 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 H synchronization pulse 1 3 1 0 1 1 0 1 0 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 H synchronization pulse 2 4 1 0 1 1 1 1 0 0 5 1 0 1 1 0 0 1 0 6 1 0 1 1 1 0 1 0 7 1 0 1 1 0 1 1 0 8 1 0 1 1 1 1 1 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 H synchronization pulse 3 9 1 0 1 1 0 0 0 1 D1 D2 D3 D4 D5 D6 D7 D8 H synchronization pulse 4 10 1 0 1 1 1 0 0 1 D1 D2 D3 D4 D5 D6 D7 D8 H synchronization pulse 5 11 1 0 1 1 0 1 0 1 D1 D2 D3 D4 D5 D6 D7 D8 H synchronization pulse 6 12 1 0 1 1 1 1 0 1 D1 D2 D3 D4 D5 D6 D7 D8 H synchronization pulse 7 13 1 0 1 1 0 0 1 1 D1 D2 D3 D4 D5 D6 D7 D8 H synchronization pulse 8 14 0 0 1 1 1 0 1 1 D1 D2 D3 D4 D5 D6 D7 D8 H synchronization pulse 9 15 1 0 1 1 0 1 1 1 16 1 0 1 1 1 1 1 1 D1 D2 D3 D4 D5 D6 D7 D8 27 HD49801FB HD49801FB State Data A16 (1 to 2): Mode setting This data determines the handling of the TV format, whether the digital interface is used, and the data input format. Address H L GE DCE PLLON NE DCKC PAL 1 1 1 1 0 HCKC 1 SECAM D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 Test mode 2 • 1 1 1 1 1 All 0 TV format • SECAM PAL 0 0 NTSC 0 1 PAL 1 0 SECAM • DCKC: AD1 to AD9 latch phase 1: Positive phase (rising edge) 0: Reverse phase (falling edge) • HCKC: REF and OBP latch phase 1: Positive phase (rising edge) 0: Reverse phase (falling edge) H.REF Sensor lock Detected on the positive (or reverse) phase of the sensor lock signal. NE 1: Does not encode 0: Does encode Note: When NE is set to 1, no encoding is performed, and the color difference signal is output from the CO pin without modulation. The HD49801FB should normally be used with NE = 0. • DCE: Digital interface control 1: On 0: Off • PLLON Set to 1 when locking externally in NTSC mode. • GE: Grey code enable 1: Grey code 0: Binary code • 28 A2 to A16 are for use in test mode, and D6 to D28 should be set to all zeros in advance. HD49801FB HD49801FB State Data Transfer Timing Specifications Image Quality Control Protocol Timing • Image quality control data (state data) transfer protocol t WLDF SLDI t WLDL t WCKH STCKI t DS t WCKL SDI Dn Dn – 1 Dn – 2 D1 t DH • Min t WLDF 280 ns t WLDL 280 ns t WCKH 140 ns t WCKL 140 ns t DS 140 ns t DH 140 ns Iris, W/B data transfer protocol tS VDO t WLD DETLDI t WS t WCKH DETCKI t WCKL DETSO Dn – 2 D1 Iris D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 (average MSB value) D6 D5 D4 D3 Iris (peak) Dn D11 D10 D9 D8 D7 D6 D5 D4 MSB Dn – 1 D2 D1 LSB D3 D2 D1 LSB White: D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Balance MSB LSB MSB Mg-G (two’s complement) IWNI = high: Iris selection, State data: Average/peak selection IWNI = low: White balance selection LSB R-B (two’s complement) Min t WLD 80 fs –1 t WS 2 fs –1 t WCKH 140 ns t WCKL 140 ns tS 10 µs 29 HD49801FB • HD49801FB A/D input data (line delay memory R/W) transfer protocol HREFI Stop address (state data A14 to A2) Start address (state data A14 to A1) ADI1 to ADI9 D2 D1 D768 SCKI State data A16 DCKC: 1: Positive phase (ADI1 to ADI9 latched on the rising edge of SCKI) 0: Reverse phase (ADI1 to ADI9 latched on the falling edge of SCKI) State data A16 HCKC: 1: Positive phase (HREFI falling edge detected on the rising edge of SCKI) 0: Reverse phase (HREFI falling edge detected on the falling edge of SCKI) • Line delay memory R/W setting example Memory start address Memory stop address SCKI HREFI HREFI falling edge detection Memory stop counter clear ADI1 to ADI9 (HGI = H) an bn an + 1 bn + 1 an+m bn+m (For example, Wrn Gbn) ADI1 to ADI9 (HGI = L) cn dn cn + 1 dn + 1 cn+m dn+m (For example, Grn Wbn) Valid data (max: 768) A14 to A1 (memory start address) A14 to A2 (memory stop address) A16 to A1 (mode): HCKC = 1, DCKC = 1 The relationship between the CCD sensor complementary color signals (Wrn, Gbn, Grn, and Wrn) and state data A7 (a, b, c, d) is determined by the relationship between the HGI input and the start address. HGI is a line determination input, and when high, the two complementary color signals correspond to (a, b), and when low, they correspond to (c, d). 30 HD49801FB • HD49801FB Definition of H.REF H.REF is the standard for determining: — Memory R/W start/stop timing — BF, CBLK, CSYNC pulse timing • Conditions required of H.REF — H.REF is a pulse generated from the sensor clock (fs), and must be phase stable with respect to fs. — It must be a continuous pulse with no missing pulse periods during the BLK or other period. — Synchronization is horizontal scan synchronization. — tWH = Min 2 fs–1 — Timing corresponding to the effective pixel region for the falling edge of HREFI. Min tF 30 fs–1 tB 0 However, there are no special requirements when the following relationship is met: fs = 4n · fH (where n is an integer). — Setting example for H synchronization pulses (for an NTSC 270,000 pixel CCD) Name Symbol D10 D1 Notes H synchronization pulse 1 H1 10 0001 1011 539 H synchronization pulse 2 H2 00 1110 1100 236 H synchronization pulse 3 H3 0001 0110 22 H synchronization pulse 4 H4 0010 1110 46 H synchronization pulse 5 H5 0100 0011 67 H synchronization pulse 6 H6 0101 1010 90 H synchronization pulse 7 H7 0101 1111 95 H synchronization pulse 8 H8 0111 1000 120 H synchronization pulse 9 H9 1000 1011 138 • Values with respect to the falling edge of HREFI. Values with respect to H synchronization pulses 1 and 2. When a 410,000 pixel CCD is used, the following timings, which are related to the sensor clock and the sensor specifications, change. — Memory R/W start/stop addresses — BF, CBLK, CSYNC pulse timings — Iris state data A13, H count 1 to 6 31 HD49801FB • HD49801FB Notes on the Y/C digital interface — Y is the post-gamma compensation output, and the color signal is the color difference signal output. — The digital interface clock is proportional to the sensor clock frequency. It can handle 270,000 or 410,000 pixel sensors, and either the NTSC or PAL format. — The upper 4 bits are added to the lower 4 bits, which are delayed by 1 clock cycle, and output. Phase signal NRYBYO f’s Clock DICK CPO1 to CPO4 (R-Y)n (R-Y)n (B-Y)n (B-Y)n (R-Y)n (R-Y)n (B-Y)n (B-Y)n (R-Y)n (R-Y)n (B-Y)n (B-Y)n H L H L +1H +1L +1H +1L +2H +2L +2H +2L CPI1 to CPI4 (R-Y)n' (R-Y)n' (B-Y)n' (B-Y)n' (R-Y)n' (R-Y)n' (B-Y)n' (B-Y)n' H L H L +1H +1L +1H +1L YPO1 to YPO8 Ym Ym + 1 Ym + 2 Ym + 3 Ym + 4 Ym + 5 Ym + 6 YPI1 to YPI8 Ym' Ym + 1' Ym + 2' Ym + 3' Ym + 4' Ym + 5' Ym + 6' fs: Sensor clock frequency L H CPO1 to CPO4 D1 to D4 D5 to D8 CPI1 to CPI4 (D1: LSB) (D8: MSB) (two’s complement) 33 HD49801FB • HD49801FB Notes on the Y/C digital interface — Y is the post-gamma compensation output, and the color signal is the color difference signal output. — The digital interface clock is proportional to the sensor clock frequency. It can handle 270,000 or 410,000 pixel sensors, and either the NTSC or PAL format. — The upper 4 bits are added to the lower 4 bits, which are delayed by 1 clock cycle, and output. Phase signal NRYBYO f’s Clock DICK CPO1 to CPO4 (R-Y)n (R-Y)n (B-Y)n (B-Y)n (R-Y)n (R-Y)n (B-Y)n (B-Y)n (R-Y)n (R-Y)n (B-Y)n (B-Y)n H L H L +1H +1L +1H +1L +2H +2L +2H +2L CPI1 to CPI4 (R-Y)n' (R-Y)n' (B-Y)n' (B-Y)n' (R-Y)n' (R-Y)n' (B-Y)n' (B-Y)n' H L H L +1H +1L +1H +1L YPO1 to YPO8 Ym Ym + 1 Ym + 2 Ym + 3 Ym + 4 Ym + 5 Ym + 6 YPI1 to YPI8 Ym' Ym + 1' Ym + 2' Ym + 3' Ym + 4' Ym + 5' Ym + 6' fs: Sensor clock frequency L H CPO1 to CPO4 D1 to D4 D5 to D8 CPI1 to CPI4 (D1: LSB) (D8: MSB) (two’s complement) 33 HD49801FB HD49801FB SSG Internal Block Diagram The PLL format corresponding to the TG or TV formats used can be selected in the HD49801FB. • NTSC — The H oscillator is unused (state data A16 PLLON = 0) — When the PLL is applied to the sensor side TG: FFSCO 11 SCO 15 fsc (3.579545 MHz) 4 fsc osc 14.31818 MHz H/V counter 14 3 63 65 FVO 1/4 13 VDO TGSYNCO CHDO V.Reset VRI CBLKO HREFI SCKI fs fs system TG BFO CSYNCO IDO V.Reset fs HD TG PLL VCO Phase comp. 34 7 6 96 97 4 8 5 9 HD49801FB • HD49801FB NTSC — The H oscillator is unused (state data A16 PLLON = 0) — When the PLL is applied to the DSP side 4 fsc. FFSCO 11 SCO 15 fsc (3.579545 MHz) 4 fsc osc 14.31818 MHz H/V counter 14 3 63 65 FVO 1/4 13 VDO TGSYNCO CHDO V.Reset VRI CBLKO HREFI SCKI fs fs system TG BFO CSYNCO IDO fs HD V.Reset 7 6 96 97 4 8 5 9 TG Phase comp. 35 HD49801FB • HD49801FB NTSC — The H oscillator is used (state data A16 PLLON = 1) — See the description of NTSC on pages 34 and 35 for sensor side TG. 11 FFSCO 15 SCO fsc (3.579545 MHz) Phase comp. 1/4 13 1/161 PLLPO 4 fsc osc 14.31818 MHz PLLNO 14 99 1/2 63 65 VRI TGSYNCO CBLKO HREFI SCKI VDO CHDO V.Reset 100 VDD H/V counter 260 fH osc 3 fs fs system TG BFO CSYNCO IDO 36 2 1/184 FVO 4.090908 MHz 1 7 6 96 97 4 8 5 9 LPF HD49801FB • HD49801FB PAL/SECAM — The H oscillator is used (state data A16 PLLON = 1) — See the description of NTSC on pages 34 and 35 for sensor side TG. 11 FFSCO 15 SCP fsc (4.43361875 MHz) Phase comp. 1/4 13 17.734475 MHz 1/161 PLLPO 4 fsc osc PLLNO 14 99 1/2 63 65 VRI TGSYNCO CBLKO HREFI SCKI VDO CHDO V.Reset 100 VDD H/V counter 282 fH osc 3 LPF 2 1/16 FVO 4.40625 MHz 1 fs fs system TG BFO CSYNCO IDO 7 6 96 97 4 8 5 9 37 38 516 518 520 522 524 0 (3) 1 516 518 520 522 524 0 2 (4) 2 2 (3) 1 4 4 6 6 8 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 Note: * The sensor clock (fs) system is set by state data A14. CSYNCO* BFO* CBLKO* HREFI TGSYNCO CHDO VDO FVO 2f H CSYNCO* BFO* CBLKO* HREFI TGSYNCO CHDO VDO FVO 2f H (2) 4 HD49801FB HD49801FB NTSC Timing Chart This figure shows the timing chart conforming to the NTSC TV format. TGSYNCO SER EQ H 2f H CHDO 5 5 5 5 10 4.89 µs 10.269 µs 126 128 0 2 4 6 8 10 130f H 15 15 20 0.489 µs 30 40 50 1H = 63.5558 µs 60 60 70 70 70 70 75 80 80 90 100 120 125 128 0 2 4 6 HD49801FB HD49801FB 39 40 (1 616 618 620 622 624 0 1 616 618 620 622 624 0 (4 1) 2) 2 2 2 1 4 4 6 6 8 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 Note: * The sensor clock (fs) system is set by state data A14. IDO CSYNCO* BFO* CBLKO* HREFI TGSYNCO CHDO VDO FVO 2f H IDO CSYNCO* BFO* CBLKO* HREFI TGSYNCO CHDO VDO FVO 2f H 4 HD49801FB HD49801FB PAL/SECAM Timing Chart This figure shows the timing chart conforming to the PAL TV format. (3 616 618 620 622 624 0 3 616 618 620 622 624 0 (2 3) 4) 2 4 2 3 4 4 6 6 8 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 Note: * The sensor clock (fs) system is set by state data A14. IDO CSYNCO* BFO* CBLKO* HREFI TGSYNCO CHDO VDO FVO 2f H IDO CSYNCO* BFO* CBLKO* HREFI TGSYNCO CHDO VDO FVO 2f H 2 HD49801FB HD49801FB 41 42 TGSYNCO SER EQ H 2f H CHDO 0 6 6 6 6 11 4.539 µs 10.439 µs 140 0 2 4 6 8 10 141f H 16 16 20 23 0.4539 µs 30 40 50 65 60 81 1H = 64 µs 76 76 70 76 80 86 90 100 110 120 130 136 140 0 2 4 HD49801FB HD49801FB HD49801FB • HD49801FB Odd/even determination signal This is determined by latching CHD on the falling edge of FV. FV FV CHD CHD (odd) • (even) IDO for PAL/SECAM The change point agrees with the falling edge of C.SYNC. IDO In PAL mode: ID = high: Modulates at R-Y + polarity ID = low: Modulates at R-Y – polarity In SECAM mode: ID = high: B-Y output ID = low: R-Y output The (R-Y) polarity inversion in PAL mode is performed in the encoder that follows the digital interface. 43