LR38269
Digital Signal Processor for
Color CCD Cameras
LR38269
DESCRIPTION
The LR38269 is a CMOS digital signal processor
for color CCD camera system of 270 k/320 k-pixel
CCD with complementary color filters. The camera
system consists of CDS/AGC/ADC IC (IR3Y38M),
DSP IC (LR38269), and V driver IC (LR36685) with
CCD.
FEATURES
• Designed for 270 k/320 k color CCDs with Mg, G,
Cy, and Ye complementary color filters
• Switchable between NTSC and PAL modes
• External control interface input/output
• Variable GAMMA and KNEE response
(Select one out of 4 kinds of GAMMA & KNEE
response)
• 10-bit digital input
• Analog NTSC/PAL composite output by built-in 9bit 1 ch DA converter
• Built-in mirror image function
• Built-in timing generator to drive CCD
• Built-in 2 k-bit EEPROM controller to set the
camera adjustment data
• Built-in auto exposure control
• Built-in auto white balance control
• Built-in auto carrier balance control
• Single + 3.3 V power supply
• Package :
80-pin LQFP (LQFP080-P-1212) 0.5 mm pin-pitch
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
LR38269
PIN CONNECTIONS
TOP VIEW
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
42
20
41
40
43
19
39
44
18
38
45
17
37
46
16
36
47
15
35
48
14
34
49
13
33
50
12
32
51
11
31
52
10
30
53
9
29
54
8
28
55
7
27
56
6
26
57
5
25
58
4
24
3
23
59
22
60
2
21
1
OBCP
ADCLP
BLKX
EEPDA
GND
VDD
EEPCK
EEPFL
EEPSL
WB1
WB2
MIR
BLC
GNDDA
VDDDA
V B
IREF
VREF
GNDDA
VIDEO
ACL
CKI
CKO
VDD
GND
ADCK
SCK
SDATA
ADI9
ADI8
ADI7
ADI6
ADI5
ADI4
VDD
GND
ADI3
ADI2
ADI1
ADI0
79
80
FCDS
FS
RS
GND
VDD
FH2
FH1
FR
GND
VDD
OFDX
VH3X
VH1X
GND
VDD
V4X
V3X
V2X
V1X
VD
80-PIN LQFP
(LQFP080-P-1212)
2
HD
Y7
Y6
Y5
Y4
VDD
GND
Y3
Y2
Y1
Y0
EXCKI
DCK2
DCK1
VDD
GND
EEMD3
EEMD2
EEMD1
EEMDS
LR38269
BLOCK DIAGRAM
ADI9-ADI0
OB
CLAMPING
4 LINES
DELAY
LUMINANCE
SIGNAL
PROCESS
VIDEO
9-BIT DA
Y7-Y0
BLKX, CSYNC
HD, VD, ADCLP
OBCP
SSG
DCK1, DCK2
COLOR
SIGNAL
PROCESS
EXCKI
CKI
CKO
FR, FH1, FH2
V1X-V4X
VH1X, VH3X
TG
AUTOMATIC
CONTROL
EEPROM
CONTROL
EEPSL, EEPFL
EEPCK, EEPDA
EEMD2, EEMD3
EEMDS, EEMD1
WB1, WB2, MIR, BLC
FCDS, FS, RS
ADCK
3
LR38269
PIN DESCRIPTION
PIN NO. SYMBOL
1 ACL
2
3
I/O
IC
CKI
CKO
OSCI
OSCO
4
VDD
5
GND
–
–
6
7
ADCK
SCK
OBF6M
OBF4M
8
SDATA
OBF4M
9
ADI9
10
ADI8
11
ADI7
12
POLARITY
DESCRIPTION
Initializing input.
Input for reference clock oscillation. Connect to CKO (pin 3) with R.
Output for reference clock oscillation. The output is the inverse of CKI (pin 2).
Supply of +3.3 V power.
A grounding pin.
Clock output of AD converter, connected to pin 13 of IR3Y38M.
Clock output of serial data, connected to pin 16 of IR3Y38M.
Serial data output, connected to pin 19 of IR3Y38M.
IC
IC
Digital signal input, fed from pin 12 of IR3Y38M (MSB).
Digital signal input, fed from pin 11 of IR3Y38M.
ADI6
IC
IC
Digital signal input, fed from pin 10 of IR3Y38M.
Digital signal input, fed from pin 9 of IR3Y38M.
13
ADI5
IC
Digital signal input, fed from pin 8 of IR3Y38M.
14
ADI4
15
VDD
IC
–
Digital signal input, fed from pin 5 of IR3Y38M.
Supply of +3.3 V power.
16
17
GND
ADI3
–
A grounding pin.
IC
Digital signal input, fed from pin 4 of IR3Y38M.
18
ADI2
IC
Digital signal input, fed from pin 3 of IR3Y38M.
19
ADI1
20
ADI0
IC
IC
Digital signal input, fed from pin 2 of IR3Y38M.
Digital signal input, fed from pin 1 of IR3Y38M (LSB).
21
OBCP
OBF4M
22
ADCLP
OBF4M
Optical clamp pulse output, connected to pin 32 of IR3Y38M.
Clamp pulse output, connected to pin 45 of IR3Y38M.
23
BLKX
OBF4M
Blanking pulse output, connected to pin 35 of IR3Y38M.
24
EEPDA
IO4MU
25
GND
–
Data input from EEPROM output pin.
Supply of +3.3 V power.
26
VDD
–
27
EEPCK
IO4MU
28
EEPFL
IC
29
EEPSL
IC
30
WB1
31
WB2
IO4M
IO4M
A grounding pin.
Clock output to EEPROM clock input pin.
This pin keeps high-impedance under high level of pin 29.
Control pin of EEPROM. Connect to the pull-up resistor.
Control pin of EEPROM. A pull-down resistor should be connected between pin
29 and GND. High level of pin 29 can make data-setting from outside available.
White balance mode setting by both WB1 and WB2.
Pin 30
0
Pin 31
0
White balance mode
AUTO
0
1
PRESET WB1
1
1
0
1
PRESET WB2
PRESET WB3
In digital output mode, pin 30 is assigned to bit 0 (LSB) of U/V signal and pin 31
is assigned to bit 1.
4
LR38269
PIN NO. SYMBOL
I/O
POLARITY
DESCRIPTION
Video output mode setting.
32
MIR
IO4M
L : Normal
H : Mirror
In digital output mode, this pin is assigned to bit 2 of U/V signal.
Backlight compensation selection.
33
BLC
IO4M
L : OFF
H : ON
In digital output mode, this pin is assigned to bit 3 of U/V signal.
34
35
GNDDA
VDDDA
36
VB
DAO
37
IREF
DAO
Bias current output of built-in DA converter, connected to GND through a resistor.
DAI
–
Bias voltage input of built-in DA converter, connected to +1.0 V power supply.
A grounding pin of built-in DA converter.
–
A grounding pin of built-in DA converter.
–
Supply of +3.3 V power of built-in DA converter.
Bias voltage output of built-in DA converter, connected to GND through a
capacitor.
38
VREF
39
GNDDA
40
VIDEO
DAO
41
42
EEMDS
EEMD1
IO4MU
IO4MU
Electronic exposure mode setting by EEMDS, EEMD1, EEMD2 and EEMD3.
See "Electronic Shutter Speed Setting" in AUTOMATIC CAMERA FUNCTION
43
EEMD2
44
EEMD3
IO4MU
IO4MU
CONTROL.
In digital output mode, 41 to 44 pins are assigned to bits 7 to 4 of U/V signals.
Analog video signal output.
45
GND
–
A grounding pin
46
VDD
–
47
DCK1
Supply of +3.3 V power.
Clock output for digital signal output.
OBF4M
Output mode setting switches to CSYNC output.
ID pulse output for U/V output signal. In digital output, this pin outputs KEIPULSE.
48
DCK2
OBF4M
NOTE : KEI-PULSE
At power-on, it keeps low. Both 1/60 s (PAL 1/50 s) as shutter speed and AGC gain
more than data of address 78h sets it high.
49
EXCKI
50
Y0
51
Y1
52
Y2
53
Y3
IC
Bit 3 of address 03h sets the function of this pin.
1 : Clock input of 13.5 MHz for digital output
0 : VRI input for analog output
OBF4M
OBF4M
Bit 0 (LSB) of digital luminance signal output.
Bit 1 of digital luminance signal output.
OBF4M
OBF4M
Bit 2 of digital luminance signal output.
Bit 3 of digital luminance signal output.
54
GND
–
55
VDD
56
Y4
–
OBF4M
A grounding pin.
Supply of +3.3 V power.
Bit 4 of digital luminance signal output.
57
Y5
58
Y6
OBF4M
OBF4M
Bit 5 of digital luminance signal output.
Bit 6 of digital luminance signal output.
5
LR38269
PIN NO. SYMBOL
I/O
POLARITY
DESCRIPTION
59 Y7
OBF4M
Bit 7 (MSB) of digital luminance signal output
Horizontal driving pulse output. Either CCD driving timing or BELL-PULSE is
selected by output mode setting.
60
HD
OBF4M
NOTE : BELL-PULSE
Some period with high level every field.
Vertical driving pulse output.
Either VD or CSYNC with either driving timing or video output timing is selected
61
VD
OBF4M
62
V1X
63
V2X
OBF4M
OBF4M
Vertical driving pulse output, connected to pin 20 of LR36685.
Vertical driving pulse output, connected to pin 21 of LR36685.
64
65
V3X
V4X
OBF4M
OBF4M
Vertical driving pulse output, connected to pin 18 of LR36685.
Vertical driving pulse output, connected to pin 14 of LR36685.
by output mode setting.
66
VDD
–
67
68
GND
VH1X
–
69
VH3X
70
OFDX
71
VDD
–
72
73
GND
FR
–
OBF12M
Reset pulse output, connected to CCD through a capacitor.
74
FH1
75
FH2
OBF12M
OBF12M
Horizontal driving pulse output, connected to CCD.
Horizontal driving pulse output, connected to CCD.
76
VDD
–
77
78
GND
RS
–
OBF6M
79
FS
OBF6M
80
FCDS
OBF6M
IC
OBF4M
OBF6M
OBF12M
IO4M
Supply of +3.3 V power.
A grounding pin.
OBF4M
Vertical driving pulse output, connected to pin 19 of LR36685.
OBF4M
OBF6M
Vertical driving pulse output, connected to pin 15 of LR36685.
OFD driving pulse output, connected to pin 22 of LR36685.
Supply of +3.3 V power.
A grounding pin.
Supply of +3.3 V power.
A grounding pin.
Sample-hold pulse output, connected to pin 31 of IR3Y38M.
Sample-hold pulse output, connected to pin 30 of IR3Y38M.
Sample-hold pulse output, connected to both pin 28 and pin 29 of IR3Y38M.
: Input pin
: Output pin
: Output pin
: Output pin
: Input/output pin
IO4MU
OSCI
OSCO
DAI
DAO
6
: Input/output pin with pull-up resistor
: Input pin for oscillation
: Output pin for oscillation
: Input pin for DA converter
: Output pin for DA converter
LR38269
INTERNAL COEFFICIENT TABLE
ADDRESS
00h
01h
NAME
BIT
CONTENTS
Not used
7
MODE 1
6
TV mode
Input signal delay
0 : NTSC
0 : No delay
1 : PAL
1 : 1 clock cycle delay
5
4
Clock polarity to latch input signal
YL killer
0 : Normal
0 : Normal
1 : Inverted
1 : Killed
3
0 : Mode input
1 : U/V output
1
Pin mode selection (NOTE 1)
VD output timing selection (NOTE 1)
HD output timing selection
0 : TG
1 : Video output
0
DCK1 output selection (NOTE 1)
2
02h
MODE 2
03h
MODE 3
7-6
Luminance gamma selection
5-4
3
Color gamma selection
Vertical aperture enhancement
0 : ON
1 : OFF
2
Horizontal aperture enhancement
0 : ON
1 : OFF
1
0
Color killer
Flicker reduction
0 : ON
0 : ON
1 : OFF
1 : OFF
7
6
Polarity selection of SP1 and SP2
Polarity inverter of HG
5
Video format selection
0 : Interlace
1 : Non-interlace
4
3
UV dot-sequence selection (output stage)
UV dot-sequence selection
2
1
Carrier balance tuning
AGC
0 : ON
0 : Auto
1 : OFF
1 : Fixed (gain at
address 1Bh)
0
Digital output clock
0 : 9.6 MHz
04h
REF_IRIS1
7-0
Exposure reference level (target of exposure control)
05h
06h
CTLD_01
CTLD_02
7-0
7-0
Higher level of exposure reference level
Lower level of exposure reference level
07h
REF_IRIS2
Exposure reference level with backlight compensation
08h
UW_E1
7-0
7-0
Exposure control weighting factor 1
09h
UW_E2
7-0
Exposure control weighting factor 2
0Ah
0Bh
UW_E3
UW_E4
7-0
7-0
Exposure control weighting factor 3
Exposure control weighting factor 4
0Ch
UW_E5
7-0
Exposure control weighting factor 5
0Dh
UW_E6
7-0
Exposure control weighting factor 6
0Eh
UW_E7
7-0
Exposure control weighting factor 7
0Fh
10h
UW_E8
CW_E
7-0
6-0
Exposure control weighting factor 8
Weighting factor of exposure window area
11h
12h
CWP_E
CWA_E
6-0
6-0
Top-left point of exposure window area
Bottom-right point of exposure window area
7
1 : Clock of EXCKI pin
LR38269
ADDRESS NAME
13h
EE_DIV_STP
LPFE_F
LPFE_N
BIT
6-4
3-2
CONTENTS
Electronic shutter speed pitch
000 : Slower
Exposure response speed selection with flicker reduction
1-0
00 : Slower
01 : Normal
Exposure response speed selection
00 : Slower
01 : Normal
10 or 11 : Quicker
10 or 11 : Quicker
14h
P_HEE_IRIS
7-0
Maximum luminance level factor to control exposure
15h
P_LEE_IRIS
INT_PEAK
7-0
6
Minimum luminance level factor to control exposure
Integrated pixels of peak signal
0 : 8 pixels
16h
5
IRIS_DLY1
Condition of exposure control under locking-in number of images to control exposure.
0 : 1 image
1 : Integrated 3 images
00 : Every image
Valid image to control exposure
3
01 : Every 2 images 10 : Every 4 images 11 : Every 8 images
Condition of exposure control under free-running
1
0
Number of images
0 : 1 image
Valid image to control exposure
01 : Every 2 images 10 : Every 4 images
00 : Every image
11 : Every 8 images
AGC control data
Minimum pitch of AGC variable gain
000 : Slower
AG_DIV_STP
7-5
AG_GAIN
4-0
19h
I_AGC_D8
7-0
Not used
AGC gain at power-on
1Ah
1Bh
REF_AGC_D8
S_38M_GA
7-0
7-0
AGC reference gain (more than data of 19h)
Fixed AGC gain
1Ch
S_38M_MAX
2-0
AGC maximum gain
S_38M_OFS
6
5-0
Offset control
Offset data
1Eh
1Fh
CSEPR
CSEPB
7-0
7-0
Coefficient to extract red color signal
Coefficient to extract blue color signal
20h
21h
CB_R
CB_B
7-0
7-0
Red signal carrier balance
Blue signal carrier balance
22h
K_T_R
7-0
Basic red WB gain
23h
24h
K_T_B
7-0
MAX_WBR
7-0
Basic blue WB gain
Red WB gain at maximum color temperature
25h
26h
MIN_WBR
MAX_WBB
7-0
7-0
Red WB gain at minimum color temperature
Blue WB gain at minimum color temperature
27h
MIN_WBB
7-0
Blue WB gain red at maximum color temperature
28h
29h
WBR1
WBB1
7-0
7-0
Red WB data (preset 1)
Blue WB data (preset 1)
2Ah
2Bh
WBR2
WBB2
7-0
7-0
Red WB data (preset 2)
Blue WB data (preset 2)
2Ch
WBR3
7-0
Red WB data (preset 3)
17h
18h
1Dh
1 : 4 pixels
4
2
IRIS_DLY2
111 : Quicker
1 : Integrated 3 images
111 : Quicker
DATA should be between 01h (finest pitch) and 1Fh.
0 : Auto
8
1 : Fixed
LR38269
ADDRESS NAME
2Dh
WBB3
2Eh
2Fh
BIT
7-0
CONTENTS
Blue WB data (preset 3)
K_GA_R
7-0
Correction coefficient of R – Y gain
K_GA_B
REF_GA_R
7-0
5-0
Correction coefficient of B – Y gain
Basic gain of R – Y signal
32h
REF_GA_B
GA_R1
5-0
5-0
Basic gain of B – Y signal
R – Y gain data (preset 1)
33h
34h
GA_B1
GA_R2
5-0
5-0
B – Y gain data (preset 1)
R – Y gain data (preset 2)
35h
GA_B2
5-0
B – Y gain data (preset 2)
36h
37h
GA_R3
GA_B3
5-0
5-0
R – Y gain data (preset 3)
B – Y gain data (preset 3)
38h
MAX_IQAREA
7
6-5
AWB IQ area selection
0 : Set data
Response speed selection with flicker reduction
30h
31h
LPFIQ_F
39h
3Ah
3Bh
00 : Slower
01 : Normal
10 or 11 : Quicker
LPFIQ_N
FINE
4-3
2
Response speed
Fine-tuning mode of auto white balance
AWB_WAIT_C
AWB_WAIT_C
1-0
7-0
AWB time constant after lock-in (upper 2 bits)
AWB time constant after lock-in (lower 8 bits)
CMP_CT
7-0
Valid data to control AWB (01h makes all AWB data valid.)
AWB_HCL
AWB_LCL
7-0
7-0
Highest luminance level to be available for AWB control
Lowest luminance level to be available for AWB control
REF_WBPK
K_CL
7-0
7-0
Offset luminance level to control data of 3Bh and 3Ch
Maximum luminance level factor to control data of 3Bh and 3Ch
K_WBCL
7-0
Weighting factor for data of 3Dh and 3Eh
41h
UW_IQ1
UW_IQ2
7-0
7-0
AWB control weighting factor 1
AWB control weighting factor 2
42h
43h
UW_IQ3
UW_IQ4
7-0
7-0
AWB control weighting factor 3
AWB control weighting factor 4
44h
INT_I_R – Y
CW_IQ
7
6-0
AWB control data
Weighting factor of AWB window area
7-4
Top-left point of AWB window area
3-0
Bottom-right point of AWB window area
7-0
Exposure level to erase the area to detect white color
3Ch
3Dh
3Eh
3Fh
40h
45h
46h
CWPA_IQ
CTLD_AW0
9
1 : Widest
0 : I/Q
1 : R – Y/B – Y
LR38269
ADDRESS NAME
AWB_IP_L
47h
BIT
7-0
First AWB detector area I-PLUS
CONTENTS
NOTE :
Data to set first area should be larger than
data to set second area.
48h
AWB_IM_L
7-0
First AWB detector area I-MINUS
49h
AWB_QP_L
7-0
First AWB detector area Q-PLUS
4Ah
AWB_QM_L
7-0
First AWB detector area Q-MINUS
4Bh
AWB_IP_S
7-0
Second AWB detector area I-PLUS
4Ch
AWB_IM_S
7-0
Second AWB detector area I-MINUS
4Dh
4Eh
AWB_QP_S
AWB_QM_S
7-0
7-0
Second AWB detector area Q-PLUS
Second AWB detector area Q-MINUS
4Fh
AWB_I_WH_L
6-0
First AWB white zone I-PLUS
50h
AWB_Q_WH_L
AWB_I_WH_S
6-0
6-0
First AWB white zone Q-PLUS
Second AWB white zone I-MINUS
AWB_Q_WH_S
K_MAT_R
6-0
7-0
Second AWB white zone Q-MINUS
R – Y gain factor for color matrix correction
51h
52h
53h
Second area should be closer to the cross
point of I-axis and Q-axis, compared to first
area.
54h
K_MAT_B
7-0
B – Y gain factor for color matrix correction
55h
56h
REF_MAT_R
REF_MAT_B
5-0
5-0
Basic R – Y data of color matrix correction
Basic B – Y data of color matrix correction
57h
58h
MAT1
MAT2
7-0
7-0
Color matrix data (preset 1) R – Y 4 bits, B – Y 4 bits
Color matrix data (preset 2) R – Y 4 bits, B – Y 4 bits
59h
5Ah
MAT3
7-0
Color matrix data (preset 3) R – Y 4 bits, B – Y 4 bits
5Bh
COL_S
COL_H
7-0
5-0
AGC gain to start suppressing color signal
Pitch of color signal suppressing by address 5Ah
5Ch
5Dh
CKI_HCL
CKI_LCL
7-0
7-0
Higher luminance level to start suppressing color signal
Lower luminance level to start suppressing color signal
7-4
Color signal suppression gain for higher luminance signal
3-0
7-4
Color signal suppression gain for lower luminance signal
Highlight luminance signal position to suppress color –2 to +2
3-0
7-0
Lowest luminance signal position to suppress color –2 to +2
7-0
7-4
Vertical aperture level to start suppressing color signal
Horizontal aperture gain to suppress color signal by address 60h
5Eh
5Fh
CKI_HLGA
CKI_HLTI
60h
CKI_HECL
61h
CKI_EVCL
62h
CKI_EGA
Horizontal aperture level to start suppressing color signal
3-0
Vertical aperture gain to suppress color signal by address 61h
63h
64h
APT_S
APT_H
7-0
5-0
AGC gain to start suppressing aperture signal
Gain to suppress aperture signal by address 63h
65h
66h
NSUP_R
NSUP_B
7-0
7-0
R – Y signal coring level
B – Y signal coring level
67h
CKI_IEL
7
CKI_ETI
6-4
3-1
Horizontal edge signal position to kill color signal –2 to +2
Vertical edge signal position to kill color signal –2 to +2
APT_HTIM
APT_HGA
7-6
5-1
Horizontal aperture signal position –1 to +1
Horizontal aperture gain
68h
Color-killer level
0 : Unity gain
10
1 : 1/4 gain
LR38269
ADDRESS NAME
69h
APT_HCL
6Ah
6Bh
BIT
6-0
CONTENTS
Horizontal aperture signal coring
APT_VGA
4-0
Vertical aperture gain
6Ch
APT_VCL
CBLK_LV
6-0
7
Vertical aperture signal coring
CBLK level selection
6Dh
SETUP
VARI_Y
6-1
4-0
Set up level
luminance signal position
SW_CTRL
7-0
The following setting is available under both EEPSL = H and digital output mode
WB1 (LSB), WB2, BACK, EEMDS, EEMD1 EEMD2, EEMD3, MIR (MSB)
6Eh
6Fh
70h
TG_SEL1
0 : 00h
7-5
ADCK phase setting (6 steps per 60˚)
4-2
FS phase setting (±2 ns x 3)
1 : 10h
7-5
FCDS phase setting (±2 ns x 3)
ENC_MUTE
4-2
7
FR phase setting (±2 ns x 3)
Encoder muting
0 : OFF
1 : ON
SYNC_SW
6
SYNC adder
0 : ON
1 : OFF
SEL_RB
OUT_GAIN
5
4-0
Serial digital data setting
Gain of video output amplifier
72h
73h
SYNC_LEV
BAS_R
7-0
7-0
SYNC level (80h = 40 IRE)
BURST level of R – Y
74h
75h
BAS_B
7-0
BURST level of B – Y
MUTE_OUT
7
6-0
Muting at power-on
Muting period (data multiplied by 1 field period)
TEST
VRI
2-0
2
Test data (EEPROM data must be 00h)
EXCKI pin function
TEST
1
Test data (EEPROM data must be 0)
TEST
KEI_AGC
0
8
Test data (EEPROM data must be 0)
AGC gain to set KEI-PULSE high
71h
76h
77h
78h
TG_SEL2
1 : VRI function
0 : Clock input
(NOTE 1)
ADDRESS
SIGNAL OUTPUT
Bit 3
01
Bit 2
Bit 0
DIGITAL
1
0
DCK1
VD for video out
HD
1
0
x
0
1
DCK1
DCK1
VD for CCD driving
CSYNC
HD
HD
1
0
0
0
CSYNC
CSYNC
VD for video out
VD for CCD driving
HD
HD
1
1
CSYNC
VD for video out
BELL
0
1
CSYNC
VD for CCD driving
BELL
ANALOG
0
DCK1 (Pin 47)
VD (Pin 61)
11
HD (Pin 60)
LR38269
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Power supply voltage
Input voltage
Output voltage
Storage temperature
SYMBOL
VDD
VI
RATING
–0.3 to +4.3
–0.3 to VDD + 0.3
UNIT
V
VO
–0.3 to VDD + 0.3
V
TSTG
–55 to +150
˚C
V
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Power supply voltage
SYMBOL
VDD
MIN.
3.0
TYP.
3.3
MAX.
3.6
UNIT
V
Operating temperature
Input clock frequency
TOPR
fCK
–20
+25
28.6
+70
˚C
MHz
ELECTRICAL CHARACTERISTICS
PARAMETER
Input "Low" voltage
Input "High" voltage
Input "Low" current
(VDD = 3.0 to 3.6 V, TOPR = –20 to +70 ˚C)
SYMBOL
VIL
VIH
CONDITIONS
|IIL1|
MIN.
TYP.
0.8 VDD
Output "Low" voltage
VOL1
VIN = 0 V
IOL = 4 mA
Output "High" voltage
VOH1
IOH = –4 mA
MAX. UNIT
V
0.2 VDD
V
µA
100
0.2 VDD
0.8 VDD
Output "Low" voltage
VOL2
IOL = 6 mA
Output "High" voltage
VOH2
IOH = –6 mA
0.8 VDD
Output "Low" voltage
Output "High" voltage
VOL3
VOH3
IOL = 12 mA
IOH = –12 mA
0.8 VDD
Output "Low" voltage
Output "High" voltage
VOL4
VOH4
IOL = 3 mA
Resolution
RES
IOH = –2 mA
V
EL
ED
RREF= 4.8 k$
Full scale current
|IFS|
ROUT = 75 $
2
3
V
V
4
0.2 VDD
V
V
5
0.2 VDD
V
V
6
±3.0
±1.0
LSB
LSB
0.8 VDD
VREF = 1.0 V
1
0.2 VDD
bit
9
Linearity error
Differential error
V
NOTE
7
mA
V
8
Reference voltage
VREF
13
1.0
Reference resistance
RREF
4.8
k$
9
Output load resistance
ROUT
75
$
7
NOTES :
1.
2.
3.
4.
5.
Applied
Applied
Applied
Applied
Applied
to
to
to
to
to
inputs (IC, IO4M, IO4MU).
input (IO4MU).
outputs (OBF4M, IO4M, IO4MU).
output (OBF6M).
output (OBF12M).
6.
7.
8.
9.
12
Applied
Applied
Applied
Applied
to
to
to
to
output (OSCO).
output (VIDEO).
input (VREF).
output (IREF).
LR38269
Data Interface
(1) Format of data transfers
• Format of transfers : Asynchronous (Based on
RS-232C standard)
• Bit rate : 9 600 bps
• Data length : 8 bits
• Parity check : 1 even parity bit
• Start bit : 1 bit
• Stop bit : 1 bit
• Signal voltage level (CMOS)
3.3 V
Start
Bit
RxD
D0
GND
D1
D2
D3
D4
D5
LSB
D6
Even
Parity
Bit
D7
Stop
Bit
MSB
Data Bit
• System configuration
SCK
LR38269
SDATA
RxD
Dedicated
Adjustment
Tool
by SHARP
PC with
Windows
TxD
SLDI
1.4 µs
11.6 µs
SCK
SDATA
SLDI
DSP Address
DSP Data
5.8 µs
13
LR38269
AUTOMATIC CAMERA FUNCTION
CONTROL
Automatic Electronic Exposure Control
exposure control data will be less than the data of
address 06h.
In the case of coming more than the data of
address 07h, exposure control starts again.
Electronic shutter speed is controlled so that the
exposure control data approach to the data of
address 04h.
Under BLC mode, the data of address 07h is
available instead of address 04h.
After the exposure control data is less than the data
of address 05h, an electronic shutter speed is hold.
And then AGC gain is controlled so that the
Electronic Shutter Speed Setting
By either hardware or coefficient data, electronic
shutter speed below is selectable.
ELECTRONIC SHUTTER SPEED
EEMDS
EEMD1
EEMD2
EEMD3
0
0
0
0
0
0
0
1
1/60 s
1/100 s
1/50 s
1/120 s
0
0
0
0
1
1
0
1
1/250 s
1/500 s
1/250 s
1/500 s
0
1
0
0
1/1 000 s
1/1 000 s
0
0
1
1
0
1
1
0
1/2 000 s
1/5 000 s
1/2 000 s
1/5 000 s
0
1
1
0
1
0
1
0
1/10 000 s
1/20 000 s
1/10 000 s
1/20 000 s
1
0
0
1
1/50 000 s
1/50 000 s
1
1
0
0
1
1
0
1
1/100 000 s
1/30 s
1/100 000 s
1/25 s
1
1
1
1
0
0
0
1
1/15 s
1/7.5 s
1/12.5 s
1/6.25 s
1
1
1
0
AUTO
1/60 to 1/100 000 s
AUTO
1/50 to 1/100 000 s
1
1
1
1
AUTO
AUTO
1/60 to 1/100 000 s
1/50 to 1/100 000 s
NTSC
PAL
VD pulse is also converted to the same frequency
as the output image rate.
Slower shutter speed less than 1/60 s (1/50 s of
PAL) can make images whose interval is every two
fields, every four fields, etc..
14
LR38269
Electronic exposure control data comes from below
equation using averaged luminance levels of 64
areas in one image, made by DSP.
e Top level : The highest luminance data in one
image by averaging either 4 pixels
or 8 pixels in horizontal.
Electronic exposure control data =
[{Weighted data 1 q x (64 – address 10h)
+ weighted data 2 w x address 10h} ÷ 64
x (256 – address 14h – address 15h)
+ top level e x address 14h
+ bottom level r x address 15h] ÷ 256
r Bottom level : The lowest luminance data in
one image by averaging either 4
pixels or 8 pixels in horizontal.
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y21
Y31
Y22
Y32
Y23
Y33
Y24
Y34
Y25
Y35
Y26
Y36
Y27
Y37
Y28
Y38
Y41
Y42
Y43
Y44
Y45
Y46
Y47
Y48
Y51
Y61
Y52
Y62
Y53
Y63
Y54
Y64
Y55
Y65
Y56
Y66
Y57
Y67
Y58
Y68
Y71
Y81
Y72
Y82
Y73
Y83
Y74
Y84
Y75
Y85
Y76
Y86
Y77
Y87
Y78
Y88
Auto White Balance Control
White balance control data less than the data of
address 51h and address 52h stops AWB.
White balance control data less than the data of
address 4Fh and address 50h makes AWB active
so that white balance control data is less than the
data of address 51h and address 52h.
In the case of larger than the data of address 4Fh
and address 50h, AWB will be active again.
White balance data comes from the following
equation using averaged I and Q data of 16 areas
in one image.
q Weighted data 1
This comes from the following equation weighting in
horizontal.
Weighting factors are the data from address 08h to
address 0Fh.
{(Y11 + Y12 π + Y18) ÷ 8 x address 08h
+ (Y21 + Y22 π + Y28) ÷ 8 x address 09h
:
+ (Y81 + Y82 π + Y88) ÷ 8 x address 0Fh} ÷ 256
= Weighted data 1
The sum from address 08h to address 0Fh shall be
256.
I11
I21
I12
I22
I13
I23
I14
I24
I31
I32
I33
I34
I41
I42
I43
I44
Q11
Q21
Q12
Q22
Q13
Q23
Q14
Q24
Q31
Q32
Q33
Q34
Q41
Q42
Q43
Q44
White balance data =
{Weighted data 3 q x (64 – address 44h)
+ weighted data 4 w x address 44h} ÷ 64
w Weighted data 2
Weighting area can be set by the data of address
11h and address 12h. (see "NOTES" in Gamma
Characteristic Option)
This comes from the following equation weighting in
selected areas.
(Y33 + Y34 π + Y66)/number of areas to be selected
= Weighted data 2
15
LR38269
q Weighted data 3
I (or Q) data comes from the following equation
using the weighting data from address 40h to
address 43h.
Auto Color Matrix Compensation
{(I11 + I12 π + I14) ÷ 4 x address 40h
+ (I21 + I22 π + I24) ÷ 4 x address 41h
:
+ (I41 + I42 π + I44) ÷ 4 x address 43h} ÷ 256
= Weighted data 3
Above data comes from below equation along the
variation of color temperature.
Color matrix compensation can be done by
R – Y = R – Y ± (Data 1 x B – Y)
B – Y = B – Y ± (Data 2 x R – Y)
Data 2 =
address 55h + {(working R white balance data –
address 25h + (address 26h – working B white
balance data)} ÷ 32 x address 53h ÷ 8
The sum from the data of address 40h to the data
of address 43h shall be 256.
Data 2 =
address 56h + {(working R white balance data –
address 25h) + (address 26h – working B white
balance data)} ÷ 32 x address 54h ÷ 8
w Weighted data 4
Weighting area can be selected by address 45h.
(see "NOTES" in Gamma Characteristic Option.)
Weighted data comes from averaged data in
selected area.
Auto Color Level Compensation
Color level can be auto-controlled by the following
equation along the variation of color temperature.
e White balance area setting
The sum of I and Q can be regulated by the
luminance level and the color level.
Setting target zone : address 47h to address 4Ah
White balance data less than the data of address
51h and address 52h changes the target zone of
auto white balance to the zone by the data from
address 4Bh to 4Eh.
B – Y level =
address 30h + {(working R white balance data –
address 25h) x address 22h + (address 26h –
working B white balance data) x address 23h} ÷ 32
x address 2Eh ÷ 8
R – Y level =
address 31h + {(working R white balance data –
address 25h) x address 22h + (address 26h –
working B white balance data) x address 23h} ÷ 32
x address 2Fh ÷ 8
Above regulation comes from the following equation
along the luminance level.
Setting available luminance level range :
Highest luminance level limiter =
address 3Bh + [{address 3Eh x H peak level +
(256 – address 3Eh) x exposure control data} ÷
256 – address 3Dh] x address 3Fh
Lowest luminance level limiter =
address 3Ch + [{address 3Eh x H peak level +
(256 – address 3Eh) x exposure control data} ÷
256 – address 3Dh] x address 3Fh
16
LR38269
Color Level Suppression Under Lower
Illuminance
Working AGC gain can control both R – Y level
and B – Y level by the following equation.
R – Y level =
address 31h x {16 – (working AGC gain – address
5Ah) x address 5Bh ÷ 16} ÷ 16
B – Y level =
address 30h x {16 – (working AGC gain – address
5Ah) x address 5Bh ÷ 16} ÷ 16
{16 – (working AGC gain – address 5Ah) x
address 5Bh ÷ 16} ≤ 16
When (working AGC gain – address 5Ah) ≤ 0, ( ) = 0.
Aperture Level Suppression Under
Illuminance
Working AGC gain can control both the horizontal
aperture level and the vertical aperture level by the
following equation.
Horizontal aperture level =
address 68h x {16 – (working AGC gain – address
63h) x address 64h ÷ 16} ÷ 16
Vertical aperture level =
address 6Ah x {16 – (working AGC gain – address
63h) x address 64h ÷ 16} ÷ 16
{16 – (working AGC gain – address 63h) x
address 64h ÷ 16} ≤ 16
When (working AGC gain – address 63h) ≤ 0, ( ) = 0.
17
LR38269
Gamma Characteristic Option
(1) Luminance Signal Gamma Option
Bit 7 and bit 6 of address 02h can select one out of
4 responses below.
256
224
192
OUTPUT
160
128
96
00
01
64
10
32
11
960
896
832
768
704
640
576
512
448
384
320
256
192
128
64
0
0
INPUT
(2) Color Signal Gamma Option
Bit 5 and bit 4 of address 02h can select one out of
4 responses below.
256
224
192
128
96
00
01
64
10
32
11
INPUT
18
960
896
832
768
704
640
576
512
448
384
320
256
192
128
64
0
0
OUTPUT
160
LR38269
NOTES :
• Weighting position of auto electronic exposure control (address 11h)
00h
08h
·
30h
38h
01h
09h
·
31h
39h
·
06h
·
0Eh
·
·
·
36h
·
3Eh
07h
0Fh
·
37h
3Fh
• Weighting area of auto electronic exposure control (address 12h)
00h
01h
08h
09h
·
·
30h
31h
38h
39h
·
·
·
·
·
06h
07h
0Eh
0Fh
·
·
36h
37h
3Eh
3Fh
• Weighting position of auto white balance control (address 45h)
00h
04h
08h
0Ch
01h
02h
05h
06h
09h
0Ah
0Dh
0Eh
03h
07h
0Bh
0Fh
• Weighting area of auto white balance control (address 45h)
00h
04h
08h
0Ch
01h
02h
05h
06h
09h
0Ah
0Dh
0Eh
03h
07h
0Bh
0Fh
19
PACKAGES FOR CCD AND CMOS DEVICES
PACKAGE
(Unit : mm)
80 LQFP (LQFP080-P-1212)
0.08
M
0.2±0.08
21
(1.0)
20
0.6375
1.70MAX.
12.0±0.2
(1.0)
1.40±0.2
14.0±0.3
Package
base plane
(1.0)
20
0.1±0.1
0.10
80
13.0±0.2
40
12.0±0.2
61
1
0.125±0.05
(1.0)
41
60
14.0±0.3
0.5TYP.