RENESAS HD49815TF

HD49815TF
Digital Camera Signal Processor
REJ03F0138-0100
(Previous: ADE-207-316)
Rev.1.00
Jun 15, 2005
Description
The HD49815TF is a CMOS IC that has been developed as a digital signal-processing IC for CCD-camera digitalsignal-processing systems.
Functions
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CCD-sensor drive-pulse generation (TG)
Digital AGC (automatic gain control)
Color signal separation circuit
RGB matrix
RGB gain
RGB and Y gamma
Color-difference matrix
Enhancer
RGB and Y setup
Digital I/F (4:2:2)
Zoom control
Mirror reversal
Synchronization signal generator for encoding (SSG)
AWB, AE, and AF detection
Two-channel 8-bit D/A converter
Features
• The HD49815TF provides camera-signal processing, TG, SSG, zoom, and D/A functions and other functions in a
single chip and supports high system-integration level.
• In conjunction with the HD49323AF-01 (CDS/AGC + 10-bit ADC) and the control microcomputer, the
HD49815TF forms a three-chip kit that can implement an optimal CCD-camera digital-signal-processing system.
• The HD49815TF provides the zoom function and controls the 1- to 256- times linear zoom. It also provides the
half-mirror function.
• Since the HD49815TF can be made compatible with the former product, HD49811TFA, through software, a shorter
development term is enabled.
• Since software controls AWB, AE, and AF, any protocol can be prepared according to the camera shooting
conditions.
• Programmable TG enables use of any CCD device.
Rev.1.00 Jun 15, 2005 page 1 of 21
HD49815TF
System Block Diagram
HD49815TF
Lens
CCD HD49323AF-01
CDS/AGC+
10-bit ADC
Input
line
memory
TG
SSG
Color
processing
Luminance
processing
Microprocessor
I/F
V.Driver
System
control
AE
(iris)
control
AWB
(white
balance)
control
8-bit single-chip microcomputer (H8 series)
Rev.1.00 Jun 15, 2005 page 2 of 21
Zoom
processing
Encode
DAC
C-signal output
Y-signal output
R-Y/B-Y
digital output
Y-signal
digital output
HD49815TF
AD(10)
AD(9)
AD(8)
AD(7)
AD(6)
AD(5)
AD(4)
AD(3)
AD(2)
AD(1)
ADCK
CPREF
DSP_MCK
VDD
VSS
SP1
SP2
OBP
VDD
H1
H2
VDD
RG
VDD
XV1
XV2
XV3
XV4
XSG1
XSG2
Pin Arrangement
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
90
DKF_LD
2
89
FP
T_CP(TEST)
3
88
NME
TY_K
4
87
CPI(1)
SDI
5
86
CPI(2)
SDCK
6
85
CPI(3)
SLD
7
84
CPI(4)
SDO
8
83
CPI(5)
EP(1)
9
82
CPI(6)
EP(2)
10
81
CPI(7)
BF
11
80
CPI(8)
HD_IN
12
79
CPO(1)
M_CK
13
78
CPO(2)
VDD
14
77
CPO(3)
VSS
15
76
CPO(4)
FV
16
75
VSS
HD
17
74
VDD
CBLK
18
73
CPO(5)
CSYNC
19
72
CPO(6)
SCBLK
20
71
CPO(7)
HSYNC
21
70
CPO(8)
ID
22
69
YPI(1)
IDP
23
68
YPI(2)
VDD
24
67
YPI(3)
VSS
25
66
YPI(4)
X1I
26
65
YPI(5)
X1O
27
64
YPI(6)
IDS
28
63
YPI(7)
MCK_S
29
62
YPI(8)
RESET
30
61
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
(Top view)
Rev.1.00 Jun 15, 2005 page 3 of 21
YPO(3)
YPO(4)
YPO(5)
YPO(6)
YPO(7)
YPO(8)
NRYBY
DICK
VSS
VDD
VSS
AVDD
VSS
Y_OUT
REXT
CBL
CBU
C_OUT
VSS
AVDD
VSS
AVDD
VSS
FSC
X2O
X2I
VR
PLL_P
TFP-120
YPO(2)
1
PLL_N
XSUB
ZOOM_HD
YPO(1)
HD49815TF
Pin Description
I/O
Format
ZC2R
ICS
IC
ICD
IC
ICS
ICS
ZC2R
Pin No.
1
2
3
4
5
6
7
8
9
Symbol
XSUB
DKF_LD
T_CP
TY_K
SDI
SDCK
SLD
SDO
EP (1)
Pin Name
CCD shutter pulse
Line input LD
Test
Title SW
State data input
State data clock
State data load pulse
AWB, AE, data output
AE window pulse 1
I/O
O
I
I
I
I
I
I
O
O
Description
CCD control pulse
Line input dedicated load
Test pin (GND input)
Title-killer SW (1 = On, 0 = Off)
State data-setting data input
State data-setting clock
State data-latch pulse
AWB, AE, and AF detection-data output
Iris detection-area-setting pulse:
SP-A7 [8] output changeover
ICZC2R
10
EP (2)
AE window pulse 2
O
ICZC2R
11
12
13
BF
HD_IN
M_CK
Burst flag
External CSYNC input
Microprocessor clock
O
I
O
Iris detection-area-setting pulse:
SP-A7 [8] output changeover
Burst flag output
External CSYNC input
OC2R
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
VDD
VSS
FV
HD
CBLK
CSYNC
SCBLK
HSYNC
ID
IDP
VDD
VSS
X1I
X1O
IDS
MCK_S
VCC2
GND
Field vertical output
HD output
Blanking pulse
SYNC output
SC blanking pulse
Horizontal SYNC
Identity
Identity pulse
VCC2
GND
X’tal 1 input
X’tal 1 output
Line ID reset input
MCK output SW
—
—
O
O
O
O
O
O
O
O
—
—
I
O
I
I
Microprocessor clock output
(1/2 or 1/4 dividing of X’tal 1)
3.3 V power supply
GND
Vertical synchronization pulse
Horizontal synchronization pulse
Blanking pulse
SYNC pulse
Subcarrier blanking pulse (SECAM)
Horizontal SYNC pulse (SECAM)
SECAM determination pulse
SECAM determination pulse
3.3 V power supply
GND
2fsc oscillator input
2fsc oscillator output
Line-determination-signal input
30
31
32
33
34
35
36
RESET
PLL_N
PLL_P
VR
X2I
X2O
FSC
Reset
PLL negative
PLL positive
Vertical reset
X’tal 2 input
X’tal 2 output
Sub carrier frequency
37
38
39
40
41
42
43
44
45
VSS
AVDD
VSS
AVDD
VSS
C_OUT
CBU
CBL
REXT
GND
Analog VCC2
GND
Analog VCC2
GND
C analog signal output
Current buffer upper
Current buffer lower
Reference resister EXT
Rev.1.00 Jun 15, 2005 page 4 of 21
ICZC2R
ICSD
VCCI
GNDI
ICZC2R
ICZC2R
ICZC2R
ICZC2R
ICZC2R
OC2R
OC2R
ICZC2R
VCCC
GNDC
IQ3
OQ3
ICD
IC
I
O
O
I
I
O
O
Pin 13 MCK dividing setting SW
(1 = 1/2, 0 = 1/4)
Reset: to restore the initial data settings
PLL signal output
PLL signal output
Vertical synchronization signal input
4fsc oscillator input
4fsc oscillator output
fsc output
ICS
ZC2
ZC2
ICSD
IQ2
OQ2
ICZC2R
—
—
—
—
—
O
I
I
I
GND
Analog system power supply: 3.3 V
GND
Analog system power supply: 3.3 V
GND
Chrominance-signal analog output
D/A upper current source
D/A lower current source
Reference voltage input
GNDA
VCCA
GNDA
VCCA
GNDA
OA
IA
IA
IA
HD49815TF
Pin Description (cont.)
Pin No.
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Symbol
Y_OUT
VSS
AVDD
VSS
VDD
VSS
DICK
NRYBY
YPO (8)
YPO (7)
YPO (6)
YPO (5)
YPO (4)
YPO (3)
YPO (2)
YPO (1)
YPI (8)
YPI (7)
YPI (6)
YPI (5)
YPI (4)
YPI (3)
YPI (2)
YPI (1)
CPO (8)
CPO (7)
CPO (6)
CPO (5)
VDD
VSS
CPO (4)
CPO (3)
CPO (2)
CPO (1)
CPI (8)
CPI (7)
CPI (6)
CPI (5)
CPI (4)
CPI (3)
Pin Name
Y analog signal output
GND
Analog VCC2
GND
VCC2
GND
Digital interface clock
R-Y, B-Y phase output
Y parallel output (8); MSB
Y parallel output (7)
Y parallel output (6)
Y parallel output (5)
Y parallel output (4)
Y parallel output (3)
Y parallel output (2)
Y parallel output (1) ; LSB
Y parallel input (8); MSB
Y parallel input (7)
Y parallel input (6)
Y parallel input (5)
Y parallel input (4)
Y parallel input (3)
Y parallel input (2)
Y parallel input (1); LSB
C parallel output (8); MSB
C parallel output (7)
C parallel output (6)
C parallel output (5)
VCC2
GND
C parallel output (4)
C parallel output (3)
C parallel output (2)
C parallel output (1); LSB
C parallel input (8); MSB
C parallel input (7)
C parallel input (6)
C parallel input (5)
C parallel input (4)
C parallel input (3)
I/O
O
—
—
—
—
—
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
O
O
O
O
—
—
O
O
O
O
I
I
I
I
I
I
Description
Luminance-signal analog output
GND
Analog system power supply: 3.3 V
GND
Digital system power supply: 3.3 V
GND
Digital interface clock output
Color-difference signal phase clock
Luminance-signal digital output MSB
Luminance-signal digital output
Luminance-signal digital output
Luminance-signal digital output
Luminance-signal digital output
Luminance-signal digital output
Luminance-signal digital output
Luminance-signal digital output LSB
Luminance-signal digital input MSB
Luminance-signal digital input
Luminance-signal digital input
Luminance-signal digital input
Luminance-signal digital input
Luminance-signal digital input
Luminance-signal digital input
Luminance-signal digital input LSB
Chrominance-signal digital output MSB
Chrominance-signal digital output
Chrominance-signal digital output
Chrominance-signal digital output
3.3 V power supply
GND
Chrominance-signal digital output
Chrominance-signal digital output
Chrominance-signal digital output
Chrominance-signal digital output LSB
Chrominance-signal digital input MSB
Chrominance-signal digital input
Chrominance-signal digital input
Chrominance-signal digital input
Chrominance-signal digital input
Chrominance-signal digital input
I/O
Format
OA
GNDA
VCCA
GNDA
VCCI
GNDI
ICZC2R
ICZC2R
OC2R
OC2R
OC2R
OC2R
OC2R
OC2R
OC2R
OC2R
ICD
ICD
ICD
ICD
ICD
ICD
ICD
ICD
OC2R
OC2R
OC2R
OC2R
VCCO
GNDO
OC2R
OC2R
OC2R
OC2R
ICD
ICD
ICD
ICD
ICD
ICD
86
87
88
89
90
91
92
93
94
CPI (2)
CPI (1)
NME
FP
ZOOM_HD
AD (10)
AD (9)
AD (8)
AD (7)
C parallel input (2)
C parallel input (1); LSB
Memory HD output
Field pulse
Zoom HD output
AD input (10); MSB
AD input (9)
AD input (8)
AD input (7)
I
I
O
O
O
I
I
I
I
Chrominance-signal digital input
Chrominance-signal digital input LSB
Line memory control output
Field pulse
Horizontal synchronization signal
A/D data input MSB
A/D data input
A/D data input
A/D data input
ICD
ICD
ICZC2DR
ICZC2R
ICZC2R
IC
IC
IC
IC
Rev.1.00 Jun 15, 2005 page 5 of 21
HD49815TF
Pin Description (cont.)
Pin No.
95
96
97
98
99
100
101
102
103
Symbol
AD (6)
AD (5)
AD (4)
AD (3)
AD (2)
AD (1)
ADCK
CPREF
DSP_MCK
104
105
106
107
108
109
Pin Name
AD input (6)
AD input (5)
AD input (4)
AD input (3)
AD input (2)
AD input (1); LSB
AD clock
Clamp reference output
I/O
Description
I
I
I
I
I
I
O
O
A/D data input
A/D data input
A/D data input
A/D data input
A/D data input
A/D data input LSB
A/D converter clock
Clamp reference pulse
O
VDD
VSS
SP1
SP2
OBP
VDD
Microprocessor clock
output
VCC2
GND
Sampling pulse 1
Sampling pulse 2
OBP pulse
VCC1
Microprocessor clock output:
SP-A7 [8] output changeover
3.3 V power supply
GND
Sampling pulse for the AGC/CDS IC
Sampling pulse for the AGC/CDS IC
Optical black-pulse output
110
111
112
H1
H2
VDD
H1
H2
VCC1
O
O
—
113
114
115
116
117
118
119
120
RG
VDD
XV1
XV2
XV3
XV4
XSG1
XSG2
Reset gate
VCC2
XV1
XV2
XV3
XV4
XSG1
XSG2
O
—
O
O
O
O
O
O
Rev.1.00 Jun 15, 2005 page 6 of 21
—
—
O
O
O
—
I/O
Format
IC
IC
IC
IC
IC
IC
ICZC2R
2C3
ICZC2R
VCCO
GNDO
ICZC2
ICZC2
ICZC2R
3 V or 5 V power supply
(H1/H2 power supply)
CCD-sensor horizontal drive pulse
CCD-sensor horizontal drive pulse
VCCC35
5 V power supply
(RG power supply)
CCD-sensor control reset gate
3.3 V power supply
CCD-sensor vertical control pulse
CCD-sensor vertical control pulse
CCD-sensor vertical control pulse
CCD-sensor vertical control pulse
CCD-sensor vertical control pulse
CCD-sensor vertical control pulse
VCCC5
OC3R
OC3R
ZC3R
VCCO
ICZC2R
ICZC2R
ICZC2R
ICZC2R
ZC2R
ZC2R
HD49815TF
Description of I/O Format
I/O Format
IC
ICD
ICS
ICSD
ICZC2
ICZC2DR
ICZC2R
OC2R
OC3R
IQ2
OQ2
IQ3
OQ3
ZC2
ZC2R
ZC3
ZC3R
VCCI
VCCO
VCCC
VCCC5
VCCC35
GNDI
GNDO
GNDC
IA
OA
VCCA
GNDA
Contents
CMOS level input
CMOS level input with pull-down resistor
CMOS level schmitt input
CMOS level input with pull-down resistor
CMOS level common I/O (4 mA)
CMOS level common I/O with pull-down resistor and through-put control (4 mA)
CMOS level common I/O with through-put control (4 mA)
CMOS level output with through-put control (4 mA)
CMOS level output with through-put control (8 mA)
Crystal oscillator input
Crystal oscillator output
Crystal oscillator input
Crystal oscillator output
CMOS-level three-state output (4 mA)
CMOS-level three-state output with through-put control (4 mA)
CMOS-level three-state output (8 mA)
CMOS-level three-state output with through-put control (8 mA)
Core system power supply: 3 V
Puddling system power supply: 3 V
Common power supply: 3 V
Common power supply: 5 V for pin 112
Common power supply: 3 or 5 V for pin 109
Core system GND
Puddling system GND
Common GND
Analog input
Analog output
Analog power supply
Analog GND
Notes: 1. Pin 113 is used for 5 V system output.
2. Pins 110 and 111 are used for 3 V or 5 V system output. They depend on the voltage of pin 109.
Rev.1.00 Jun 15, 2005 page 7 of 21
Rev.1.00 Jun 15, 2005 page 8 of 21
16
16
16
16
16
1HDL
FV, HD, MCK, MCKS
PLLP, PLLN, fsc, CBLK
CP, CSYNC, EP1-3
IDP, SCBLK, etc.
FV,
CHD etc. 16
H1, H2, RG, XV1 to 4
XSG1,2, XSUB
SSG
DL
1HDL
Timing
generator
Memory
control
AGC
ADCK, OBP, SP1
SP2, PBLK
De-Knee
SW
LPF
to
CDS/AGC 16
to
Vdriver 16
CCD
DSP_MCK 16
M_CK 16
X'tal 2
X'tal 1
10-bit
A/D input
LPF
+
Zoom
function
PreFilter
+
CLK
conversion
MOD
7.5IRE
+
16 16 16 16
BLK
+
Fade
C-G
16 16 16 16
Y
C
Highlight
enhancer
YL
Matrix
Gamma
correction
Microprocessor interface
SW
SW
Titler
Gamma
correction
WB
RGB
Gain
SDO
Digital interface
SW
SW
SW
SW
+
+
RGB Setup
RGB
Matrix
Y Setup
Luminance
correction
Climit
AE
detection
H.V
enhancer
LINE
SW
AF
detection
8-bit
8-bit
WB
detection
Axis
conversion
(WB)
Axis
conversion
C.DAC
Y.DAC
Base
clipping
16
C out
Y out
16
HD49815TF
Block Diagram
CPI
SLD
SDCK
SDI
YPI
CPO
YPO
HD49815TF
Absolute Maximum Ratings
(Ta = 25°C)
Item
Ratings
Unit
Power supply voltage
VCC
–0.2 to +6.8
V
Pin voltage (5 V operation block)
Vt5V
–0.2 to VCC1 +0.2
V
Pin voltage (3 V operation block)
Vt3V
–0.2 to VCC2 +0.2
V
Output current
Per output
Io
–32 to +32
mA
Per GND-VCC pair
Iot
–72 to +72
mA
Allowable power dissipation
Popr
450
mW
Operating temperature
Topr
–10 to +75
°C
Storage temperature
With bias
Tbias
–10 to +75
°C
Without bias
Tstg
–40 to +125
°C
Notes: 1. Using this LSI at values in excess of the absolute maximum ratings may permanently damage the LSI. The
LSI should normally be operated under the conditions specified for the electrical characteristics. Exceeding
these conditions may lead to incorrect operation and may adversely affect LSI reliability.
2. All voltage values are referenced to GND = 0 V.
3. The pin voltage ratings also apply to the NC pins.
4. VCC1 indicates the 5 V system power supply and VCC2 indicates the 3 V system power supply.
Rev.1.00 Jun 15, 2005 page 9 of 21
Symbol
HD49815TF
Electrical Characteristics
(VCC1 = 4.75 V to 5.25 V, VCC2 = 2.85 V to 3.15 V, AVCC = 2.85 V to 3.15 V, Ta = 25°C)
Item
CMOS-level
input voltage
CMOS schmitt
input voltage
Output voltage
Symbol
VIHC
VILC
VTC+
VTC–
VOHC1
Min
VCC2×0.75
0.0
2.50
0.0
VCC1–0.5
Typ
—
—
—
—
—
Max
VCC2
VCC2×0.20
VCC2
0.60
—
Unit
V
V
V
V
V
Test Conditions
Note
VOLC1
—
—
0.4
V
IOL = 200 µA
5 V system pin
VOHC2
VCC2–0.5
—
—
V
IOH = –200 µA
3 V system pin
1, 5
VOLC2
—
—
0.4
V
1, 6
Input leakage current
Output leakage current
ILI
ILO
—
—
—
—
1.0
1.0
µA
µA
IOL = 200 µA
3 V system pin
VIN = 0 V to VCC
2
Pull-down current
IPD
5
—
100
µA
Output Hi-Z
conditions
VIN = VCC2 = 3 V
Power dissipation
Popr
—
—
450
mW
VCC1 = 5 V,
VCC2 = 3 V,
AVCC = 3 V
3
Analog output voltage
(full scale)
Vfull
0.80
1.00
1.20
V
VCC1 = 5 V
VCC2 = 3 V
IOH = –200 µA
5 V system pin
1
2
3, 4
Vzero
–0.20
0.00
0.20
V
Analog output voltage
(zero scale)
Differential linearity
DNL
–2.0
—
2.0
LSB
Notes: 1. Output voltage must be measured in the steady state.
2. Except for pins that include a pull-down resistor.
3. Guaranteed at CBU = 0.1 µF, CBL = 0.1 µF, REXT = 3.4 kΩ, analog output load resistance = 500 Ω, and Ta
= 25°C.
4. Applied to pins indicated as OA in the I/O format column of the pin-functions table.
5. Because VOH of pin 31 cannot be measured logically, it was not tested.
6. Because VOL of pin 32 cannot be measured logically, it was not tested.
7. VCC1, VCC2, and AVCC indicate the 5 V system power supply, the 3 V system power supply, and the analog
system power supply, respectively. VCC indicates VCC1, VCC2, and AVCC.
8. The voltage range of pin 109 (VCCC35) is VCC = 2.85 V to 5.25 V.
Rev.1.00 Jun 15, 2005 page 10 of 21
HD49815TF
Crystal Oscillation Circuit
1. Measuring conditions
The oscillation frequency was measured under the following conditions
VCC1 = 5.0 V
VCC2 = 3 V
Ta = 25°C
8 MHz, 20 MHz, and 24 MHz:
Rf = 1 to 10 MΩ
Cin, Cout = 20 pF (±20 pF)
32 MHz:
Rf = 1 to 10 MΩ
Cin = 20 pF (±20 pF)
Cout = 100 pF (±20 pF), Co = 15 pF (±5 pF), Lout = 1 µH
The conditions above may be changed within the range of measuring conditions.
2. Measuring method
Under the measuring conditions above, two methods were tested.
fmin. = 20 MHz, and fmax. = 32 MHz (applied to pins 26 and 27)
fmin. = 8 MHz, and fmax. = 24 MHz (applied to pins 34 and 35)
Note: The oscillation start time tosc is max. = 200 ms.
3. Measuring circuit
To the internal circuit
Xout
Xin
Dividing
counter
Cin
Monitor pin
Cout
Counter
Co
Lout
Note: The part enclosed by the dotted line in the above
circuit is used when measuring at 32 MHz.
Figure 1 Measuring Circuit
Rev.1.00 Jun 15, 2005 page 11 of 21
HD49815TF
Built-in Functions and System Configuration
System Configuration
HD49815TF
Lens
CCD HD49323AF-01
CDS/AGC+
10-bit ADC
Color
processing
Input
line
memory
Luminance
processing
SP1/2
Microprocessor
I/F
TG
SSG
H1, H2
V.Driver
Zoom
processing
Encode
DAC
C-signal output
Y-signal output
R-Y/B-Y
digital output
Y-signal
digital output
Initial setting resistor input and
AE, AWB detection data output
XV1 to 4
AGC gain setting
System
control
AE
(iris)
control
AWB
(white
balance)
control
8-bit single-chip microcomputer (H8 series)
Figure 2 System Configuration
System Description
1. CCD
The following lists the pixels of the CCD sensors that can be used with the HD49815TF. For other pixel numbers,
contact our sales dept.
512 (H) × 492 (V) NTSC
512 (H) × 582 (V) PAL
682 (H) × 492 (V) NTSC
681 (H) × 582 (V) PAL
2. CDS/AGC + 10-bit ADC
The HD49323AF-01 (manufactured by Renesas) is recommended as an optimal CDS/AGC + 10-bit ADC IC for the
HD49815TF. Since the HD49323AF-01 provides a correlated double sampling circuit that realizes high S/N and an
automatic gain control (AGC) circuit that implements programmable control of 0 dB to 34.7 dB, it enables a highimage-quality camera system when used in conjunction with the HD49815TF.
3. 8-bit single-chip microcomputer
The 8-bit single-chip microcomputer controls the system. It receives the image detection data that the HD49815TF
is gathering and implements automatic iris control (AE), automatic white balance control (AWB), and automatic
focus control (AF).
When setting the power on, this microcomputer implements the initial setting to the state data of the HD49815TF.
For details on the state data, see “Renesas Camera DSP (HD49815TF) State Data”.
Rev.1.00 Jun 15, 2005 page 12 of 21
HD49815TF
Built-in Functions
1. Input line memory block
A/D input
10-bit
16
De-Knee
AGC
DL
+
To the color-signal
processing block
1HDL
Memory
control
16
1HDL
To the luminance-signal
processing block
Figure 3 Input Line Memory Block
a. De-knee function
When the CDS/AGC IC at the pre-stage or the external circuit uses the knee circuit to expand the dynamic range
of the signal, the de-knee (inverse knee) circuit returns the signal converted by the knee circuit to the original
state.
The de-knee point can be set in State Data SP_A0 [1]. The gain of the high-luminance block is 1/2.
b. AGC function
A digital AGC circuit is provided. The AGC gain can be set in State Data SP_A0 [2] from 1 to 16 times.
c. 1H delay line (1HDL) function
This circuit obtains horizontal efficient pixels of the CCD output signal. The number of efficient pixels is set in
State Data SP_A0 [9, 10] and TM_A0 [14] MCSET.
2. Color-signal processing block
From
the input
line
memory
block
+
LINE
SW
Climit
PreFilter
RGB
Matrix
+
RGB Setup
RGB
Gain
Gamma
correction
WB
YL
Matrix
Axis
conversion
C-G
To the luminance
signal processing block
Base
clipping
To
the zoom
function
Axis
conversion
(WB)
To the AWB
detection block
Figure 4 Color-Signal Processing Block
a. C-limit (complementary color clipping level) function
High clipping processing is performed on the complementary color signals independently. High clipping is set
in State Data SP_A2 [0 to 3].
The complementary color signal indicates Gb: (G + Cy), Wr: (Ye + Mg), Wb: (Mg + Cy), and Gr: (G + Ye).
b. RGB-matrix block
The three primary colors (red, green, and blue) are acquired in the RGB matrix by multiplying arbitrary
coefficients by the four complementary colors (Gb, Wr, Wb, and Gr) and taking the total of those results. The
RGB matrix is designed to support the minimum color moire and to enable free color reproduction. Arbitrary
coefficients are set in State Data SP_A2 [4 to 15]. The following shows the formula.
KRa KRb KRc KRd
R
B = KBa KBb KBc KBd
KGa KGb KGc KGd
G
Gb
Wr
Wb
Gr
State Data SP_A2 [4 to 15]
Rev.1.00 Jun 15, 2005 page 13 of 21
HD49815TF
c. RGB-setup block
The black level of the color signals is variable according to the coefficients of the RGB matrix. The value
calculated by the formula below is subtracted from the color signal to correct the black level. The subtracted
value can be set externally and is set in State Data SP_A3 [0 to 2].
Formula = −[48 × Σ (Matrix data) × 23]
d. RGB-gain block
The RGB gain value acquired in the AWB control is set in the RGB gain circuit to improve the white
reproduction performance. As it is set prior to the gamma correction, it changes the gamma correction amount.
The RGB gain can be set in State Data SP_A3 [3 to 5] from 1 to 256 times. (The G gain is set from 1 to 128
times.)
e. C gamma (γ) correction block
The C gamma correction circuit performs gamma processing on the RGB signal. It is set in State Data SP_A3 [6
to 9]. Four kinds of values can be set independently, according to the input-signal level, to acquire optimal
gamma characteristics: the C gamma dark (to reduce the gain of the small signals for improving S/N), C gamma
coefficient (to control the expansion of the gamma curve), C gamma knee (to decide the slope of the large
signals), and C gamma limit (to perform high-clipping processing for the input signal of the C gamma circuit).
f. YL matrix block
The luminance level changes according to the color temperature of the imaged object. Set State Data SP_A5 [12,
13] for the luminance correction. To correct the luminance, create YL from the three primary colors (R, G, and
B) and convert it to the luminance signal level. The YL matrix circuit creates the YL level from the RGB signal.
The YL matrix is set in State Data SP_A3 [11 to 13].
g. The axis-conversion (C-Y matrix) block
The C-Y (color-difference) matrix takes R-G and B-G as its input signals, and creates the R-Y and B-Y colordifference signals by setting coefficients for those inputs.
The axis-conversion (C-Y matrix) circuits are set in State Data SP_A8 [0 to 5].
h. Base-clipping block
Since base clipping is performed on the color-difference signals, the base-clipping circuit has the characteristics
of clipping the sections near axes on a vector scope.
This circuit is set in State Data SP_A8 [8].
3. Luminance-signal-processing block
To
the AWBdetection block
from
YL matrix
From
the input
line
memory
block
H.V
enhancer
Luminance
correction
+
Gamma
correction
Y Setup
Highlight
enhancer
Fade
+
To
the zoom
function
7.5IRE
Figure 5 Luminance-Signal-Processing Block
a. H-enhancer function
The H-enhancer circuit allows the core level, the enhancer gain, and the noise coefficient to be set independently
to acquire optimal characteristics.
This circuit is set in State Data SP_A4 [4 to 7].
b. V-enhancer function
The V-enhancer circuit allows the enhancer coefficient to be set and can control the gain for only those signal
components that exceed the set core level.
This circuit is set in State Data SP_A4 [8 to 10].
c. Luminance correction
The ratio of the red and blue levels changes according to the color temperature of the imaged object. For
example, if a red object is imaged at a low color temperature, the luminance level increases and the object
appears to have a lower chrominance. Therefore, the luminance correction circuit performs luminancecorrection processing to implement color depth reproduction.
The luminance-correction circuit is set in State Data SP_A5 [12, 13].
Rev.1.00 Jun 15, 2005 page 14 of 21
HD49815TF
d. Y setup
Since the OB clamp processes the signal, the black level of the 10-bit signal input to the HD49815TF is fixed to
48/1024. The Y-setup circuit subtracts 48 at the black level. However, when 48 at the black level differs due to
the noise mixed in the analog signal, the Y-setup circuit subtracts that value.
The Y-setup circuit is set in State Data SP_A5 [6].
e. Gamma correction
The gamma-correction circuit implements the gamma-correction processing for the separated Y signal. Four
kinds of values can be set independently, according to the input-signal level, to acquire optimal gamma
characteristics: the gamma input limit, the gamma knee coefficient, the gamma coefficient, and the gamma black
clipping.
The gamma correction circuit is set in State Data SP_A5 [1 to 4].
f. Highlight enhancer
For input-Y signal levels in excess of 100 IRE, the highlight enhancer implements highlight enhancer processing.
This circuit is set in State Data SP_A5 [0, 5, and 14].
g. Fade
The fade circuit amplifies the luminance signal by a factor of 0 to 1.
This circuit is set in State Data SP_A5 [9].
4. Zoom, encode block, TG, SSG, and AWB and AE detection blocks
a. Zoom processing
The Y, R-Y, and B-Y signals completed the color-signal processing and the luminance-signal processing can be
electronically zoomed by a factor of 1 to 256.
After clipping CCD signals for V direction, zoom circuit clips these signals for H direction, and expand these
signals for H and V directions.
The zooming times and the read starting position for the V and H directions are set in State Data TM_A2 [3, 4, 5,
6, 8, and 9] and ZM_A0 to 6.
b. Encode block
This circuit encodes the signals completed the color-signal processing, the luminance-signal processing, and the
zoom processing as the NTSC/PAL TV-monitor method.
A DAC that converts the digital signal to an analog signal is provided. The DAC has two channels: one for R-Y
signals and one for B-Y signals.
c. TG and SSG
The TG generates the signals required to drive the CCD sensor (H1, H2, RG, SG1/2, and the V transfer pulse),
and the CDS/AGC control signals (SP1 and SP2).
In addition, the SSG generates the signals to synchronize with the TV monitor (the Sync signal).
The drive timing of the generated signals differs according to the manufacturer and the specifications of the
CCD sensor. Setting the state data enables setting of any timing.
The state data of TG and SSG can be set in TM_A0, A1, A2, A3, and A8.
d. AWB- and AE-detection blocks
The HD49815TF provides automatic white-balance (AWB) and automatic-iris (AE) detection circuits that are
indispensable for a camera.
The AWB-detection block takes the R-Y and B-Y color-difference signals completed the color-signal processing,
and converts to the R-B and MG-G axes. The converted signals are sent to circuits for the white detection to
obtain white signal components only, and the white-color difference value is detected. The 8-bit single-chip
microcomputer acquires this detection data, and controls the R and B gains to produce the true white.
The State Data of the AWB detection is AWB_A0 and A8.
The AE-detection block divides the CCD output signal converted to digital by the 10-bit ADC to six arbitrary
areas, and performs integration processing. This function enables detection of the lighting level of the image
signal.
The 8-bit single-chip microcomputer acquires this detection data, and controls the accumulation amount (the
shutter) of the CCD sensor or the iris motor of the lens to maintain the proper lighting.
The State Data of the AF detection is AE_A0 to A7 and A8.
Rev.1.00 Jun 15, 2005 page 15 of 21
HD49815TF
Microcomputer Interface Specifications
• Write format
SLD
(Pin 7)
SDCK
(Pin 6)
LSB
SDI
(Pin 5)
MSB
D1 D2 D3 D4 D5 D6 D7 D8
1 byte
Data (N byte)
STD3-----STH2-----STD1
LSB
MSB LSB
MSB
D1 D2 D3 D4 D5 D6 D7 D8 D1 D2 D3 D4 D5 D6 D7 D8
Address
STAL
STAH
Function address
(write address)
• Read format
SLD
(Pin 7)
SDCK
(Pin 6)
LSB
SDI
(Pin 5)
MSB LSB
MSB
D1 D2 D3 D4 D5 D6 D7 D8 D1 D2 D3 D4 D5 D6 D7 D8
STAL
1 byte or 2 byte
STAH
Function address
LSB
SDO
(Pin 8)
MSB
Hi-Z
Hi-Z
Data
(N byte)
Notes: 1.
2.
3.
4.
Synchronous serial transfer (The microcomputer serial port can be used.)
Transfer frequency: 3.58 MHz or lower
Data and address are handled in a byte unit.
The clock and load pulse are used in common for read/write.
Rev.1.00 Jun 15, 2005 page 16 of 21
HD49815TF
Data Transfer Specification
For data transfer between the HD49815TF and the microcomputer, two types (N and E for write, and R1 and R2 for
read) are available. The following table shows the relationship between the function block and the transfer
specifications. On the next page, the details of the transfer specifications are described.
Function Block
Signal processing
TM
Iris
White balance
AF
ZOOM
Note:
Transfer Mode
W
W
R
W
R
W
R
W
R
W
Transfer
1
Specifications *
N
N
E
R1
N
R2
N
R1
N
R1
N
Related Address
SP_A0, 2 to 5, 7 to 10, 15
TM_A3, 15
TM_A0 to 2, 8, 10 to 12
TMR_A0
AE_A0 to 7
AE_A8
AWB_A0
AWB_A8
AF_A0 to 3
AF_A8 to 13
ZM_A0 to 6
1. Transfer specifications
Type N : Normal transfer from the microcomputer to the DSP
Type E : Transfer using the set pulse (synchronous with VD) or the reset signal (used as a synchronous
pulse in the DSP) sent from the microcomputer to the RS latch in the DSP
Note: This cannot be set during the standby mode.
Type R1 : Data transfer (1) from the DSP to microcomputer
Type R2 : Data transfer (2) from the DSP to microcomputer
Rev.1.00 Jun 15, 2005 page 17 of 21
HD49815TF
• Type N
Transfer
specification
Pulse Timing
Conditions
SLD
(Pin 7)
A = 100 ns or more
B = 100 ns or more
C = 100 ns or more
N
SDCK
(Pin 6)
A
B
C
• Type E
Transfer
specification
Pulse Timing
SLD
(Pin 7)
E
SDCK
(Pin 6)
A
B
D
Conditions
270,000
pixels
150 ns
A 0.5 / fs + 100 ns or more or more
300 ns
B 2 / fs + 100 ns or more
or more
650 ns
D 5.5 / fs + 100 ns or more or more
fs Sensor clock
100 ns
410,000
pixels
135 ns
or more
240 ns
or more
485 ns
or more
70 ns
• Type R1
Transfer
specification
Pulse Timing
SLD
(Pin 7)
R1
Conditions
A = 100 ns or more
B = 100 ns or more
D = 400 ns or more
SDCK
(Pin 6)
B
A
D
Do not read the white balance data and the
AF read data within the 1H period from the
start of the V blanking.
• Type R2
Transfer
specification
Pulse Timing
A = 100 ns or more
B = 100 ns or more
SLD
(Pin 7)
R2
Conditions
SDCK
(Pin 6)
A
D {1 / fs × (32 + 5)
+ 400 ns} or more
B
D
Rev.1.00 Jun 15, 2005 page 18 of 21
fs Sensor clock
270,000
pixels
4.1 µs
or more
410,000
pixels
2.99 µs
or more
100 ns
70 ns
HD49815TF
Note:
2 to 9.
Function addresses
The following table shows the function addresses for each function block (during state data transfer) and the
data to be transferred from the microcomputer.
Table 2
Function Addresses for each Function Block and State Data
List of Data Transferred
2
Function Address
STAH
STAL
STD1
STD2
Signal D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1
processing
0 0 0 0 0 0 0 0 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗
(Setting
example) 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 D8 D7 D6 D5 D4 D3 D2 D1        D9
3
Function Address
STAH
STAL
STD1
STD2
TM write D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1
0 0 0 0 0 0 0 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗
(Setting
example) 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 D8 D7 D6 D5 D4 D3 D2 D1        
4
Function Address
TM read D8 D7 D6 D5 D4 D3 D2 D1
Data read for automatic phase adjustment for SP1, SP2, and RG
0 0 0 0 1 0 0 1
Function Address ADATA
STAH
STAL
STD1
STD2
D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1
0 0 0 1 0 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗  ∗ ∗ ∗ ∗ 0 0 0 0 0 0 0 0
5 0 0 0 1 0 1 0 0      D3 D2 D1         0 0 0 0 0 0 0 0
W Function Address ADATA
STAH
STAL
STD1
STD2
AE
D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1
0 0 0 0 0 0 0 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗  ∗ ∗ ∗ ∗ ∗ 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0    D5 D4 D3 D2 D1 0 0 0 0 0 0 0 0
Function Address
STAH
STAL
6 D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1
Read area setting by STAL (4 bits)
R
0 0 0 1 1 0 0 0  ∗ ∗ ∗ ∗
Function Address ADATA
STAH
STAL
STD1
STD2
D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1
0 0 1 0 0  ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0 0 0 0 0 0 0 0
7 0 0 1 0 0       0 0 0 0 1   D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 0 0
STAH
STAL
STD1
W Function Address ADATA
Window setting
AWB
D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1
for white balance
WB detection
0 0 0 0 0 0 0 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗  ∗ ∗ ∗ ∗ ∗
axis phase setting
0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 D8 D7 D6 D5 D4 D3 D2 D1
Function Address
8 D8 D7 D6 D5 D4 D3 D2 D1
White balance read
R
0 0 1 0 1 0 0 0
Function Address ADATA
STAH
STAL
HPF bandwidth selection
D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1
0 0 1 1 0 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗
Base-clip quantity setting, etc.
9 0 0 1 1 0 0 0 0     D4 D3 D2 D1
W Function Address ADATA
STAH
STAL
STD1
D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1 Setting for integration
AF
and display gate
0 0 0 0 0 0 0 1 1 1 0 0 0 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗
0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 1 D8 D7 D6 D5 D4 D3 D2 D1
Function Address
10 D8 D7 D6 D5 D4 D3 D2 D1
Vf fetch address (read_cycle)
R
0 0 1 1 1 ∗ ∗ ∗
Data 3
Data 2
Header
Data 1
D8 D7 D6 D5 D4 D3 D2 D1
1 0 1 1 0 ∗ ∗ ∗
ZOOM W
Data 5
Data 6
Data 4
Remarks
This example
is related to
SP-A0[9].
This example
is related to
TM-A0 [14].
This example
is related to
the IRIS peak
detection area.
This example
is related to
the window
H count 3.
This example
is related to
the offset R-B.
This example
is related to
the V count 2.
This example
is related to
the HRF
bandwidth
selection.
This example
is related to
the differential
gate of V-end.
Note: For the ZOOM, the transfer of in total of seven bytes is required for the header and data 1 to 6.
Rev.1.00 Jun 15, 2005 page 19 of 21
HD49815TF
Digital Interface Timing
• The output specification and timing of the digital interface output (Y, R-Y, B-Y)
NRYBY
DICK
4 : 2 : 2 output timing
CPO (1 to 8)
R-Y0
B-Y0
R-Y2
B-Y1
R-Y4
B-Y4
YPO (1 to 8)
Y0
Y1
Y2
Y3
Y4
Y5
• Detailed specifications of digital interface timing
X'tal CLK
35 nsec
70 nsec
DICK output
2 to 15 nsec
CPO, YPO
10 to 50 nsec
CPI, YPI
20 to 35 nsec
NRYBY
(Reference)
NRYBY
DICK
CPO, YPO
CPI, YPI
: R-Y/B-Y determination pulse
: Clock dedicated to the digital interface (The clock generated from the external X'tal.)
: Digital interface output terminal
: Digital interface input terminal
Rev.1.00 Jun 15, 2005 page 20 of 21
HD49815TF
Package Dimensions
JEITA Package Code
P-TQFP120-14x14-0.40
RENESAS Code
PTQP0120LA-A
Previous Code
TFP-120/TFP-120V
MASS[Typ.]
0.5g
HD
*1
D
90
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
61
91
60
bp
Reference
Symbol
D
c
c1
HE
Dimension in Millimeters
Min
Nom
Max
14
E
14
A2
1.00
*2
E
b1
Terminal cross section
15.8
16.0
16.2
HE
15.8
16.0
16.2
A1
0.00
0.10
0.20
bp
0.12
0.17
0.22
0.12
0.17
1.20
ZE
A
31
120
HD
0.15
b1
ZD
c
c1
Index mark
θ
F
A1
L
L1
Detail F
e
*3
y
bp
θ
0°
e
M
8°
0.4
x
0.07
y
0.10
ZD
L
L1
Rev.1.00 Jun 15, 2005 page 21 of 21
0.15
1.20
1.20
ZE
x
0.22
c
A2
30
A
1
0.4
0.5
1.0
0.6
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits,
(ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
http://www.renesas.com
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon 2.0