ETC P3C1024

P3C1024
HIGH SPEED 128K x 8
3.3V STATIC CMOS RAM
FEATURES
3.3 Volts Power Supply
High Speed (Equal Access and Cycle Times)
— 15/17/20/25/35 ns (Commercial)
— 20/25/35/45 ns (Industrial)
Single 3.3 Volts 0.3 Volts Power Supply
Easy Memory Expansion Using
CE2 and
1,
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast tOE
Automatic Power Down
Packages
—32-Pin DIP and SOJ
DESCRIPTION
The P3C1024 is a 1,048,576-bit high-speed CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 3.3V 0.3V tolerance power
supply.
The P3C1024 device provides asynchronous operations with matching access and cycle times. Memory
locations are specified on address pins A0 to A16. Reading is accomplished by device selection ( 1 low and
CE2 high) and output enabling ( ) while write enable
(
) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory
Access times of 20 nanoseconds permit greatly en- location is presented on the data input/output pins. The
hanced system operating speeds. CMOS is utilized to input/output pins stay in the HIGH Z state when either
reduce power consumption to a low level. The P3C1024
or
is HIGH or
or CE2 is LOW.
1
is a member of a family of PACE RAM™ products offering fast access times.
Package options for the P3C1024 include 32-pin 300
mil DIP and SOJ packages as well as 400 mil SOJ.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
A
262,144BIT
MEMORY
ARRAY
(9)
A
INPUT
DATA
CONTROL
COLUMN
I/O
I/O2
COLUMN
SELECT
32
VCC
2
31
A15
3
30
CE2
A12
4
29
WE
A7
5
28
A13
6
27
7
26
A8
A9
A4
A3
8
25
A11
9
24
OE
A2
A1
10
23
11
22
A10
CE1
A0
I/O0
12
21
13
20
I/O1
I/O2
WE
CE2
1
A6
A5
I/O1
CE1
NC
A16
A14
•••
CONTROL
CIRCUIT
A
(8)
GND
•••
A
1024.1
OE
I/O7
I/O6
14
19
15
16
18
I/O5
I/O4
17
I/O3
1024.2
DIP , SOJ
TOP VIEW
Means Quality, Service and Speed
1Q97
159
160