Inchange Semiconductor Product Specification 2N6489 2N6490 2N6491 Silicon PNP Power Transistors DESCRIPTION ・With TO-220 package ・Excellent safe operating area ・Complement to type 2N6486 2N6487 2N6488 respectively APPLICATIONS ・Power amplifier and medium speed switching applications PINNING PIN DESCRIPTION 1 Emitter 2 Collector;connected to mounting base 3 Base Fig.1 simplified outline (TO-220) and symbol 导体 半 电 R O T UC Absolute maximum ratings(Ta=25℃) 固 SYMBOL VCBO VCEO VEBO PARAMETER CONDITIONS 2N6489 Collector-base voltage 2N6490 EMIC Open emitter S E G N A H C IN Collector-emitter voltage Emitter-base voltage 2N6491 2N6489 2N6490 OND Open base 2N6491 VALUE UNIT -50 -70 V -90 -40 -60 V -80 Open collector -5 V IC Collector current -15 A IB Base current -5 A PT Total power dissipation 75 W Tj Junction temperature 150 ℃ Tstg Storage temperature -65~150 ℃ MAX UNIT 1.67 ℃/W TC=25℃ THERMAL CHARACTERISTICS SYMBOL Rth j-c PARAMETER Thermal resistance from junction to case Inchange Semiconductor Product Specification 2N6489 2N6490 2N6491 Silicon PNP Power Transistors CHARACTERISTICS Tj=25℃ unless otherwise specified SYMBOL PARAMETER CONDITIONS 2N6489 VCEO(SUS) Collector-emitter sustaining voltage 2N6490 MIN TYP. MAX UNIT -40 IC=-0.2A ;IB=0 2N6491 V -60 -80 VCEsat-1 Collector-emitter saturation voltage IC=-5A;IB=-0.5A -1.3 V VCEsat-2 Collector-emitter saturation voltage IC=-15A;IB=-5A -3.5 V VBE-1 Base-emitter on voltage IC=-5A ; VCE=-4V -1.3 V VBE-2 Base-emitter on voltage IC=-15A ; VCE=-4V -3.5 V 2N6489 VCE=-45V; VCE=-40V;TC=150℃ -0.5 -5.0 2N6490 VCE=-65V; VCE=-60V;TC=150℃ 2N6491 VCE=-85V; VCE=-80V;TC=150℃ ICEX 导体 半 电 Collector cut-off current VBE=-1.5V 固 R O T UC -0.5 -5.0 D N O IC M E S GE -0.5 -5.0 N A H INC 2N6490 VCE=-30V;IB=0 2N6491 VCE=-40V;IB=0 IEBO Emitter cut-off current VEB=-5V; IC=0 hFE-1 DC current gain IC=-5A ; VCE=-4V 20 hFE-2 DC current gain IC=-15A ; VCE=-4V 5 ICEO Collector cut-off current 2N6489 VCE=-20V;IB=0 2 mA -1.0 mA -1.0 mA 150 Inchange Semiconductor Product Specification 2N6489 2N6490 2N6491 Silicon PNP Power Transistors PACKAGE OUTLINE 导体 半 电 固 R O T UC D N O IC M E S GE N A H INC Fig.2 Outline dimensions(unindicated tolerance:±0.10 mm) 3