UC1727 UC2727 UC3727 Isolated High Side IGBT Driver FEATURES DESCRIPTION • Receives Power and Signal from Single Isolation Transformer • Generates Split Rail for 4A Peak Bipolar Gate Drive • The UC1727 and its companion chip, the UC1726, provide all the necessary features to drive an isolated IGBT transistor from a TTL input signal. A unique modulation scheme is used to transmit both power and signal across an isolation boundary with a minimum of external components. 16V High Level Gate Drive • Low Level Gate Drive more Negative than -5V • Undervoltage Lockout • Desaturation Detection and Fault Processing • Separate Output Enable Input The chip generates a bipolar supply so that the gate can be driven to a negative voltage insuring the IGBT remains off in the presence of high common mode slew rates. • Programmable Stepped Gate Drive for Soft Turn On Uses include isolated off-line full bridge and half bridge drives for motors, switches, and any other load requiring full electrical isolation. • Programmable Stepped Gate Drive for Soft Fault Protection features include under voltage lockout and desaturation detection. High level gate drive signals are typically 16V. Intermediate high drive levels can be programmed for various periods of time to limit surge current at turn on and in the event of desaturation due to a short circuit. BLOCK DIAGRAM UDG-94005-2 12/94 UC1727 UC2727 UC3727 ABSOLUTE MAXIMUM RATINGS Supply voltage (VCC - VEE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Power Inputs (|A - B|) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45V Analog Input Voltage (ENBL, CLAMP). . . . . . . . . . . . . . . . . . -0.3 To Vcc+0.3 Analog Input Voltage (DSAT+, DSAT-) . . . . . . . . . . . . . . . . VEE-0.3 to VCC+0.3 Analog Input Current (DSAT+, DSAT-) . . . . . . . . . . . . . . . . . . . . . . -10 to 10mA Output Current, (OUT) DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8A Pulse (0.5µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4A FRPLY Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Note: All voltages are with respect to COM. Currents are positive into the specified terminal. CONNECTION DIAGRAMS DIL-18 (Top View) J Package PLCC-28 (Top View) QP Package DIL-20 (Top View) N Package SOIC-28 (Top View) DWP Package LCC-28 (Top View) LP Package PACKAGE PIN FUNCTION FUNCTION PIN N/C VEE N/C COM CLAMP B A VCC PVCC OUT PVEE DSAT+ DSATENBL NC TRC FRC FRPLY N/C N/C N/C 1 2 3-4 5 6 7 8 9 10 11 12-18 19 20 21 22 23 24 25 26 27 28 PACKAGE PIN FUNCTION FUNCTION PIN N/C VEE N/C COM CLAMP B A VCC PVCC OUT N/C PVEE N/C DSAT+ DSATENBL NC TRC FRC FRPLY N/C 2 1 2 3-4 5 6 7 8 9 10 11 12-13 14 15-18 19 20 21 22 23 24 25 26-28 UC1727 UC2727 UC3727 See Application Note U-143A "New Chip Pair Provides Isolated Drive for High Voltage IGBTs" PIN DESCRIPTIONS FRPLY: Fault Reply pin. Open collector output. Normally connected to VEE. When desaturation is detected, the pin opens. A, B: Signal and power input pins. Connect these pins to the secondary of the transformer driven by UC1726. CLAMP: Analog programming pin for intermediate drive level to be used at turn on or in response to a desaturation event. Requires a bypass capacitor to COM. OUT: Gate drive output. Connect to gate of IGBT with a series damping resistor greater than 3 ohms. COM: Self generated common for bipolar supply. This pin will be 16.5V below PVCC. TRC: Timing Resistor and Capacitor. Programs the duration that OUT will be held at CLAMP potential and the period of time the desaturation comparator will be ignored during the rising edge. DSAT+, DSAT-: Inputs to the desaturation comparator. Desaturation is detected when DSAT+ is greater than DSAT-. VCC: Positive supply voltage. Bypass to COM with a low ESL/ESR 1µF capacitor. ENBL: Negative true enable input. Tie to VCC to disable the chip. Connect to COM to enable the chip. If the ENBL pin is used as the primary input to the chip, connect B to VCC and A to VEE. VEE: Negative supply voltage. Bypass to COM with a low ESL/ESR 1µF capacitor. FRC: Fault Resistor and Capacitor. Programs the duration that OUT will be held at CLAMP potential during a desaturation event before it is driven fully low. Also sets the period of time that OUT will be held low before allowing it to be driven high again. PVEE: Output driver negative supply. Connect to VEE with a 3.3 ohm resistor and bypass to COM with a low ESL/ESR 1µF capacitor. PVCC: Output driver positive supply. Connect to VCC with a 3.3 ohm resistor and bypass to COM with a low ESL/ESR 1µF capacitor. ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = −55°C to 125°C for the UC1727, TA = −40°C to 85°C for the UC2727, TA = 0°C to 70°C for the UC3727, R(TRC) = 54.9k, C(TRC) = 180pF, R(FRC) = 309K, C(FRC) = 200pF, VCC - VEE = 25V, CLAMP = 9V, TA = TJ, and all voltages are measured with respect to COM. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS IF = 50mA 0.5 0.65 V IF = 500mA 1.2 2 V 16.5 17.5 V Power Input Receivers Forward Diode Drop VCC Regulator VCC 25 ≤ (VCC - VEE) ≤ 36V,I(COM) ≤ 15mA 15.5 Hysteresis Comparator Input Open Circuit Voltage (Measured with respect to VEE) 12 Input Impedance V 100 Hysteresis 44 47 kΩ 50 V 5 V −460 −900 µA Enable Input High Level Input Voltage 12 V Low Level Input Voltage Input Bias Current ENBL = COM Output Driver Saturation to VCC I(OUT) = -20mA 1.7 2.3 V Saturation to VCC I(OUT) = -500mA 2 2.5 V Saturation to VEE I(OUT) = 20mA 2 3 V Saturation to VEE I(OUT) = 500mA 2.4 3.6 V 3 UC1727 UC2727 UC3727 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = −55°C to 125°C for the UC1727, TA = −40°C to 85°C for the UC2727, TA = 0°C to 70°C for the UC3727, R(TRC) = 54.9k, C(TRC) = 180pF, R(FRC) = 309K, C(FRC) = 200pF, VCC - VEE = 25V, CLAMP = 9V, TA = TJ, and all voltages are measured with respect to COM. PARAMETER Output Driver (cont.) MIN TYP I(OUT) = -100mA 7 9 11 Fault Clamp Voltage |I(OUT)| = 100mA 8 10 12.5 V UVLO Saturation to VEE I(OUT) = 20mA,VCC no connection 2 3 V Rise and Fall Times Cl = 1n, CLAMP = VCC, ROUT = 3Ω (Note 1) 75 150 ns Turn on Clamp Voltage TEST CONDITIONS MAX UNITS V Turn On Sequence Timer Clamped Driver Time (Note 1) 0.4 1 1.7 µs Blanking Time (Note 1) 3 5 7 µs Clamped Driver Time (Note 1) 0.4 1 1.7 µs Fault Lock Off Time (Note 1) 15 25 35 µs Fault Manager FRPLY Saturation I(FRPLY) = 10mA 1.8 3 V FRPLY Leakage FRPLY = VCC 0 10 µA Input Offset Voltage (|vio|) VCM = VEE+2, VCM = VCC-2 0 20 mV Input Bias Current Delay to Output −1.5 150 10 C(FRC) = 0 (Note 1) µA ns 15.5 17 V Desaturation Detection Comparator Undervoltage Lock Out VCC Threshold 14 VCC Hysteresis 0.35 V VEE Threshold −4.5 −5.5 −6.5 V VEE Hysteresis 0.5 1 1.5 V Thermal Shutdown Threshold Hysteresis Not tested Not tested °C °C 175 45 Total Standby Current I(VCC) 24 Note 1: Guaranteed by design, but not 100% tested in production. APPLICATION INFORMATION Figure 1 shows the rectification and detection scheme used in the UC1727 to derive both power and signal information from the input waveform. VCC-VEE is generated by peak detecting the input signal via the internal bridge rectifier and storing it on external capacitors. COM is generated by an internal amplifier that maintains PVCC-COM = 16.5V. Signal detection is performed by the internal hysteresis comparator which senses the polarity of the input signal as shown in Figure 2. This is accomplished by setting (or resetting) the comparator only if the input signal exceeds 0.95VCC-VEE. In some cases it may be necessary to add a damping resistor across the transformer secondary to minimize ringing and eliminate false triggering of the hysteresis comparator as shown in Figure 3. Figure 1. Input Stage & Bipolar Supply 4 30 mA UC1727 UC2727 UC3727 APPLICATION INFORMATION (cont.) Figure 2. Input Waveform Figure 4. Rising Edge Waveform Figure 3. Output Pulsing Caused By Transformer Ringing Figure 5. Transient Desaturation Response GATE DRIVE WAVEFORM In the event that desaturation is detected outside the blanking interval, OUT will be driven back to the CLAMP plateau for a fault time set by a resistor from FRC to VCC and a capacitor to COM as: The rising edge of OUT can be programmed for a two step sequence as shown in Figure 4. The plateau voltage is programmed by a resistive divider from VCC to COM applied at CLAMP. CLAMP must be bypassed to COM. The plateau voltage is approximately OUT = CLAMP. The plateau time is set by a resistor from TRC to VCC and a capacitor to COM as: R−7.6k Tf = RC ln . R−12.4k If the event is transient, OUT will return high at the end of Tf as shown in Figure 5. During Tf, FRPLY is open. After Tf, FRPLY is connected to COM. R−7.6k Tp = RC ln . R−12.4k TRC also programs a blanking time during which the chip ignores the desaturation comparator. The blanking time is: Desaturation shown in Figure 6 that persists longer than Tf will cause OUT to be driven low. The chip will not accept a command to drive OUT high for a delay period of Td = 0.4RC Tb = Tp + 0.4RC. FRPLY will be open during this entire period. 5 UC1727 UC2727 UC3727 EXTERNAL BIPOLAR SUPPLIES If it is desired to drive an emitter grounded IGBT from external supplies, the configuration in Figure 8 should be used. COM should never be connected to ground. VCC must be ≥ 12V and VCC-VEE must be ≥ 23.5V. Figure 6. Desaturation Response ENABLE ENBL provides an alternate means of controlling the output. If ENBL is used as the primary input, B must be connected to VCC and A to VEE. ENBL can be driven by the output of an optoisolator from ENBL to COM as shown in Figure 7. If ENBL is not used, it should be connected to COM. Figure 8. Using External Supplies Figure 7. Using ENBL as Primary Input Figure 9. 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