3 3 2
SLUS471 – NOVEMBER 2000
Wide Supply Range ±20 V to ±100 V
Smooth Output Ramping Using Linear
PW PACKAGE
(TOP VIEW)
Current Amplifier
DC-To-DC Converters
Open-Drain Fault Output
ON Input Referenced to Positive Supply
(UCC3923)
ON Input referenced to Negative Supply
(possible alternative version)
Dual Insertion Detection Inputs
Electrostatic-Discharge Protection
– Human-Body-Model 2 kV
– Machine Model 200 V
–VIN
UVLO
SEQTIME
REF
DRAINSENS
OLVO
ON
ISENS
IRAMP
INSB
PACKAGE
(TOP VIEW)
D OR P PACKAGE
(TOP VIEW)
FAULT
FLTTIME
GATE
GND
20
19
18
17
16
15
14
13
12
11
1
8
2
7
3
6
4
5
1
2
3
4
5
6
7
FAULT
FLTTIME
GATE
–VIN
GND
ON
INSA
ISENS
INSB
IRAMP IRAMP
14
13
12
11
10
9
8
–VIN
UVLO
PG
REF
DRAINSENS
ON
ISENS
description
The UCC3923 family of devices are Hot-Swap Power Managers for use with negative power supplies. These
devices are optimized for use in systems with nominal –48-V supplies, but are fully functional over a supply
range of –20 V to –200 V. These devices can be used both on plug-in cards and on back-planes to limit inrush
current, control load turnon and turnoff, report faults, isolate faulty loads, and sequence downstream dc-to-dc
converters.
The UCC3923 offers the basic features of controlled turnon, load current ramping, and logic output of fault status
in a tiny 8-pin package. The UCC3924 adds undervoltage protection, two insertion detection pins, power-good
sensing, one output for downstream converter enabling, and a reference for cascoding, in a 14-pin package.
The UCC3925 has all of the previously noted features plus overvoltage protection and supply sequencing for
up to five downstream converters in a 20-pin package.
AVAILABLE OPTIONS
TA
–40C
40C to 85C
ENABLE
Active high
PACKAGED DEVICES†
TSSOP–8
TSSOP–14
TSSOP–20
UCC3923
UCC3924
UCC39235
Active low
UCC3926
UCC3927
UCC3928
† All packages are available left end taped and reeled. Add an R suffix to the device type (e.g.,
UCC3923PWPR) to order quantities of 2000 devices per reel.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
%(")+'-%)( )(!+(, *+) .-, %( -$! ")+'-%/! )+
!,%#( *$,! )" !/!&)*'!(- $+-!+%,-% - ( )-$!+
,*!%"%-%)(, +! !,%#( #)&, !1, (,-+.'!(-, +!,!+/!, -$! +%#$- -)
$(#! )+ %,)(-%(.! -$!,! *+) .-, 0%-$).- ()-%!
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
PRODUCT PREVIEW
1
2
3
4
5
6
7
8
9
10
PG1
PG2
PG3
PG4
PG5
FAULT
FLTTIMEGATE
GND
INSA
Undervoltage and Overvoltage Shutdown
Sequenced Open-Drain Outputs for Five
SLUS471 – NOVEMBER 2000
functional block diagram
LOAD
DRAINSENS
19
PG5
+
ON
18
4V
20
+
PG4
+
17
3V
1.4 V
GND
PG3
+
1
16
2V
INSA
+
+
2
PG2
+
15
1V
INSB
+
1.5 V
4V
PG1
3
+
UVLO
PRODUCT PREVIEW
14
0V
99 R
4
+
GATE
+
13
ISENS
+
OVLO
12
6
FAULT
R
REF
TIMER
5
5V
S
Q
R
Q
11
1.25 V
7
–VIN
8
9
IRAMP
FLTTIME
10
SEQTIME
UDG–00151
‡ 20-pin package shown. Pin numbers are for counting purposes only, Actual pin locations are dependent upon customer requirements and
precedence of other products.
DETAILED OPTION MATRIX
PIN NAME
DESCRIPTION
UVLO
Undervoltage input
UCC3923
OVLO
Overvoltage input
PGx
PG output(s)
1
5
1
5
REF
Reference output
X
X
X
X
INSA, INSB
Insert detect
X
X
X
X
DRAINSENS
Power good detection input
X
X
X
X
SEQTIME
Programming for downstream load sequencing
UCC3925
X
X
UCC3927
UCC3928
X
X
X
14–Pin TSSOP
X
X
X
X
X
POST OFFICE BOX 655303
X
X
20–Pin TSSOP
2
UCC3926
X
8–Pin TSSOP
Packages
ac ages
UCC3924
• DALLAS, TEXAS 75265
X
SLUS471 – NOVEMBER 2000
Terminal Functions
TERMINAL
NO.
UCC3923
UCC3926
UCC3924
UCC3927
UCC3925
UCC3928
I/O
DRAINSENS
–
10
16
I
Power good detection input
FAULT
1
1
6
O
Logic fault output
FLTTIME
2
2
7
I
Programming for fault timeout
GATE
3
3
8
O
Gate drive output
GND
4
4
9
I
Ground
INSA
–
5
10
I
Insertion detection input A
INSB
–
6
11
I
Insertion detection input B
IRAMP
5
7
12
I
Programming for current ramping
ISENS
6
8
13
I
Current sense input
ON
7
9
14
O
Logic command to turn on power to load
OVLO
–
–
15
I
Input overvoltage detection input
PG1
–
12
1
O
Enable for first downstream load
PG2
–
–
2
O
Enable for second downstream load
PG3
–
–
3
O
Enable for third downstream load
PG4
–
–
4
O
Enable for fourth downstream load
PG5
–
–
5
O
Enable for fifth downstream load
REF
–
11
17
O
Reference output
SEQTIME
–
–
18
I
Programming for downstream load sequencing
UVLO
–
13
19
I
Input undervoltage detection input
–VIN
8
14
20
I
Negative supply input
detailed description
power good detection input (UCC3924 and UCC3925 only)
DRAINSENS is an input that senses the voltage across the power FET. When the voltage on DRAINSENS is
less than 1V with respect to –VIN and IRAMP is greater than or equal to 5 V with respect to –VIN, then the power
FET is considered fully on and the PG outputs are allowed to begin sequencing the loads.
logic fault output (UCC3923, UCC3924, UCC3925)
FAULT is an open-drain, active-low driver that asserts when the fault latch is set. The UCC3923 UCC3924 and
UCC3925 controls the load inrush during starting by closed-loop regulation of load current. When the ON input
is low, IRAMP, FLTTIME, and SEQTIME are held low. When ON is asserted high, IRAMP is released and allows
CIRAMP to charge. Load current is limited to:
I
LOAD
0.01 V
R
IRAMP
SENSE
During this time, CFLTTIME charges. If CFLTTIME charges to 4 V before the power FET fully enhances, the fault
latch sets, the load is immediately turned off, and FAULT pulls low. The fault latch is cleared when ON is pulled
low.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
PRODUCT PREVIEW
DESCRIPTION
NAME
SLUS471 – NOVEMBER 2000
detailed description (continued)
programming for fault timeout
During the time when the power FET is regulating current to the load, FLTTIME is pulled high with 10 µA. When
the load current drops below the commanded maximum load current, FLTTIME is quickly pulled low. If FLTTIME
charges to 4 V before the power FET fully enhances, the fault latch sets and the load is immediately turned off.
gate drive output
When ON is low, GATE is held low. When ON is asserted high, IRAMP is released and allows CIRAMP to charge.
During this time, GATE rises, turning on the external power FET so that:
I
LOAD
0.01 VIRAMP VIN
R
SENSE
PRODUCT PREVIEW
IRAMP does not ramp higher than 5 V above –VIN, so load current is programmed to a maximum of
0.05/RSENSE. If the load is unable to accept the current, GATE rises up to 12 V above –VIN, fully enhancing
the power FET. If load current ever spikes above that maximum value, the current limiting amplifier reduces
GATE voltage to a level that maintains ILOAD at 0.05/RSENSE.
ground
GND is the ground input to the IC in negative supply systems. The ON input signal is measured with respect
to GND. All other signals are with respect to –VIN.
insertion detection
INSA and INSB are active-low inputs that must be asserted for the IC to drive the load. These inputs have
internal pullup current sources of 10 µA so they can be driven by open-drain logic. These inputs can also be
used as board insertion detection inputs. In this case, these inputs would be connected to corner pins of a
connector. The mating pins of the connector would be connected to –VIN. This would prevent operation before
both corners of the connector are mated.
current ramping
When ON is low, IRAMP is held low. When ON is asserted high, IRAMP is released and allows CIRAMP to charge.
During this time, GATE rises, turning on the external power FET so that:
I
LOAD
0.01 VIRAMP VIN
R
SENSE
IRAMP does not ramp higher than 5 V above –VIN, so load current is programmed to a maximum of
0.05/RSENSE.
current sensing
Load current is sensed by the voltage between ISENS and –VIN. A current sense resistor, RSENSE is
connected between ISENS and –VIN. Maximum load current is limited to:
I
LOAD
0.01 VIRAMP VIN
R
during current ramp and I
SENSE
when IRAMP reaches final value.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
LOAD
0.05
R
SENSE
SLUS471 – NOVEMBER 2000
detailed description (continued)
logic command to turn on power-to-load
Three logic inputs enable the load: INSA, INSB, and ON. To turn on the load, INSA and INSB must be lower
than a TTL threshold above –VIN and ON must be more than a TTL threshold above GND.
overvoltage/undervoltage lockout
In addition to the logic inputs INSA, INSB, and ON, two other inputs enable load current: OVLO and UVLO.
Specifically, OVLO must be less than 1.25 V with respect to –VIN and UVLO must be more than 1.25 V with
respect to –VIN to enable load current. These pins can be used as logic inputs or as precision overvoltage
shutdown and undervoltage lockout inputs by connecting these inputs to a voltage divider from GND to –VIN.
The IC has five outputs to enable downstream power converters or loads. These outputs are open-drain
active-low drivers. During power–up, all five outputs are high–impedance. When load current is ramped up to
maximum command and the output power FET has VDS < 1 V, CSEQTIME starts to charge and PG1 immediately
asserts low. When CSEQTIME charges up to 1 V, PG2 asserts low. When CSEQTIME charges up to 2 V, PG3
asserts low. When CSEQTIME charges up to 3 V, PG4 asserts low and when CSEQTIME charges up to 4 V, PG4
asserts low.
reference output
REF is a voltage reference output 5 V higher than –VIN. This output is enabled whenever –VIN to GND is
greater than 20 V. This reference can be used as a bias for cascode devices to buffer low-voltage logic outputs.
This reference should not be loaded with more than 50 µA.
programming for downstream load sequencing
These outputs turn on sequentially, with PG1 turning on first, PG2 second, etc. The delay from PG1 to PG2
is the time required to charge the capacitor from SEQTIME to –VIN by 1 V. SEQTIME is pulled high through
a 10-µA current source, so the delay between output enables is C/10 µA.
negative supply input
–VIN is the negative supply input to the IC. All signals are measured with respect to –VIN except ON. In positive
supply systems, –VIN is the ground input to the IC.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
PRODUCT PREVIEW
enable downstream power converter
SLUS471 – NOVEMBER 2000
absolute maximum ratings over operating free–air temperature range (unless otherwise noted)†
Input voltage range, all pins except GND, ON, DRAINSENS . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
Input voltage range, GND, ON, DRAINSENS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 80 V
Output voltage range, PG1, PG2, PG3, PG4, PG5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
Output voltage range, FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 65 V
Continuous output current, PG1, PG2, PG3, PG4, PG5, FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40C to 125C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65C to 150C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260C
ESD Protection: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HBM 2 kV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDM 1 kV
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
‡ All voltages are with respect to –VIN unless otherwise stated.
DISSIPATION RATING TABLE
TA ≤ 25C
POWER RATING
DERATING FACTOR
ABOVE TA = 25C
TA = 85C
POWER RATING
TSSOP–8
800 mW
10 mW/C
200 mW
TSSOP–14
800 mW
10 mW/C
200 mW
TSSOP–20
800 mW
10 mW/C
200 mW
PRODUCT PREVIEW
PACKAGE
recommended operating conditions
Input voltage (–VIN to GND)
MIN
MAX
UNIT
–20
–80
V
Input voltage (FLTTIME, INSA, INSB, IRAM, OVLO, SEQTIME, UVLO to –VIN)
0
7
V
Input voltage (ISENS to –VIN)
0
0.2
V
Input voltage (DRAINSENS to –VIN)
0
80
V
Input voltage (ON to GND)
0
80
V
2
mA
–40
125
C
MIN
MAX
UNIT
Output current (PG1, PG2, PG3, PG4, PG5, FAULT, REF)
Operating virtual junction temperature, TJ
electrostatic discharge protection
Human body model
2
kV
Charged device model
1
kV
0.2
kV
Machine model
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLUS471 – NOVEMBER 2000
electrical characteristics over recommended operating junction temperature range,
–VIN to GND = –48 V, ON to GND = 2.8 V, INSA = INSB = –VIN, ISENS = –VIN, UVLO = 2.5 V, OVLO
= VIN, all outputs unloaded (unless otherwise noted)
power fet drive
PARAMETER
TEST CONDITIONS (See Note 1)
GATE output voltage
VISENS = 0 V
GATE pulldown current in fault
VISENS = 0.1 V
ISENS input current
ON = high,
0 V < VISENS < 0.1 V
MIN
TYP
10
12
100
250
MAX
UNIT
14
V
mA
–1
1
µA
timers
TEST CONDITIONS
MIN
0 V < VIRAMP < 5 V
TYP
MAX
UNIT
µA
IRAMP pullup current during start
ON = high,
IRAMP low voltage
ON = low
10
IRAMP to ISENS gain
ON = high,
0 V < VIRAMP < 5 V
IRAMP offset voltage referred to ISENS
ON = high,
VIRAMP = 0 V
IRAMP clamp voltage referred to ISENS
ON = high
FLTTIME pullup current during current
limit
ON = high,
FLTTIME low voltage
ON = low
FLTTIME fault threshold voltage
ON = high,
FLTTIME discharge current
ON = low
SEQTIME pullup current
ON = high,
SEQTIME low-level input voltage
ON = low
10
mV
SEQTIME to PG2 threshold voltage
ON = high,
VIRAMP = 5 V, VISENS = 0 V
0.9
1.0
1.1
V
SEQTIME to PG3 threshold voltage
ON = high,
VIRAMP = 5 V, VISENS = 0 V
1.9
2.0
2.1
V
SEQTIME to PG4 threshold voltage
ON = high,
VIRAMP = 5 V, VISENS = 0 V
2.9
3.0
3.1
V
SEQTIME to PG5 threshold voltage
ON = high,
VIRAMP = 5 V, VISENS = 0 V
3.9
4.0
4.1
V
SEQTIME discharge current
ON = low
2
0.01
V/V
–2
45
Fault latch not set
50
2
mV
55
mV
µA
10
10
VISENS = 0.1 V
3.75
4.00
4.25
10
VIRAMP = 5 V, VISENS = 0 V
mV
PRODUCT PREVIEW
PARAMETER
mV
V
mA
µA
10
10
mA
power good
PARAMETER
TEST CONDITIONS
PG1, PG2, PG3, PG4, PG5 on
resistance
ON = high,
VSEQTIME = 5 V,
VISENS = 0 V
DRAINSENS threshold voltage
To PG1 rising
DRAINSENS pullup current
DRAINSENS = –VIN
MIN
TYP
MAX
100
0.85
1.00
1.15
UNIT
Ω
V
µA
10
fault output
PARAMETER
FAULT on resistance
TEST CONDITIONS
ON = high,
VISENS = 0.1 V,
VFLTTIME = 5 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
TYP
MAX
100
UNIT
Ω
7
SLUS471 – NOVEMBER 2000
electrical characteristics over recommended operating junction temperature range,
–VIN to GND = –48 V, ON to GND = 2.8 V, INSA = INSB = –VIN, ISENS = –VIN, UVLO = 2.5 V, OVLO
= VIN, all outputs unloaded (unless otherwise noted) (continued)
voltage reference output
PARAMETER
TEST CONDITIONS
–50 µA < IREF < 0 µA
REF voltage
MIN
4.9
TYP
5.0
MAX
UNIT
5.1
V
undervoltage/overvoltage lockout
PRODUCT PREVIEW
PARAMETER
TEST CONDITIONS
UVLO falling threshold
ON = high,
to GATE falling
UVLO hysteresis
ON = high,
to GATE rising
UVLO input current
VUVLO = 2.5 V
OVLO rising threshold
ON = high,
to GATE falling
OVLO hysteresis
ON = high,
to GATE rising
OVLO input current
VOVLO = 2.5 V
MIN
1.20
TYP
1.25
MAX
UNIT
1.30
25
1
µA
1.30
V
–1
1.20
1.25
V
mV
25
mV
–1
1
µA
supply and control inputs
PARAMETER
TEST CONDITIONS
MIN
–VIN input current
8
TYP
MAX
µA
250
INSA, INSB threshold voltage
ON = high,
INSA, INSB pullup current
VINSA = VINSB = –VIN
ON threshold voltage with respect to
GND
To GATE rising
ON input current
VON – VGND = 5 V
POST OFFICE BOX 655303
to GATE rising
• DALLAS, TEXAS 75265
1.0
1.4
1.8
1.4
10
V
µA
10
1.0
UNIT
1.8
V
µA
SLUS471 – NOVEMBER 2000
TYPICAL CHARACTERISTICS
TYPICAL TURNON CYCLE
TURNON INTO EXCESSIVELY HEAVY LOAD
–VIN
–VIN
ON
ON
IRAMP
IRAMP
GATE
GATE
ISENS
ISENS
FLTTIME
FLTTIME
SEQTIME
FAULT
PRODUCT PREVIEW
ENA1
ENA2
ENA3
ENA4
ENA5
Figure 1
Figure 2
APPLICATION INFORMATION
ESD Protection
All UCC3923, UCC3924, and UCC3925 terminals incorporated ESD-protection circuitry designed to withstand
a 2-kV human-body-model discharge as defined in MIL–STD–883C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
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Copyright 2000, Texas Instruments Incorporated