DRF1202 500V, 50A, 30MHz MOSFET Driver Hybrid The DRF1202 hybrid includes a high power gate driver and the power MOSFET. The driver output can be configured as Inverting and NonInverting. It was designed to provide the system designer increased flexibility and lowered cost over a non-integrated solution. D IN DRIVER 50A MOSFET S TYPICAL APPLICATIONS FEATURES • Switching Frequency: DC TO 30MHz • Switching Speed 3-4ns • Class C, D and E RF Generators • Low Pulse Width Distortion • BVds = 500V • Switch Mode Power Amplifiers • Single Power Supply • Ids = 50A avg. • Pulse Generators • Rds(on) ≤ .25 Ohm • Ultrasound Transducer Drivers • PD = 1180W • Acoustic Optical Modulators • 1V CMOS Schmitt Trigger Input 1V Hysteresis • Inverting Non-Inverting Select • RoHS Compliant Driver Absolute Maximum Ratings Symbol VDD Parameter Ratings Supply Voltage Unit 18 V IN, FN Input Single Voltages -.7 to +5.5 IO PK Output Current Peak 8 A TJMAX Operating and Storage Temperature 175 °C Driver Specifications VDD IN Parameter Min Typ Max Supply Voltage 8 15 18 Input Voltage 3 5.5 Unit V IN(R) Input Voltage Rising Edge 3 IN(F) Input Voltage Falling Edge 3 IDDQ Quiescent Current 2 mA Output Current 8 A IO Coss Output Capacitance Ciss Input Capacitance 3 RIN Input Parallel Resistance 1 ns 2500 pF mΩ VT(ON) Input, Low to High Out 0.8 1.1 VT(OFF) Input, High to Low Out 1.9 2.2 TDLY Time Delay (throughput) 38 tr Rise Time 5 tf Fall Time 5 TD Prop. Delay 35 Microsemi Website - http://www.microsemi.com V ns ns 050-4973 Rev B 4-2009 Symbol MOSFET Absolute Maximum Ratings Symbol BVDSS ID RDS(on) DRF1202 Parameter Min Drain Source Voltage 500 Typ Max V Continuous Drain Current THS = 25°C 50 Drain-Source On State Resistance Unit 0.25 A Ω Dynamic Characteristics Symbol Parameter Min Typ Ciss Input Capacitance 2000 Coss Output Capacitance 165 Crss Reverse Transfer Capacitance 75 Max Unit pF Thermal Characteristics Symbol Parameter Ratings RθJC Thermal Resistance Junction to Case 0.10 RθJHS Thermal Resistance Junction to Heat Sink 0.27 TJSTG Storage Temperature PD PDC -55 to 150 Maximum Power Dissipation @ TSINK = 25°C 1180 Total Power Dissipation @ TC = 25°C 3100 Unit °C/W °C W Microsemi reserves the right to change, without notice, the specifications and information contained herein. 050-4973 Rev B 4-2009 Figure 1, DRF1202 Simplified Circuit Diagram The Simplified DRF1202 Circuit Diagram is illustrated above. By including the driver high speed by-pass capacitor (C1), their contribution to the internal parasitic loop inductance of the driver output is greatly reduced. This, coupled with the tight geometry of the hybrid, allows optimal gate drive to the MOSFET. This low parasitic approach, coupled with the Schmitt trigger input (IN), Kelvin signal ground (SG) and the AntiRing Function, provide improved stability and control in Kilowatt to Multi-Kilowatt, high Frequency applications. The IN pin is the input for the control signal and is applied to a Schmitt Trigger. Both the FN and IN pins are referenced to Kelvin ground (SG.) The signal is then applied to the intermediate drivers and level shifters; this section contains proprietary circuitry designed specifically for the ring abatement. The power drivers provide high current to the gate of the MOSFETS. DRF1202 The Function (FN, pin 3) is the invert or non-invert select Pin, it is Internally held high. Truth Table *Referenced to SG FN (pin 3)* IN (pin 4)* MOSFET HIGH HIGH ON HIGH LOW OFF LOW HIGH OFF LOW LOW ON Figure 2, DRF1202 Test Circuit The Test Circuit illustrated above was used to evaluate the DRF1202 (available as an evaluation Board DRF12XX / EVALSW.) The input control signal is applied to the DRF1202 via IN(4) and SG(5) pins using RG188. This provides excellent noise immunity and control of the signal ground currents. Microsemi’s products are covered by one or more of U.S. patents 4,895,810 5,045,903 5,089,434 5,182,234 5,019,522 5,262,336 6,503,786 5,256,583 4,748,103 5,283,202 5,231,474 5,434,095 5,528,058 6,939,743 and foreign patents. US and Foreign patents pending. All Rights Reserved. 050-4973 Rev B 4-2009 The +VDD inputs (2,6) are by-passed (C1,C2, C4-C9), this is in addition to the internal by-passing mentioned previously. The capacitors used for this function must be capable of supporting the RMS currents and frequency of the gate load. A 50Ω (R4) load is used to evaluate the output performance of the DRF1202. DRF1202 Pin Assignments Pin 1 Ground Pin 2 U1 +Vdd Pin 3 FN Pin 4 U1 IN Pin 5 U1 SG Pin 6 U1 +Vdd Pin 7 Ground Pin 8 Source Pin 9 Drain Pin 10 Source 0.300 1.500 GAPS - 0.090" , 2 PLCS 0.275 0.200 0.370 0.200 10 9 8 0.038 0.275 0.125 R0.150 4 PLCS 0.125 0.750 1.000 0.520 0.0045 Ø0.125 4 PLCS 0.250 0.250 1 0.275 LARGE LEADS - 0.200", 2 PLCS 2 3 4 5 6 7 GAPS - 0.050", 6 PLCS SMALL LEADS - 0.040", 3 PLCS MEDIUM LEADS - 0.065", 2 PLCS All dimensions are ± .005 050-4973 Rev B 4-2009 0.300 Figure 3, DRF1202 Mechanical Outline .005" TYP. HALF HARD COPPER GOLD PLATED