DA6116.001 27 February, 2009 MAS6116 Stereo Digital Volume Control • • • • Signal Voltage up to ± 18V Two Independent Channels Use of Differential DACs Possible Serial Control Registers DESCRIPTION MAS6116 is a stereo volume control for audio systems, which require high output voltages (AC3). It has serial interface, which controls two audio channels. Simple serial interface allows microcontroller to control many MAS6116 chips on the same PCB board. “Clicking” between gain changes is eliminated by changing gain only when zero crossing has been detected in the input signal. FEATURES • • • • • • • • • • • • • • Signal Voltage up to ± 18V Two Independent Channels Use of Differential DACs Possible Serial Control Registers Zero Cross Detection for Gain Changes Gain Range +15.5db…-111.5dB 0.5 dB Gain Step Size Mute Pin Power On/Off Transient Suppression Signal Peak Level Comparator with Adjustable Reference Independent Writing to Both Channels Instant Gain Change Function for Fast Gain Switching XMUTE Using the Zero Cross and Timeout Functions Write Operation Status Register MAS6116 also features a peak detection circuitry that allows easy monitoring of the output signal. MAS6116 has also a set of “instant gain change” instructions that allow fast gain switching. The use of external operational amplifier provides flexibility for the operating voltage, signal swing, noise floor and cost optimization. APPLICATION • • High End Audio Systems Multi-channel Audio Systems 1 (18) DA6116.001 27 February, 2009 BLOCK DIAGRAM RFO RIN R2 R1 RMO R3 VRIN ROUT RGND VROUT PEAK DETECTOR ZERO CROSSING DATA CCLK XCS XMUTE 8 DAC CONTROL ZERO CROSSING PEAK DETECTOR LFO LIN R2 VLIN LGND AGND AVCC DVCC DGND R1 LMO R3 LOUT MAS6116 VLOUT 2 (18) DA6116.001 27 February, 2009 PIN CONFIGURATIONS SO16 AVCC LMO LFO LIN LGND XCS DVCC XMUTE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 AGND RMO RFO RIN RGND DGND CCLK DATA PIN DESCRIPTION Pin Name Pin QFN 4x5 23 24 1 Type AVCC LMO LFO* Pin SO16 1 2 3 LIN* LGND XCS DVCC XMUTE DATA CCLK DGND RGND RIN* RFO* 4 5 6 7 8 9 10 11 12 13 14 3 4 7 8 9 11 12 13 16 17 19 AI AI DI P DI DIO DI G AI AI AI RMO AGND 15 16 20 21 AI G P AI AI Function Power Supply, for Analog External Amplifier Negative Input (Left) Feedback Signal from External Amplifier Output (Left) Input, Left Channel Signal Ground, Left Channel Chip Select Input of Serial Interface Power Supply, for Digital Mute Input Data Input and Output of Serial Interface, Tristate Clock Input of Serial Interface Ground for Digital Signal Ground, Right Channel Input, Right Channel Feedback Signal from External Amplifier Output (Right) External Amplifier Negative Input (Right) Ground for Analog *) Note: These pins have limited ESD protection. See Absolute Maximum Ratings on page 9 for further details. 3 (18) DA6116.001 27 February, 2009 GENERAL DESCRIPTION Main features MAS6116 is a stereo digital volume control designed for audio systems. The levels of the left and right analog channels are set by the serial interface. Both channels can be programmed independently. The channel gains can be programmed from -111.5 dB to +15.5 dB with 0.5 dB resolution. The code for -112 dB (00HEX) activates mute for maximum attenuation. MAS6116 operates from single +5V supply and accepts analog input signal levels up to ±18V. MAS6116 has a zero cross detect function that changes the channel gain only when a zero crossing has been detected in the input signal. This eliminates clicking sounds from the output signal when the gain is changed. The zero cross detection circuit is also equipped with a timeout function to make sure the gain value is updated even when there is no input signal. Channel gains can also be changed instantly without using the zero cross detect function. This can be done with dedicated instant gain change commands specified in Register Description on page 7. Using this feature to change channel gains in large increments is not recommended because it may cause large transients in the output signal. See chapter Changing the gain of the channels and chapter Write operation status register for further details. The XMUTE pin in MAS6116 always uses the zero cross detection and timeout functions when entering to or returning from the MUTE state. This prevents fast transients from occurring in the output signal. Serial interface Control information is written into or read back from the internal register via the serial control port. Serial control port consists of a bi-directional pin for data (DATA), chip select pin (XCS) and control clock (CCLK) and supports the serial communication protocol. All control instructions require two bytes of data. To shift the data in CCLK must be pulsed 16 times when XCS is low. The data is shifted into the serial input register on the rising edges of CCLK pulses. The first 8 bits contain address information. The second byte contains the control word. XCS must return to high after the second byte. That is, after the 16th CCLK XCS must be returned to high. See chapter Serial interface timing diagram on page 12. The same process takes place for reading the information. XCS will remain low for next 16 CCLK pulses. The data is shifted out on the falling edges of CCLK. When XCS is high, the DATA pin is in high impedance state, which enables DATA pins of other devices to be connected together. On the PCB board the same DATA and CCLK lines can be routed to every MAS6116 chip. If the XCS-pin is not active (low), DATA pin of that chip is in high-impedance state. This allows using a simple PCB board for multichannel audio systems. 4 (18) DA6116.001 27 February, 2009 GENERAL DESCRIPTION Operating modes When power is first applied, power-on reset initializes control registers and sets MAS6116 into mute state, ignoring the state of the XMUTE pin. The activation of the device requires that XMUTE pin is high and a control byte with a greater than the default value (00HEX) is written in the gain register. It is possible to return to the mute state either by setting XMUTE pin low or writing zero (00HEX) to the gain register. Setting the XMUTE pin low will mute both channels. Setting the XMUTE pin back high will return the channels to previously written gain values. The zero cross detector function is used when entering and returning from the mute state to prevent large transients in the output signal (see chapter Changing the gain of the channels). The device has a special test mode register, which is used only for internal testing of the device. It is strongly recommended not to change the default value (00HEX) of the test register during normal operation. For device testing the XMUTE pin is bi-directional. When the test register bit 1 is set to high, XMUTE pin is in output mode. In the test mode internal signals can be directed to the XMUTE pin. Note: In the test mode both analog outputs are in mute state and the device will not allow new gain values to be written in the gain registers. An exception to this is the force latch command specified in table Test Register CR5 Description, which can be used to instantly change the gain of both channels. This function is intended to be used in the test mode only, and it is recommended to use the commands specified in Register Description to instantly change the channel gains. Changing the gain of the channels When a new gain value is written to the gain register the device will activate the zero crossing detection and delay generator for the selected channel. MAS6116 will wait until a rising edge of the input signal is detected to change the gain value. This is done to ensure that no audible clicks are produced to the output signal during the gain change operation. The zero cross detection circuit has also a timeout delay generator that will force the gain change. The delay generator generates a typical delay of 22 ms. If a new gain value is written before the previous write operation has finished, the previously written value will be overwritten and will not be set to the output. If it is desired that each gain value is set to the output, it is recommended to read the status bit from the write operation status register (CR6) or wait for at least 30 ms before the next gain change instruction. Both channels can be programmed independently with separate commands. In this case the gain values will be set to the output in the order of writing. Both channels can also be programmed to the same value by writing only one instruction (see the Register Description on page 7). Note: Due to the input signal dependency of the zero cross detection circuits the order of the gain changes may differ from the order of writing to the registers if the input signals to the channels are different. This applies to all instructions that use the zero cross detection and timeout functions, i.e. instructions that are not labeled as “instant” in the register description. The new gain value can be set instantly to the output by using the instant gain change function. By using this command function the gain is set to the output instantly after the write operation has finished, without waiting a zero cross to occur in the input signal or a delay to pass. The gains can be set independently to both channels using different commands, or both channels can be set to the same gain value by using a single command. Using the instant gain change function to change the gain value in larger than 0.5 dB steps may produce audible clicks to the output signal. 5 (18) DA6116.001 27 February, 2009 GENERAL DESCRIPTION Peak level detection MAS6116 has a 8-bit digital-to-analog converter (DAC) used to monitor the peak level of the output signal. The reference value is programmed using the serial interface and the same reference value is used for both channels. The reference value V REF can be calculated using the following formula. VREF = (0.0036 + 0.0145 · CODE) · AVCC where CODE is the decimal value of the control byte (0...255) and AVCC is the analog supply voltage of the MAS6116 device. With nominal analog supply voltage of 5V the reference value is VREF = 18mV + 72.5mV · CODE When a positive peak signal level at the output exceeds the V REF value, bits 0 and 1 of the status register are set (see register description). When set, the register contents will remain high until the value of the status register has been read. Write operation status register MAS6116 features a status register that can be used to determine if the channel registers are ready to accept new gain values. The status register bits 0 and 1 are set high at the start of a gain write operation, and are set back low when the new gain value has been set to the output. This happens when a positive zero crossing is detected in the input signal or the timeout delay has passed. It is allowed to write a new gain value to a channel that is busy (i.e. waiting for a zero cross in the input signal). The new value will overwrite the previous one and the timeout delay will be reset. This means that the previously written gain value will not be set to the channel gain registers. To prevent this from happening it is recommended to read the write operation status register prior to setting a new gain value to determine if the write operation can be safely executed. 6 (18) DA6116.001 27 February, 2009 REGISTER DESCRIPTION Register Write Operation Status CR6 Address Byte 7 X 6 1 1 5 0 0 4 1 1 3 0 1 2 R R Data Byte 1 X X 0 X X msb…lsb Output code 00000000 00000001 00000010 00000011 Output code 00000000 00000001 00000010 00000011 Input code 11111111 11111110 11111101 • • 00000010 00000001 00000000 Input code 11111111 11111110 11111101 • • 11100000 00000010 00000001 00000000 Input code 11111111 11111110 11111101 • • 11100000 00000010 00000001 00000000 Function Both channels ready Right channel busy Left channel busy Both channels busy Peak Detector Status CR4 X Peak Detector Reference CR3 X 1 1 0 0 R/W X X Left Channel Gain CR2 X 1 1 0 1 R/W X X Right Channel Gain CR1 X 1 1 1 0 R/W X X Test Mode, CR5 Normal Write, Both Instant Write, Left (CR2) Instant Write, Right (CR1) Instant Write, Both X X X X 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 0 R/W W W W X X X X X X X X No overload Right overload Left overload Both overload DAC output, Note 1. VREF(255) VREF(254) VREF(253) • • VREF(2) VREF(1) VREF(0) Gain dB +15.5 +15.0 +14.5 • • 0.0 -111.0 -111.5 Mute Gain dB +15.5 +15.0 +14.5 • • 0.0 -111.0 -111.5 Mute Reserved Write to both gain registers Instant gain set to left channel Instant gain set to right channel X 0 1 1 1 W X X Instant gain set to both channels Note 1. Reference voltage is calculated from VREF = (0.0036 + 0.0145 • CODE) • AVCC Address byte bits: • Bit 2 is read/write bit (1=read, 0=write). • Bits marked as X are don’t care bits. • The instant write commands write values to CR1 and CR2 registers for right and left channels respectively. These values can be read by using the specified read commands for CR1 and CR2 registers. 7 (18) DA6116.001 27 February, 2009 Data byte bits: • All registers are set to their default values 00HEX except CR3 which is set to FFHEX during power-on reset. • Default value for all bits is zero (00HEX). TEST REGISTER CR5 DESCRIPTION Note: Test register is intended for internal testing of the device only and not supposed to be used in normal operation. It is strongly recommended not to change initial test register value from the default (00HEX). The XMUTE pin is in output mode when bit 1 in the test register CR5 is set. Bits 2, 3 and 4 select the internal signal to be routed to the XMUTE pin in the test mode. Condition Data Byte bits 7 0 0 0 0 0 0 0 0 0 0 XMUTE=in Test, XMUTE=in Test, XMUTE=out Test, XMUTE=out Test, XMUTE=out Test, XMUTE=out Test, XMUTE=out Test, XMUTE=out Test, XMUTE=out Test, XMUTE=out 6 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 1 1 1 1 3 0 0 0 0 1 1 0 0 1 1 Function 2 0 0 0 1 0 1 0 1 0 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 Normal operation Force latch, note 2 Left delay generator Left peak detector Left zero crossing Left gain set enable Right delay generator Right peak detector Right zero crossing Right gain set enable Note 2. Forces the new gain value to be set without waiting for a zero crossing to occur in the input signal or the timeout delay to pass. When force latch is used, both channels are latched with the same gain value. POWER-ON RESET MAS6116 has a Power-On Reset circuit (POR) that ensures that the circuit is set to a known state when power is applied. The device can be activated as described in chapter Operating modes after the POR delay has passed. In addition MAS6116 has a supply voltage monitoring circuit, that monitors the digital supply voltage (DVCC) level. If the digital supply voltage drops below the specified level, the circuit is set to RESET state. The voltage monitoring circuit is functional only when sufficient analog supply voltage (AVCC) is present. Parameter Symbol Conditions Min POR delay TPOR From DVCC=5V to POR rising edge 450 µs Monitored DVCC level AVCC level to enable DVCC monitoring Vmon Measured from DGND 2.8 V VAVCC Measured from AGND 2.5 Typ Max Unit V 8 (18) DA6116.001 27 February, 2009 ABSOLUTE MAXIMUM RATINGS All voltages with respect to ground. Parameter Symbol Signal Voltage Positive Supply Voltage All other pins Storage Temperature Operating Temperature ESD (HBM) pins 3, 4, 13 and 14 ESD (HBM) all other pins Conditions Min Max Unit Note 3. -20 -0.5 -0.3 +20 +6.0 AVCC +0.3 +125 +95 V V V RIN, RFO, LIN, LFO AVCC, DVCC DATA, CLK, XCS, XMUTE TS TA -55 -40 200 2000 o C C V V o Note 3. Pin voltage must not exceed +6V under any circumstances. Stresses beyond those listed may cause permanent damage to the device. The device may not operate under these conditions, but it will not be destroyed. RECOMMENDED OPERATION CONDITIONS (AVCC=+5.0 V, AGND=0 V, TA=+25oC unless otherwise noted) Parameter Symbol Signal Voltage Conditions Min Typ Positive Supply Voltage RIN, RFO, LIN, LFO AVCC,DVCC Negative Supply Voltage AGND,DGND 0 Signal Grounds LGND,RGND 0 Operating Temperature TA -18 4.5 5 Max Unit +18 V 5.5 V V V -30 +25 +85 o C ANALOG CHARACTERISTICS ◆ Analog Inputs/Outputs (AVCC=+5.0 V, AGND=0 V, TA=+25oC unless otherwise noted) Parameter Symbol Conditions Min Typ Max Unit Input impedance RIN Average impedance, note 4 7 10 13 Input capacitance CIN For any gain value 2 kΩ pF Input offset voltage VIH External OpAmp, Gain = 15.5 dB Note 5 From AVCC From AGND From AVCC 0.23 mV Supply current Supply current Power supply 1 rejection ratio IVCC IGND PSRR 0.6 2.2 80 mA mA dB Note 4. Average input impedance is calculated as an average of the impedance measured for all gain values. Note 5. Output offset voltage depends on external opamp and selected gain. Low input offset voltage and input bias current opamp is recommended to be used for minimum output offset. 9 (18) DA6116.001 27 February, 2009 ANALOG CHARACTERISTICS ◆ Gain Control (AVCC=+5.0 V, AGND=0 V, TA=+25oC unless otherwise noted) Parameter Symbol Gain range G Step size D Absolute gain Typ -111.5 Max Unit +15.5 dB 0.5 dB Absolute gain value with setting G=255 +15 +15.5 +16 dB DE Relative to GABS, note 6 -0.5 0 0.5 dB ME Between channels, note 7 -0.2 0 0.2 dB MATT AC measurement 96 1 Mute attenuation Min GABS Gain step error Gain match error Conditions dB Note 6. Gain value for each gain setting is measured as AC measurement relative to GABS assuming a gain step size of 0.5dB. Gain settings 65…255 are tested in production. Gain error for lower gain settings is guaranteed by design only. Note 7. Gain mismatch is tested in production for gain settings 90…255. Mismatch for lower gain settings is guaranteed by design only. ◆ Audio Performance (AVCC=+5.0 V, AGND=0 V, TA=+25oC unless otherwise noted) Parameter Noise Symbol N rd 3rd harmonic component Total harmonic distortion plus noise Signal to noise ratio 3 HD Crosstalk CR THD SNR Conditions Vin = 0V, Vout with OP2277, A-weighting gain=0dB gain=-40dB gain=-60dB gain=mute Vin=5Vrms, gain=0dB, fin=800Hz Vin=5Vrms, gain=0dB, fin=800Hz, 10 harmonics Vin=5Vrms, gain=0dB, fin=800Hz, non-weighted Between channels, Vin = 5Vrms, gain= 0dB, fin = 1kHz Min Typ Max 11 3.7 2.2 1.8 Unit µVrms -72 -75 dB -68 dB 100 dB -110 dB ◆ Peak Level Detection (AVCC=+5.0 V, AGND=0 V, TA=+25oC unless otherwise noted) Parameter Peak detector minimum level Peak detector maximum level Peak detector step size Symbol Conditions Min Typ Max Unit VMIN PD reference = 0 0 18 500 mV VMAX PD reference = 255 18 18.5 20 V 60 72.5 90 mV Min Typ Max Unit 15 22 30 ms VSTEP ◆ Zero Cross Detection Timeout (AVCC=+5.0 V, AGND=0 V, TA=+25oC unless otherwise noted) Parameter Zero cross detection timeout Symbol TDEL Conditions 10 (18) DA6116.001 27 February, 2009 DIGITAL CHARACTERISTICS ◆ Digital Inputs/Outputs (AVCC=+5.0 V, AGND=0 V, TA=+25oC unless otherwise noted) Parameter Symbol Conditions Input low voltage VIL Input high voltage VIH Output low voltage VOL Output high voltage VOH All digital inputs, DC All digital inputs, DC All digital outputs, IL=2mA All digital outputs, IH=-2mA Min Typ Max Unit 0.3* DVCC V 0.7* DVCC V 0.3* DVCC 0.7* DVCC V V ◆ Serial Interface Timing (AVCC=+5.0 V, AGND=0 V, TA=+25oC unless otherwise noted) Parameter Symbol Frequency of CCLK FCCLK Period of CCLK high TWHC Measured from VIH to VIH 50 ns Period of CCLK low TWLC Measured from VIL to VIL 50 ns Rise time of CCLK TRC Measured from VIL to VIH 100 ns Fall time of CCLK TFC Measured from VIH to VIL 100 ns Hold time, CCLK high to XCS low Setup time, XCS low to CCLK high Setup time, valid CI to CCLK high Hold time, CCLK high to invalid CI Delay time, CCLK low to valid CI th Delay time, XCS high or 8 CCLK low to invalid CI th Hold time, 16 CCLK high to XCS high Setup time, XCS high to CCLK high Conditions Min Typ Max Unit 10 MHz THCHS 20 ns TSSLCH 100 ns TSDCH 100 ns THCHD 100 ns TDCLD Load=100pF TDSZ Load=3.3kΩ 50 50 ns 150 ns THLCHS 200 ns TSSHCH 200 ns 11 (18) DA6116.001 27 February, 2009 SERIAL INTERFACE TIMING TWHC TWLC CCLK 1 THCSH 2 3 4 5 6 TRC 7 8 9 10 11 12 TFC 13 14 15 16 TSSHCH THLCHS TSSLCH XCS THCHD TSDCH DATA (IN) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 TDCLD DATA (OUT) 7 ADDRESS BYTE 6 5 4 TDSZ 3 2 1 0 DATA BYTE 12 (18) DA6116.001 27 February, 2009 APPLICATION INFORMATION Application Note 1 – Typical application Connect signal ground and opamp +input together on PCB RF LIN AUDIO SOURCE RIN +18V LFO + LMO LGND LEFT CHANNEL -18V RF RIN AUDIO SOURCE RGND RIN +18V RFO + RMO RIGHT CHANNEL -18V MAS6116 +5VDC MICROCONTROLLER XCS DATA CCLK XMUTE AVCC DVCC + 220nF 10uF AGND DGND Application Note 2 - Configuration for balanced output DAC (only one channel shown) RFO RIN +18V RMO - 2k RGND + 2k +18V -18V - MAS6116 + +18V -18V + LGND LFO LIN LMO 2k -18V 2k 13 (18) DA6116.001 27 February, 2009 APPLICATION INFORMATION Application Note 3 – Single supply voltage usage Single supply voltage circuit below is based on signal AC coupling and biasing output opamp in the middle point of supply voltages. Note that only right channel circuit is presented. The left channel circuit would be exactly the same. The component values have been chosen to limit overall lower corner frequency to about 10 Hz. AVCC DVCC + 5V supply 10µF RFO MAS6116 (Right Channel) IN 1MΩ 1MΩ 10µF + 10µF RIN RM 100nF AC RGND LGND OUT (inverted) 10kΩ 1MΩ DGND AGND Application Note 4 – Lower supply voltage MCU communication example 1 If the serial control interface is driven from MCU which operates from lower supply voltage than MAS6116 which is using higher 5V voltage supply there is level shifting needed for keeping the digital signal levels proper in the communication. The bi-directional DATA line requires additionally level shifting in both directions. Figure below shows an example of serial interface level shifting between 3V and 5V voltage supplies. In this example level shifters with output enable function are used. The output enable function is used to disable level shifter output when data direction changes in the bi-directional data line of MAS6116. +3V VDD +5V +5V DVDD AVDD +3V GPIO MAS6116 MCU +5V GPIO GPIO OE DATA +5V CLK GPIO +5V GPIO XCS +5V GPIO XMUTE 14 (18) DA6116.001 27 February, 2009 APPLICATION INFORMATION Application Note 5 – Lower supply voltage MCU communication example 2 Second example of communication with lower supply voltage MCU is shown in the figure below. There are open drain buffers used in the level shifting between 3V and 5V signal levels. In this example the DATA signal line communication is bi-directional also on the MCU side. +3V +3V 4k7 VDD +5V +5V DVDD AVDD +5V 4k7 74LVC1G07 +3V MCU 4k7 74LVC1G07 GPIO +3V MAS6116 +5V 4k7 DATA +5V 4k7 CLK 74LVC1G07 GPIO +3V +5V 4k7 74LVC1G07 GPIO +3V XCS +5V 4k7 74LVC1G07 XMUTE GPIO 15 (18) DA6116.001 27 February, 2009 SO-16 PACKAGE OUTLINE 16 LEAD SO OUTLINE (300 MIL BODY) 1.27 5° TYP. TYP. 5° TYP. 0.86 TYP . 10.10 10.50 PIN 1 7.40 7.60 10.00 10.65 5° TYP. SEATING PLANE 0.10 0.30 0.25 RAD. MIN. 0-0.13 RAD. 2.36 2.64 5° TYP. 0.36 0.48 0.94 1.12 5°TYP 0.33 x 45° ALL MEASUREMENTS IN mm All dimensions are in accordance with JEDEC standard MS-013. SOLDERING INFORMATION ◆ For Lead-Free / Green QFN 4mm x 5mm Resistance to Soldering Heat Maximum Temperature Maximum Number of Reflow Cycles Reflow profile Lead Finish According to RSH test IEC 68-2-58/20 260°C 3 Thermal profile parameters stated in IPC/JEDEC J-STD-020 should not be exceeded. http://www.jedec.org Solder plate 7.62 - 25.4 µm, material Matte Tin 16 (18) DA6116.001 27 February, 2009 REEL SPECIFICATIONS W2 A D Tape Slot for Tape Start C N B W1 1000 Components on Each Reel Reel Material: Conductive, Plastic Antistatic or Static Dissipative Carrier Tape Material: Conductive Cover Tape Material: Static Dissipative Carrier Tape Cover Tape End Start Trailer Dimension A B C D N W 1 (measured at hub) W 2 (measured at hub) Trailer Leader Components Min 1.5 12.80 20.2 50 8.4 160 390, of which minimum 160 mm of empty carrier tape sealed with cover tape Leader Max Unit 178 mm mm mm mm mm mm mm mm mm 13.50 9.9 14.4 17 (18) DA6116.001 27 February, 2009 ORDERING INFORMATION Product Code Product MAS6116AA1SA306 MAS6116 MAS6116AA1SA308 MAS6116 Package 16-pin Plastic SOIC, RoHS compliant 16-pin Plastic SOIC, RoHS compliant Quantity 1000 pcs/reel in MBB 46 pcs/tube Comments MBB=Moisture Barrier Bag MSB0091A Bake recommendation for surface mounted devices LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kamreerintie 2, P.O. Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. 18 (18)