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20 September, 2000
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The MAS7838 is a single chip duplex synchronous to
asynchronous converter. It converts asynchronous start
stop characters to synchronous character format, with
stop bit deletion when required as defined in the CCITT
recommendation V.14 (V.22). On the receiver channel
the MAS7838 converts the incoming synchronous data
to asynchronous start stop character format with stop bit
insertion when required as defined in the CCITT
recommendation V.14 (V.22).The MAS7838 implements
the data modes for the synchronous interface as
specified in the V.14 (V.22). The device can be
configured to operate at any frequency to maximum
device speed within the above mentioned modes.
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• Implements CCITT recommendations V.14 and
V.22 chapters 4.1, 4.2 and 4.3
• Operates in modes as defined in the CCITT
recommendations V.22 (i), ii), iii), iv) and v)
• Transmission rate up to 64 kbit/s
• CMOS compatible interface
• Low power consumption (typically 25 mW)
• No additional circuitry required to perform the
conversion
• CMOS device
• Single =5V supply
•
•
•
Adapts asynchronous terminals to synchronous
modems
Full or half card PC modems using UART as a
data source
Simplifying data multiplexing in a MUX/DEMUX
system
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CL1
VDD
CONTROL
CL2
XESR
TMG
OSC
O
S
C
TSL
TXC
ASYNC
TO
SYNC
TDO
RXC
TDI
SYNC
TO
ASYNC
RDI
RDO
XASY
>1
_
XHST
VSS
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DA7838.002
20 September, 2000
3,1&21),*85$7,21
SO16
PDIP 16
MAS7838N
TSL 1
16 VDD
TMG 2
15 RXC
OSC 3
14 RDI
TXC 4
CL1 5
CL2 6
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;
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:
;
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XESR 7
13 RDO
12 XHST
11 XASY
10 TDO
VSS 8
MAS7838S
TSL
TMG
OSC
TXC
CL1
CL2
XESR
VSS
1
2
3
4
5
6
7
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8
16
15
14
13
12
11
10
9
VDD
RXC
RDI
RDO
XHST
XASY
TDO
TDI
9 TDI
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TSL
1
I
Timing select. 0 selects asynchronous sampling timing 16 x TXC from pin 2, TMG.
1 selects asynchronous sampling timing 256...8192 x TXC from pin 2, TMG.
TMG
2
I
Timing. Square wave timing signal 16 x TXC (TSL=0) or 256...8192 x TXC (TSL=1).
Max f=10 MHz.
OSC
3
O
Oscillator. Output for crystal. If used, the crystal is connected between pins 2 and 3.
TXC
4
I
Transmitter timing. Synchronous square wave timing for transmitter. The transmitted
data output, TDO is synchronized to the rising edge of TXC. The duty cycle of TXC
has to be 50% +/- 5%.
CL1
5
I
CL2
6
I
Character length. The total character length including one start bit, one stop bit and
possible parity bit is selected with the CL1 and CL2 signals.
XESR
7
I
Extended signalling rate. The tolerance of the synchronous bit rate can be:
XESR = 1 (basic signalling rate) TXC -2.5%...+1.0%
XESR = 0 (extended signalling rate) TXC -2.5%...2.3%
VSS
8
G
Ground
TDI
9
I
Transmitter data input. 1 = mark or stop bit, 0 = space, start or break signal
TDO
10
O
Transmitter data output. The output data is synchronized to the synchronous timing
signal TXC (pin 4). 1 = mark, 0 = space
XASY
11
I
Asynchronous mode. XASY=0 Asynchronous transmission. XASY=1 Synchronous
transmission. In synchronous transmission the converter is totally bypassed in both
directions: TDI=TDO, RDI=RDO
XHST
12
I
Higher speed signalling timing. XHST = 1 normal synchronous to asynchronous
conversion (Bell 212; CCITT V.22). XHST = 0 asynchronous to synchronous
conversion with higher speed synchronous timing (TXC, RXC). TXC and RXC timing
must be 1-2% higher than the normal bit rate in order to allow some overspeed in the
asynchronous data. On the receiver side the RX buffer is deleted and the
synchronous data RDI is directly connected to the asynchronous output RDO.
RDO
13
O
Receiver data output. RDO is the received data converted back to asynchronous
mode.
1 = mark or stop bit, 0 = space, start or break signal
RDI
14
I
Receiver data input. 1 = mark, 0 = space. The received data must be synchronized to
the receiver timing RXC from the synchronous channel (pin 15).
RXC
15
I
Receiver timing. Receiver square wave timing from the synchronous channel. The
received data RDI must be synchronized to the rising edge of RXC.
VDD
16
P
Power supply
2 (9)
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20 September, 2000
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Input low voltage
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Input leakage current
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Input capacitance load
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Internal pull-up resistor for
digital inputs
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Input high voltage
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Output low voltage
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Low to high logic transition time
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High to low logic transition time
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TDO delay time after TXC
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50
RDI set up time before RXC
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RDI hold time after RXC
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(test conditions: TSL = 0, TMG = 16xTXC)
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RDI hold time after RXC
T3
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3 (9)
DA7838.002
20 September, 2000
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Timings between synchronous clocks and data are shown below. Note that absolute delays depend on the speed of
the data transmission.
TTXC
TXC
TDO
T1
delay
TRXC
RXC
T2
T3
RDI
If pin TSL = 1 (Automatic synchronous sampling timing)
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The synchronous start-stop character, TDI (transmitter
data input), is read into the Tx buffer. When the
character is available the data bits are transferred as
TDO (transmitter data output) with the synchronous
timing signal TXC (transmitter clock). The bit rate of TDI
must be the same as the TDO rate within -2.5%...+1%
or -2.5%...+2.3% tolerance depending on XESR
(extended signalling rate) signal. The transmitter adds
extra stop bits to the synchronous data stream, if TDI is
slower than TDO. The over speed is handled by
deleting one stop bit in every 8th character at maximum
in the synchronous output data TDO. When extended
signal rate (XESR = 0) is used 4th stop bit may be
deleted. When the transmitter detects a break signal( at
least M bits of start polarity, where M is length of
character), it sends 2M + 3 bits of start - polarity to
TDO. If the break is longer than 2M + 3 bits, then all bits
are transferred to TDO. After a break signal, at least 2M
bits of stop polarity must be transmitted before sending
further data.
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The synchronous RDI (receiver data input) is buffered
to recognise the stop and start bits. If a missing stop bit
is detected, it is added to the RDO (receiver data
output). In this case the stop bits are shortened 12.5%
(25% if XESR = 0) during each character. When the
receiver gets at least 2M + 3 bits of start polarity, it does
not add stop bits to RDO. This enables the break signal
to go through the buffer.
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An alternative method to handle the over speed in
asynchronous data is to boost synchronous timing TXC
and RXC by 1-2%. In this mode XHST (higher speed
timing) = 0. In this case there is no need to delete any
stop bits in the transmitter buffer. The break signal goes
through unchanged. On the receiver side the
synchronous data, RDI, is transferred directly to the
asynchronous output RDO with RXC.
4 (9)
DA7838.002
20 September, 2000
)81&7,216
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The MAS7838 requires clock signals in order to function
properly. The synchronous data transfer always
requires the TXC clock. The clock is used internally for:
-shifting data out from the TX buffer (to pin TDO)
-shifting data into the RX buffer (via pin RDI)
-detection of the bit rate in order to adjust the internal
baud rate generator (only if TSL = 1)
The asynchronous data transfer (pins TDI, TDO) is
accomplished by generating an internal timing signal for
the asychronous circuits. This internal timing signal
(16T) is 16 times the TXC bit rate in order to sample the
asynchronous data stream (TDI) at the proper speed.
Timing Circuits
MAS 7838
16 x TXC
TXC
EXTERNALLY GENERATED 16T CLOCK
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The MAS7838 is intended for applications where an
asynchronous and synchronous data source must be
linked together. A typical case appears in a data
modem
where the terminal interface of the modem has been
specified to be asynchronous but the modem data
pump operates in a synchronous fashion.
RS232C
MODEM CIRCUITS
MAS9138
INTERFACE
TXD
TDI
TDO
TXC
RDI
RXD
RDO
RXC
PHONE LINE
5 (9)
DA7838.002
20 September, 2000
$33/,&$7,21,1)250$7,21
RS232C
MODEM CIRCUITS
MAS7838
TDO
TDI
uP INTERFACE
TXC
Sync Modem
Data Pump
RDI
RDO
RXC
PHONE LINE
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Another application is a synchronous serial interface for uP which uses UART as a data source. The concept is
illustrated below.
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A third application is a data multiplexing/demultiplexing
system. The system accepts data from several sources.
These data lines are sampled and the samples are sent
through a multiplexer to a demultiplexer. To accomplish
this, either a very high sample rate is needed or first
convert the data to synchronous mode, where
synchronous multiplexing can be used and only one
sample per data bit is needed.
M AS7838
CH 1
RDO
RDI
TDO
RDI
TDI
M AS7838
TDO
1
RDO
1
TDI
M AS7838
M AS7838
FORWARD
CH 2
2
CH N
N
MUX/
DEMUX
BACKWARD
MUX/
DEMUX
2
TIMING
N
6 (9)
DA7838.002
20 September, 2000
$33/,&$7,21,1)250$7,21
+5v
Synchronous
Modem
RS232C
TTL/V28
TXD
16
TDI
10
9
4
78189A
+12v
470pF
TTL/V28
14
RDO
TTL-Level
TXC
TTL-Level
RDI
TTL-Level
RXC
TTL-Level
75189A
*)
+5v
470pF
+5v
-12v
MAS7838
TSL
XHST
3x
4.75k
Ext. Signal Rate
Char. Length
Char. Length
+5v
2
1
RXC
16 x TXC
22pF
12
CR 1
7
9.8304MHz
5
3
6
ASY/SYN Select 11
mode
selection
jumpers
TXC
15
13
RXD
TDO
8
22pF
Modem
Timing
Circuit
*) Optional timing from the
synchronous modem.
In this case CR 1 can be
eliminated.
MAS7838 simplified application:
V.28 interface for synchronous modem
7 (9)
DA7838.002
20 September, 2000
3$&.$*(287/,1(6
16 LEAD PDIP OUTLINE (300 MIL BODY)
6.10
7.11
7.62
BSC
0 .2 5 4
1.15
1.77
0.36
0.56
5.33
MAX
5.5
5-7°
2.93
4.95
1.52
18.93
21.33
SEATING
PLANE
2.54
BSC
0.63 TYPICAL
1 PIN
ALL MEASUREMENTS IN mm
All dimensions are in accordance with JEDEC standard MS-001.
16 LEAD SO OUTLINE (300 MIL BODY)
1.27
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2.36
2.64
0.25 RAD.
MIN.
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.
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ALL MEASUREMENTS IN mm
All dimensions are in accordance with JEDEC standard MS-013.
8 (9)
DA7838.002
20 September, 2000
25'(5,1*,1)250$7,21
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MAS7838N
PDIP16
25 pcs/tube
MAS7838S-T
SO16
1000 pcs/reel
MAS7838S
SO16
47 pcs/tube
MSB0091A Bake
recommendation for
surface mounted devices
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Micro Analog Systems Oy
Kamreerintie 2, P.O.Box 51
FIN-02771 Espoo, FINLAND
http:\\www.mas-oy.com
Tel. (09) 80 521
Tel. Int. +358 9 80 521
Telefax +358 9 805 3213
E-mail: [email protected]
NOTICE
Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or
performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this
data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that circuits are
free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes
no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
9 (9)