MICROSEMI SG3825CDW

SG1825C / SG2825C / SG3825C
HIGH-SPEED CURRENT-MODE PWM
T
H E
I
N F I N I T E
P
O W E R
O F
I
P
N N O V A T I O N
R O D U C T I O N
DESCRIPTION
The SG1825C is a high-performance pulse
drivers. This device can be used to
width modulator optimized for high frequency implement either current mode or voltagecurrent-mode power supplies. Included in the mode switching power supplies. It also is
controller are a precision voltage reference,
useful as a series-resonant controller to
micro power start-up circuitry, soft start, high- frequencies beyond 1MHz. The SG1825C is
frequency oscillator, wideband error amplifier, specified for operation over the full military
fast current limit comparator, full double-pulse ambient temperature range of -55°C to
suppression logic, and dual totem pole output 125°C.
drivers. Innovative circuit design and an
The SG2825C is characterized for the
advanced linear Schottky process result in
industrial range of -25°C to 85°C, and the
very short propagation delays through the
SG3825C is selected for the commercial
current limit comparator, logic, and output
range of 0°C to 70°C.
D
A T A
„ IMPROVED REFERENCE
„
„
„
„
„
„
„
PRODUCT HIGHLIGHT
„
„
INITIAL O SCILLATOR A CCURACY
„
Percentage of Units - %
15
„
Sample Size = 279
Mean 401.661
Std. Dev. = 3.8
„
„
10
H E E T
KEY FEATURES
„
IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com
S
INITIAL TOLERANCE (±1%
max.)
IMPROVED OSCILLATOR
INITIAL ACCURACY (±3% typ.)
IMPROVED STARTUP
CURRENT (500µA typ.)
PROP DELAY TO OUTPUTS
(50ns typ.)
10V TO 30V OPERATION
5.1V REFERENCE TRIMMED
TO ±1%
2MHZ OSCILLATOR
CAPABILITY
1.5A PEAK TOTEM-POLE
DRIVERS
U.V. LOCKOUT WITH
HYSTERESIS
NO OUTPUT DRIVER "FLOAT"
PROGRAMMABLE
SOFTSTART
DOUBLE-PULSE
SUPPRESSION LOGIC
WIDEBAND LOW-IMPEDANCE
ERROR AMPLIFIER
CURRENT-MODE OR
VOLTAGE-MODE CONTROL
WIDE CHOICE OF HIGHFREQUENCY PACKAGES
KEY FEATURES
„ AVAILABLE TO MIL-STD-883B
„ MICROSEMI LEVEL "S"
5
PROCESSING AVAIL.
0
390
395
400
405
410
415
Initial Oscillator Accuracy - KHz
PACKAGE ORDER INFO
TJ (°C)
0 to 70
-25 to 85
-55 to 125
MIL-STD-883
DESC
N
Plastic DIP
16-Pin
DW
Plastic SOIC
16-Pin
RoHS Compliant / Pb-free
Transition DC: 0503
RoHS Compliant / Pb-free
Transition DC: 0516
SG3825CN
SG2825CN
-
SG3825CDW
SG2825CDW
-
Q
Plastic LCC
20-Pin
SG32825CQ
SG2825CQ
-
J
Ceramic DIP
16-Pin
L
Ceramic LCC
20-Pin
SG3825CJ
SG282CJ
SG1825CJ
SG1825CL
SG1825CJ/883B
SG1825CL/883
SG1825CJ/DESC SG1825CL/DESC
Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. SG3825CN-TR)
Copyright © 1994
Rev. 1.3a,2005-03-21
LINFINITY MICROELECTRONICS INC.
11861 WESTERN AVENUE, GARDEN GROVE, CA. 92841, 714-898-8121, FAX: 714-893-2570
1
PRODUCT DATABOOK 1996/1997
SG1825C/SG2825C/SG3825C
H IGH- SPEED C URRENT-M O D E PWM
NOT RECOMMENDED
A B S O L U T E M A X I M U M R AT I N G S
FOR
NEW DESIGNS
PACKAGE PIN OUTS
(Note 1)
RoHS Peak Package Solder Reflow Temp. (40 sec. max. exp.)......................................................... 260° (+0, -5)
Input Voltage (VIN and VC) .......................................................................................... 30V
Analog Inputs:
Error Amplifier and Ramp ........................................................................ -0.3V to 7.0V
Softstart and ILIM/S.D. ................................................................................ -0.3V to 6.0V
Digital Input (Clock) .................................................................................... 1.5V to 6.0V
Driver Outputs ........................................................................................ -0.3V to V C +1.5V
Source / Sink Output Current (each output):
Continuous .............................................................................................................. 0.5A
Pulse, 500ns ............................................................................................................ 2.0A
Softstart Sink Current ................................................................................................ 20mA
Clock Output Current ................................................................................................. 5mA
Error Amplifier Output Current ................................................................................. 5mA
Oscillator Charging Current ....................................................................................... 5mA
Operating Junction Temperature:
Hermetic (J, L Package) ....................................................................................... 150°C
Plastic (DW, N, Q Packages) ............................................................................... 150°C
Storage Temperature Range ...................................................................... -65°C to 150°C
Lead Temperature (soldering, 10 seconds) ............................................................ 300°C
INV. INPUT
N.I. INPUT
E/A OUTPUT
CLOCK
RT
CT
RAMP
SOFTSTART
INV. INPUT
N.I. INPUT
E/A OUTPUT
CLOCK
RT
CT
RAMP
SOFTSTART
65°C/W
DW PACKAGE:
12
6
11
7
10
8
9
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
+VREF
+VIN
OUTPUT B
VC
PWR GND
OUTPUT A
GROUND
ILIM / S.D.
95°C/W
2
1
20 19
18
17
6
16
7
15
8
14
9
80°C/W
10 11 12 13
Q PACKAGE
(Top View)
80°C/W
3
L PACKAGE:
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
13
5
5
J PACKAGE:
THERMAL RESISTANCE-JUNCTION TO CASE, θJC
14
4
4
Q PACKAGE:
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
3
VREF
+VIN
OUTPUT B
VC
PWR GND
OUTPUT A
GROUND
I LIM / S.D.
1
3
N PACKAGE:
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
15
DW PACKAGE*
(Top View)
T H E R M A L D ATA
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
16
2
J & N* PACKAGE
(Top View)
Note 1. Exceeding these ratings could cause damage to the device.
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
1
2
1 20 19
35°C/W
4
18
120°C/W
5
17
6
16
7
15
8
14
Junction Temperature Calculation: TJ = T A + (PD x θJA).
The θ JA numbers are guidelines for the thermal performance of the device/pc-board
system. All of the above assume no ambient airflow.
9 10 11 12 13
L PACKAGE
(Top View)
1. N.C.
2. INV. INPUT
3. N.I. INPUT
4. E/A OUTPUT
5. CLOCK
6. N.C.
7. RT
8. CT
9. RAMP
10. SOFTSTART
11. N.C.
12. ILIM / S.D.
13. GROUND
14. OUTPUT A
15. PWR GND
16. N.C.
17. VC
18. OUTPUT B
19. +VIN
20. V REF
*DW & N Packages: RoHS / Pb-free 100% Matte Tin Lead Finish
2
Copyright © 1994
Rev. 1.3a
PRODUCT DATABOOK 1996/1997
SG1825C/SG2825C/SG3825C
HIGH-SPEED CURRENT-MODE PWM
NOT RECOMMENDED
FOR
NEW DESIGNS
R E C O M M E N D E D O P E R AT I N G C O N D I T I O N S
Parameter
Symbol
Supply Voltage Range
Voltage Amp Common Mode Range
Ramp Input Voltage Range
Current Limit / Shutdown Voltage Range
Source / Sink Output Current
Continuous
Pulse, 500ns
Voltage Reference Output Current
Oscillator Frequency Range
Oscillator Charging Current
Oscillator Timing Resistor
Oscillator Timing Capacitor
Operating Ambient Temperature Range:
SG1825C
SG2825C
SG3825C
(Note 2)
Recommended Operating Conditions
Min.
Typ.
Max.
10
1.5
0
0
Units
30
5.5
5.0
4.0
V
V
V
V
RT
CT
1
4
0.030
1
0.470
10
1500
3
100
10
mA
A
mA
kHz
mA
kΩ
nF
TA
TA
TA
0
-25
-55
70
85
125
°C
°C
°C
200
1.0
Note 2. Range over which the device is functional.
ELECTRICAL CHARACTERISTICS
(Note 3)
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG3825C with 0°C ≤ TA ≤ 70°C, SG2825C with
-25°C ≤ TA ≤ 85°C, SG1825C with -55°C ≤ TA ≤ 125°C, and VIN=V C=15V. Low duty cycle pulse testing techniques are used which maintains junction
and case temperatures equal to the ambient temperature.)
Parameter
Symbol
Test Conditions
Reference Section
SG1825C/2825C
SG3825C
Units
Min. Typ. Max. Min. Typ. Max.
Output Voltage
Line Regulation
Load Regulation
Temperature Stability (Note 3)
Total Output Range (Note 3)
Output Noise Voltage (Note 3)
Long Term Stability (Notes 3 &4)
Short Circuit Current
Oscillator Section (Note 5)
TJ = 25°C, IL = 1mA
VIN = 10 to 30V
I L = 1 to 10mA
Over Operating Temperature
Over Line, Load, and Temperature
f = 10Hz to 10kHz, IL = 0mA
TJ = 125°C, t = 1000hrs
VREF = 0V
5.05 5.10 5.15 5.05 5.10 5.15
2
15
2
15
5
15
5
15
0.2 0.4
0.2 0.4
5.00
5.20 5.00
5.20
50 200
50
5
25
5
25
-15 -50 -100 -15 -50 -100
Initial Accuracy
Voltage Stability
Temperature Stability (Note 3)
Total Frequency Limits (Note 3)
Minimum Frequency
Maximum Frequency
Clock High Level
Clock Low Level
Ramp Peak Voltage
Ramp Valley Voltage
Valley-to-Peak Amplitude
TJ = 25°C, CCLK ≤ 10pF
VIN = 10 to 30V
Over Rated Operating Temperature
Over Line and Temperature
RT = 100KΩ, CT = 0.01µF
RT = 1KΩ, CT = 470pF
ICLK = -1mA
ICLK = -1mA
370
400
0.2
5
350
1.5
3.9
2.6
0.7
1.6
4.5
2.3
2.8
1.0
1.8
430
2
8
450
4
370
350
1.5
3.9
2.9
3.0
1.25
2.0
400
0.2
5
2.6
0.7
1.6
4.5
2.3
2.8
1.0
1.8
430
2
8
450
4
2.9
3.0
1.25
2.0
V
mV
mV
mV/°C
V
µV RMS
mV
mA
kHz
%
%
kHz
kHz
MHz
V
V
V
V
V
Note 3. This parameter is guaranteed by design and process control, but is not 100% tested in production.
Note 4. This parameter is non-accumulative, and represents the random fluctuation of the reference voltage within some error band when observed
over any 1000 hour period of time.
Copyright © 1994
Rev. 1.3a
3
PRODUCT DATABOOK 1996/1997
SG1825C/SG2825C/SG3825C
H IGH- SPEED C URRENT-M O D E PWM
NOT RECOMMENDED
FOR
NEW DESIGNS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Test Conditions
(Cont'd.)
SG1825C/2825C
SG3825C
Units
Min. Typ. Max. Min. Typ. Max.
Error Amplifier Section (Note 6)
Input Offset Voltage
Input Bias Current
Input Offset Current
DC Open Loop Gain
Common Mode Rejection
Power Supply Rejection
Output Sink Current
Output Source Current
Output High Voltage
Output Low Voltage
Unity Gain Bandwidth (Note 3)
Slew Rate (Note 3)
AVOL
RS ≤ 2KΩ, VERROR = 2.5V
VERROR = 2.5V
VERROR = 2.5V
VERROR = 1 to 4V
Over Rated Voltage Range, VERROR = 2.5V
VIN = 10V to 30V, VERROR = 2.5V
VERROR = 1V
VERROR = 4V
IERROR = -0.5mA
IERROR = 1mA
AVOL = 0dB
60
75
85
1
-0.5
4.0
0
3
6
0.6
0.1
95
95
110
2.5
-1.3
4.7
0.5
5.5
15
3
1
5.0
1.0
60
75
85
1
-0.5
4.0
0
3
6
0.6
0.1
95
95
110
2.5
-1.3
4.7
0.5
5.5
15
3
1
5.0
1.0
mV
µA
µA
dB
dB
dB
mA
mA
V
V
MHz
V/µsec
PWM Comparator Section (Note 5 & 7)
Ramp Input Bias Current
Minimum Duty Cycle
Maximum Duty Cycle (Note 8)
Zero Duty Cycle Threshold
Delay to Driver Output (Note 3)
-1
VERROR = 1V
VERROR = 4V
85
1.1
VRAMP = 0V to 2V, VERROR= 2V
-5
0
-1
85
1.1
1.25
50
80
9
20
-5
0
1.25
50
80
9
20
µA
%
%
V
ns
Softstart Section
CSS Charge Current
CSS Discharge Current
VSOFTSTART = 0.5V
VSOFTSTART = 1.0V
3
1
3
1
µA
mA
Current Limit / Shutdown Section (Note 9)
ILIM Input Bias Current
Current Limit Threshold
Shutdown Threshold
Delay to Driver Output (Note 3)
VSHUTDOWN = 0V to 1.2V
±15
±10
0.9 1.0 1.1 0.9 1.0 1.1
1.25 1.40 1.55 1.20 1.40 1.55
50
80
50
80
µA
V
V
ns
ISINK = 20mA
ISINK = 200mA
ISOURCE = 20mA
ISOURCE = 200mA
VC = 30V
CL = 1000pF
0.25 0.40
0.25 0.40
1.2 2.0
1.2 2.0
13.0 13.5
13.0 13.5
12.0 13.0
12.0 13.0
150 500
150 500
30
60
30
60
V
V
V
V
µA
ns
Output Drivers Section (each output)
Output Low Level
Output High Level
VC Standby Current
Output Rise / Fall Time (Note 3)
Undervoltage Lockout Section
Start Threshold Voltage
UV Lockout Hysteresis
8.8
0.4
9.2
0.8
9.7
1.2
0.5
22
1.2
33
8.8
0.4
9.2
0.8
9.7
1.2
V
V
0.5
22
1.2
33
mA
mA
Supply Current Section (Note 5)
Start Up Current
Operating Current
Note
Note
Note
Note
Note
4
VIN = 8V
VINV , VRAMP, V(I LIM/S.D.) = 0V, VN.I. = 1V
5. FOSC = 400kHz (R T = 3.65kΩ, CT = 1.0nF).
6. VCM = 1.5V to 5.5V.
7. VRAMP = 0V, unless otherwise specified.
8. 100% duty cycle is defined as a pulsewidth equal to one oscillator period.
9. V(ILIM/S.D.) = 0V to 4.0V, unless otherwise specified.
Copyright © 1994
Rev. 1.3a
PRODUCT DATABOOK 1996/1997
SG1825C/SG2825C/SG3825C
HIGH-SPEED CURRENT-MODE PWM
NOT RECOMMENDED
FOR
NEW DESIGNS
BLOCK DIAGRAM
VREF
16
+9V
13 VC
11 OUTPUT A
REFERENCE
REGULATOR
+VIN 15
GND 10
Q
+ 4.0V
T
CLOCK 4
Q
14 OUTPUT B
RT 5
OSCILLATOR
CT 6
S
12 POWER GND
R Q
1.25V
RAMP 7
E/A OUTPUT 3
N.I. INPUT 2
ERROR
INV. INPUT 1
9µA
+ 1.0V
SOFTSTART 8
9 ILIM/S.D.
+ 1.4V
FIGURE INDEX
Application Circuits
FIGURE #
1.
HIGH-SPEED LAYOUT AND BYPASSING
2.
MICROPOWER STARTUP
3.
SOFTSTART FAST RESET
4.
OSCILLATOR SYCHRONIZATION
5.
OSCILLATOR FUNCTIONAL DIAGRAM
6.
VOLTAGE AMPLIFIER CONNECTIONS
7.
DRIVING SHIELDED CABLE
Copyright © 1994
Rev. 1.3a
5
PRODUCT DATABOOK 1996/1997
SG1825C/SG2825C/SG3825C
H IGH- SPEED C URRENT-M O D E PWM
NOT RECOMMENDED
FOR
NEW DESIGNS
A P P L I C AT I O N I N F O R M AT I O N
A P P L I C AT I O N F I G U R E S
HIGH-SPEED LAYOUT AND BYPASSING
FIGURE 1. — HIGH-SPEED LAYOUT and BYPASSING
The SG1825C, like all high-speed circuits, requires extra attention to external
conductor and component layout to minimize undesired inductive and
capacitive effects. All lead lengths must be as short as possible. The best
printed circuit board choice would be a four-layer design, with the two
internal planes supplying power and ground. Signal interconnects should
be placed on the outside, giving a conductor-over-ground-plane
(microstrip) configuration. A two-sided printed circuit board with one side
dedicated as a ground plane is next best, and requires careful component
placement by a skilled pc designer.
Two supply bypass capacitors should be employed: a low-inductance
0.1µF ceramic within 0.25 inches of the +VIN pin for high frequencies, and
a 1 to 5µF solid tantalum within 0.5 inches of the VC pin to provide an energy
reservoir for the high-peak output currents. A low-inductance .01µF bypass
for the reference output is also recommended.
VREF 16
VREF
SG1825C
VC 13
PWR GND
0.1µF
GND
15 +V
IN
12
0.01µF
10
1µF
+VIN
FIGURE 2. — MICROPOWER STARTUP
TO POWER TRANSFORMER
GND
6
POWER 12
GND
RB
L2
0.1µF
CS
15 +V
IN
GND
10
1µF
+ VIN
FIGURE 3. — SOFTSTART FAST RESET
SG1825C
CSS
R1
100W
8
VC 13
PWR GND
0.1µF
15 +V
IN
GND
12
CSOFTSTART
10
1µF
+ VIN
FIGURE 4. — OSCILLATOR SYCHRONIZATION
FREQUENCY SYNCHRONIZATION
Two or three SG1825C oscillators may be locked together with the
interconnection scheme shown, if the devices are within an inch or so of
each other. A master unit is programmed for desired frequency with RT and
CT as usual. The oscillators in the slave units are disabled by grounding CT
and by connecting RT to VREF. The logic in the slave units is locked to the
clock of the master with the wire-OR connection shown.
Many SG1825Cs can be locked to a master system clock by wiring the
oscillators as slave units, and distributing the master clock to each using a
tree-fanout geometry.
VC 13
L1
SOFTSTART CIRCUIT / OUTPUT DUTY CYCLE LIMIT
The softstart pin of the SG1825C is held low when either the chip is in the
micropower mode, or when a voltage greater than +1.4 volts is present at
the ILIM/S.D. pin. The maximum positive swing of the voltage error amplifier
is clamped to the Softstart pin voltage, providing a ramp-up of peak charging
currents in the power semiconductors at turn-on.
In some cases, the duration of the Shutdown signal can be too short to
fully discharge the softstart capacitor. The illustrated resistor/discrete PNP
transistor configuration can be used to shorten the discharge time by a factor
of 50 or more. When the internal discharge transistor in the SG1825C turns
on, current will flow through surge limit resistor R1. As the resistor drop
approaches 0.6 volts, the external PNP turns on, providing a low resistance
discharge path for the energy in the softstart capacitor. The capacitor will
be rapidly discharged to +0.7 volts, which corresponds to zero duty cycle
in the pulse width modulator.
SG1825C
120
Since the SG1825C typically draws 700µA of supply current before turning
on, a low power bleeder resistor from the rectified AC line supply is all that
is required for startup. A start capacitor, CS, is charged with the excess
current from the bleeder resistor. When the turn-on threshold voltage is
reached, the PWM circuit becomes active, energizing the power transistors.
The additional operating current required by the PWM is then provided by
a bootstrap winding on the main high-frequency power transformer.
240
MICROPOWER STARTUP
MASTER
CLK
SG1825C
RT
4
4
SLAVE
CLK
0.1µF
15 +V
IN
GND
RT 5
CT 6
12
10
16
SG1825C
5
CT 6
PWR GND
VREF
PWR GND
CT
RT
0.1µF
15 +V
IN
GND
12
10
+ VIN
Copyright © 1994
Rev. 1.3a
PRODUCT DATABOOK 1996/1997
SG1825C/SG2825C/SG3825C
HIGH-SPEED CURRENT-MODE PWM
NOT RECOMMENDED
FOR
NEW DESIGNS
A P P L I C AT I O N I N F O R M AT I O N
A P P L I C AT I O N F I G U R E S
FIGURE 5. — OSCILLATOR FUNCTIONAL DIAGRAM
OSCILLATOR
The oscillator frequency is programmed by external timing components R T
and CT . A nominal +3.0 volts appears at the RT pin. The current flowing
through RT is mirrored internally with a 1:1 ratio. This causes an identical
current to flow out the CT pin, charging the timing capacitor and generating
a linear ramp. When the upper threshold of +2.8 volts is reached, a
discharge network reduces the ramp voltage to +1.0, where a new charge
cycle begins.
The Clock output pin is LOW (+2.3 volts) during the charge cycle, and
HIGH (+4.5 volts) during the discharge cycle. The Clock pin is driven by
an NPN emitter follower, and so can be wire-ORed. Each Clock pin can drive
a 1mA load. Since the internal current-source pulldown is approximately
400µA, the DC fan-out to other SG1825C Clock pins is at least two.
The type of capacitor selected for CT is very important. At high
frequencies, non-ideal characteristics such as effective series resistance
(ESR), effective series inductance (ESL), dielectric loss and dielectric
absorption all affect frequency accuracy and stability. RF capacitors such as
silver mica, glass, polystrene, or COG ceramics are recommended. Avoid
high-K ceramics, which work best in DC bypass applications.
ERROR AMPLIFIER
The voltage error amplifier is a true operational amplifier with lowimpedance output, and can be gain-stabilized using conventional feedback
techniques. The typical DC open-loop gain is 95dB, with a single lowfrequency pole at 100Hz.
The input connections to the error amplifier are determined by the
polarity of the power supply output voltage. For positive supplies, the
common-mode voltage is +5.1 volts and the feedback connections in Figure
A are used. With negative outputs, the common-mode voltage is half the
reference, and the feedback divider is connected between the negative
output and the +5.1 volt reference as shown in Figure B.
RT
3V
IR
SG1825C
5
+ 5.1V
IC = IR
CT
6
+ 4.5V
4 CLOCK
400µA
2.8V
1.0V
FIGURE 6. — VOLTAGE AMPLIFIER CONNECTIONS
R1
VREF
R2
2
3 VERROR
1
R3
RZ
CP
POSITIVE
OUTPUT
VOLTAGE
R4
Copyright © 1994
Rev. 1.3a
FIGURE B
FIGURE A
R1
VREF
R2
NEGATIVE
OUTPUT
VOLTAGE
R4
2
3 VERROR
1
R3
VREF
2
OUTPUT DRIVER
The output drivers are designed to provide up to 1.5 Amps peak output
current. To minimize ringing on the output waveform, which can be
destructive to both the power MOSFET and the PWM chip, the series
inductance seen by the drivers should be as low as possible.
One solution is to keep the distance between the PWM and MOSFET gate
as short as possible, and to use carbon composition series damping resistors.
A Faraday shield to intercept radiated EMI from the power transistors is
usually required with its choice.
A second approach is to place the MOSFETs some distance from the PWM
chip, and use a series-terminated transmission line to preserve drive pulse
fidelity. This will minimize noise radiated back to the sensitive analog
circuitry of the SG1825C. A Faraday shield may also be required.
If the drivers are connected to an isolation transformer, or if kickback
through CGD of the MOSFET is severe, clamp diodes may be required. 1 Amp
peak Schottky diodes will limit undershoot to less than -0.3 volts.
+ 2.3V
RZ
CP
FIGURE 7. — DRIVING SHIELDED CABLE
SG1825C
FARADAY SHIELD
13 VC
24W
11
*
12
10
50W
50W
PWR GND
GND
* SCHOTTKY CLAMP MAY BE REQUIRED
7