MURATA-PS ADS-236

®
ADS-235, ADS-236, ADS-237
®
12-Bit, 5MHz and 9MHz
Sampling A/D Converters
FEATURES
·
·
·
·
·
·
·
·
·
·
5MHz (ADS-235/236) and 9MHz (ADS-237) sampling rates
Low power
Outstanding dynamic performance
Fully differential or single-ended analog input
100MHz full power input bandwidth
Integral sample-and-hold
Single +5V supply operation
Internally generated DC bias Voltage
3.0/5.0V CMOS compatible digital output
TTL/CMOS compatible digital inputs/outputs
GENERAL DESCRIPTION
INPUT/OUTPUT CONNECTIONS
The ADS-235, ADS-236 and ADS-237 are monolithic, 12-bit,
sampling analog-to-digital converters fabricated in a CMOS
process. The converters are designed for applications where
high speed, wide bandwidth and low power dissipation are
essential. These characteristics are provided through the use
of a fully differential sampling pipeline A/D architecture with
digital error correction logic.
PIN FUNCTION
The ADS-235, ADS-236 and ADS-237 offer excellent dynamic
performance while consuming only 300mW. The digital output
circuit is separate and can be powered from either a 3V or 5V
supply allowing the user to interface with 3V logic, if desired.
The ADS-235, ADS-236 and ADS-237 provide the user with
an internally generated DC bias voltage output. This DC bias
voltage is ideal for AC coupled analog input applications.
The units are available in a 28-lead plastic SOIC package
and operate over the 0°C to 70°C and –40 to +85°C
temperature ranges.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIN FUNCTION
CLK, CLOCK
+DVS1, +5V DIG. SUP.
DGND1
+DVS1, +5V DIG. SUP.
DGND1
+AVS, +5V ANALOG SUP.
AGND
VIN+, ANALOG INPUT
VIN–, ANALOG INPUT
VDC, DC BIAS OUTPUT
VROUT, REF. OUT
VRIN, REF. IN
AGND
+AVS, +5V ANALOG SUP.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
+DVS2, DIG. OUTPUT SUP.
DGND2
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1 (MSB)
Stage 4
4-Bit
Flash A/D
15 Bit 1 (MSB)
X8
16 Bit 2
Stage 3
17 Bit 3
–
18 Bit 4
+
19 Bit 5
4-Bit
Flash A/D
4-Bit
DAC
X8
Digital Delay
and
Error
Correction
Stage 1
VROUT 11
VRIN 12
VIN+
8
VIN–
9
23 Bit 7
24 Bit 8
25 Bit 9
–
Reference
20 Bit 6
26 Bit 10
27 Bit 11
+
28 Bit 12 (LSB)
4-Bit
Flash A/D
S/H
4-Bit
DAC
2.3 Volt
DC Bias Output
VDC 10
Clock
2, 4
+DVS1
3, 5
DGND 1
6, 14
+AVS
7, 13
AGND
22
+DVS2
1 CLK
21
DGND 2
Figure 1. ADS-235, ADS-236 and ADS-237 Functional Block Diagram
DATEL, Inc., Mansfield, MA 02048 (USA) · Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 · Email: [email protected] · Internet: www.datel.com
®
®
ADS-235, ADS-236, ADS-237
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
+AVS, +DVS1 and +DVS2 Supplies
DGND to AGND
Analog I/O Pins
Digital I/O Pins
Lead Temperature
(10 seconds, Pin Tips Only)
PHYSICAL/ENVIRONMENTAL
LIMITS
UNITS
+6.0
0.3
AGND to +AVS Supply
DGND to +DVS Supply
Volts
Volts
Volts
Volts
300
°C
PARAMETERS
MIN.
Operating Temperature Range
ADS-235S
ADS-236S/ADS-237S
Storage Temperature Range
Thermal Resistance, qja ➀
Junction Temperature
Package Type
0
–40
–65
—
—
TYP.
MAX.
—
70
—
85
—
150
75
—
150
28-Pin Plastic SOIC
UNITS
°C
°C
°C
°C/W
°C
➀ Measured mounted on PC board in free air.
FUNCTIONAL SPECIFICATIONS
(TA = +25°C, (ADS-235), TMIN to TMAX (ADS-236/237), +DVS1 = +DVS2 = +AVS = +5V, VRIN = 3.5V, FS = 5MHz (ADS-235/236) and 9MHz (ADS-237) at a 50% duty
cycle, CL =10pF, and differential analog input unless otherwise specified.)
ANALOG INPUTS
MIN.
Max. Peak-to-Peak Diff. Voltage
Input Range (VIN+ - VIN–)
Max. Peak-to-Peak Single-Ended
Voltage Input Range
Analog Input Common Mode
Voltage Range (VIN+ + VIN–)/2 ➀
Input Bias Current, IB+ or IB– ➁
Differential Input
Current, (IB+ - IB–)
Input Impedance ➁
Input Capacitance
TYP.
MAX.
UNITS
—
±2.0
—
Volts
—
4.0
—
Volts
1.0
–10
2.3
—
4.0
10
Volts
µA
—
1.0
—
±0.5
—
10
—
—
—
µA
MW
pF
—
—
3.5
—
—
1
Volts
mA
—
—
—
—
200
50
—
—
—
ppm/°C
ppm/°C
ppm/°C
PERFORMANCE (cont.)
Second Harmonic, F IN=1MHz
ADS-235
ADS-236
ADS-237
Third Harmonic, FIN=1MHz
ADS-235
ADS-236
ADS-237
Effective Number Of Bits,
ENOB, FIN=1MHz
ADS-235
ADS-236
ADS-237
Signal to Noise Ratio and
Distortion, SINAD, FIN=1MHz
ADS-235
ADS-236
ADS-237
Signal to Noise Ratio,
SNR, FIN=1MHz
ADS-235
ADS-236
ADS-237
Intermodulation Distortion,
IMD, F1=1MHz F2=1.02MHz
ADS-235
ADS-236
ADS-237
Transient Response ➄
Over-Voltage Recovery,
0.2V Overdrive
INTERNAL VOLTAGE REFERENCE
Reference Output Voltage, VROUT
Reference Output Current
Reference Temperature Coefficient
ADS-235 ➂
ADS-236
ADS-237
REFERENCE VOLTAGE INPUT
Reference Voltage Input, VRIN
Total Reference Resistance, RL
Reference Current
—
—
—
3.5
7.8
450
—
—
—
Volts
kW
µA
12
—
—
Bits
—
5
9
—
5
—
—
0.5
—
—
—
—
MHz
MHz
MHz
MHz
—
—
±2.0
±1.0
—
±2.0
LSB
LSB
—
±0.5
±1.0
LSB
—
—
12
19
—
—
LSB
LSB
—
—
—
—
—
24
32
5
5
100
—
—
—
—
—
LSB
LSB
ns
ps(RMS)
MHz
PERFORMANCE
Resolution
Maximum Sample Rate, FCLK
ADS-235
ADS-236
ADS-237
Minimum Sample Rate
Integral Nonlinearity, F IN=DC
ADS-235
ADS-236, ADS-237
Differential Nonlinearity,
FIN=DC ➃
Input Offset Error, FIN=DC
ADS-235
ADS-236, ADS-237
Full Scale Error, FIN=DC
ADS-235
ADS-236, ADS-237
Aperture Delay, tAP
Aperture Uncertainty, tAJ
Full Power Input Bandwidth
Spurious Free Dynamic Range,
SFDR, FIN=1MHz
ADS-235
ADS-236
ADS-237
Total Harmonic Distortion,
THD, FIN=1MHz
ADS-235
ADS-236
ADS-237
—
—
—
73
83
77
—
—
—
dB
dB
dB
—
—
—
–70
–80
–75
—
—
—
dB
dB
dB
MIN.
TYP.
MAX.
UNITS
—
—
—
–73
–86
–80
—
—
—
dB
dB
dB
—
—
—
–73
–83
–77
—
—
—
dB
dB
dB
—
—
—
10.3
11
10.8
—
—
—
Bits
Bits
Bits
—
—
—
64
68
66.5
—
—
—
dB
dB
dB
—
—
—
65
68
67.3
—
—
—
dB
dB
dB
—
—
—
—
–66
–68
–65
1
—
—
—
—
dB
dB
dB
Cycle
—
2
—
Cycle
—
—
8
8
—
—
ns
ns
90
106
—
100
111
—
110
116
3
ns
ns
Cycles
—
—
2.3
—
—
1.0
volts
mA
–0.2
1.6
—
—
—
—
—
–0.2
1.6
5
—
—
—
—
—
mA
mA
mA
mA
pF
TIMING CHARACTERISTICS
Data Output Hold, tH
Data Output Delay, tOD
Clock Pulse Width, TPWO, TPW1
ADS-235, ADS-236
ADS-237
Data Latency, tLAT
DC BIAS VOLTAGE OUTPUT
DC Bias Voltage Output,VDC
DC Bias Voltage Current
DIGITAL OUTPUTS
Logic Levels
Logic "1", +DVS2=5V,
Logic "0", +DVS2=5V,
Logic "1", +DVS2=3V,
Logic "0", +DVS2=3V,
Output Capacitance
2
VOH=2.4V
VOL=0.4V
VOH=2.4V
VOL=0.4V
®
®
ADS-235, ADS-236, ADS-237
POWER REQUIREMENTS
Power Supply Ranges
+5V Analog Supply, +AVS
+5V Digital Supply, +DVS1
+3V Digital Supply, +DVS2
+5V Digital Supply, +DVS2
Power Supply Currents
ADS-235, ADS-236
+AIS
+DIS1
+DIS2
ADS-237
+AIS
+DIS1
+DIS2
Power Dissipation
ADS-235
ADS-236
ADS-237
Offset Error Sensitivity, 5V±5%
ADS-235
ADS-236, ADS-237
Gain Error Sensitivity, 5V±5%
ADS-235
ADS-236, ADS-237
MIN.
TYP.
MAX.
UNITS
+4.75
+4.75
+2.7
+4.75
5
5
3
5
+5.25
+5.25
+3.3
+5.25
Volts
Volts
Volts
Volts
—
—
—
46
13
1
—
—
—
mA
mA
mA
—
—
—
46
17
2
—
—
—
mA
mA
mA
—
—
—
300
300
325
—
350
365
mW
mW
mW
—
—
±16
2
—
—
LSB
LSB
—
—
±16
30
—
—
LSB
LSB
applied to the sampling capacitors, CS. At the same time the
hold capacitors, CH, are discharged to analog ground. At the
falling edge of Ø1 the input signal is sampled on the bottom
plates of the sampling capacitors. In the next clock phase, Ø2,
the two bottom plates of the sampling capacitors are connected
together and the holding capacitors are switched to the op-amp
output nodes. The charge then redistributes between CS and
CH completing one sample and hold cycle.
The sample and hold output is a fully differential representation
of the sampled analog input. The circuit not only performs the
sample-hold function but will also convert a single-ended input
to a fully differential output. During the sampling phase, the VIN
pins see only the on resistance of a switch and CS. The small
values of these components result in a typical full power input
bandwidth of 100MHz for the converters.
As illustrated in the Functional Block Diagram, figure 1, and the
Internal Timing Diagram, figure 2A, three identical pipeline
sub-converter stages, each containing a four-bit flash converter
and a four-bit multiplying digital-to-analog converter, follow the
S/H with the fourth stage being a four-bit flash converter. Each
converter stage in the pipeline will be sampling in one clock
phase and amplifying in the other clock phase. Each subconverter clock signal is offset by 180 degrees from the
previous stage clock signal resulting in alternate stages in the
pipeline performing the same operation.
Footnotes: ➀ Differential Mode
➁ CLK off and Low
➂ Not specified
➃ No missing codes
➄ For FS step to settle to 12-bits accuracy
The four-bit output of each of the sub-converter stages is used
by the error correction logic. The output of each stage is input
to a digital delay line which is controlled by the internal
sampling clock. The function of the delay line is to align the
digital outputs in time of the three identical stages with the
output of the fourth stage flash converter before applying the
sixteen bit result to the error correction logic. The error
correction logic uses the supplementary bits to correct any
error that may exist before generating the final twelve-bit digital
data output.
FUNCTIONAL DESCRIPTION
The ADS-235, ADS-236 and ADS-237 are 12-bit fully
differential pipeline sampling A/D converters with digital error
correction. Referring to the Functional Block Diagram shown in
figure 1, figure 3.1 shows the circuit for the front end differential
in and out sample-and-hold (S/H). The switches are controlled
by an internal sampling clock which is a non-overlapping two
phase signal, Ø1 and Ø2, derived from the master sampling
clock. During the sampling phase, Ø1, the input signal is
Due to the pipeline nature of this converter, the digital data
representing an analog input sample is output to the digital
Analog Input,
VIN
A/D CLK
SN–1 HN–1
1ST Stage
2ND Stage
3RD Stage
SN
HN
B1, N–1
B2, N–2
B1, N
B2, N–1
B3, N–2
4TH Stage
Data
Output
SN+1 HN+1 SN+2
SN+4 HN+4
B1, N+2
B1, N+3
B1, N+1
B2, N
B3, N–1
B4, N–2
DN–3
HN+2 SN+3 HN+3
B2, N+1
B3, N
B4, N–1
DN–2
B2, N+2
B3, N+1
B4, N
DN–1
B1, N+4
B2, N+3
B3, N+2
B4, N+1
DN
SN+5 HN+5 SN+6 HN+6
B2, N+4
B3, N+3
B4, N+2
DN+1
tLAT
B1, N+5
B2, N+5
B3, N+4
B4, N+3
DN+2
B4, N+4
DN+3
Notes: 1. SN: N-th sampling period.
2. HN: N-th holding period.
3. BM, N: M-th stage digital output corresponding to N-th sampled input.
4. DN: Final data output corresponding to N-th sampled input.
Figure 2A. Internal Timing Diagram
3
®
®
ADS-235, ADS-236, ADS-237
data bus on the third cycle of the clock after the analog sample
is taken. After this latency delay, the digital data representing
each successive sample of the analog input is output during
the following clock cycle. The digital output data is
synchronized to the external sampling clock through a double
buffered latching circuit. The output of the digital error
correction circuit is available in offset binary format.
sufficient but the actual value must take into account the
highest frequency component of the input signal.
Single-Ended Analog Input
The circuit in figure 3.4 may be used with a single-ended AC
coupled input. Assuming again that the difference between the
two internal voltage references is 2V and VIN is a 4Vp-p
sinewave, then VIN+ is a 4Vp-p sinewave riding on a positive
voltage equal to VDC. The converter will be at a positive full
scale when VIN+ is at VDC+2V (VIN+ - VIN– = 2V) and will be
equal to a negative full scale when VIN+ is equal toVDC-2V
(VIN+ - VIN– = –2V). In this case, VDC could range between 2V
and 3V without significant change in the converters
performance. The simplest way to obtain a VDC voltage is to
use the VDC output provided by the converters.
Differential Analog Input
The analog input is a differential input that can be configured in
various ways depending on the signal source and the level of
performance desired. A fully differential connection as shown
in figures 3.2 and 3.3 will give the best performance.
The ADS-235, ADS-236 and ADS-237 are powered by a single
+5V analog power supply which limits the analog input to
between ground and +5V. For the differential input connection
this implies that the analog input common mode voltage can
range from 1.0V to 4.0V, see figure 3.6. Performance for the
converter does not change significantly with the value of the
analog input common mode voltage. A DC voltage source, VDC,
equal to 2.3V, typical, is provided to help simplify circuit design
when using an AC coupled differential input. This low
impedance voltage source is not designed to be a reference
voltage but makes an excellent DC bias source. This bias
voltage source stays well within the analog input common
mode voltage range over temperature.
The single-ended analog input can be DC coupled, as shown
figure 3.5, as long as the input is within the analog input
common mode voltage range. The resistor, R, shown is not
absolutely necessary but may be used as a load setting
resistor. A capacitor, C, connected between VIN+ and VIN– will
help filter high frequency noise. A value of approximately 20pF
is normally sufficient but the actual value must take into
account the highest frequency component of the input signal.
INTERNAL REFERENCE GENERATOR, VROUT VRIN
The ADS-235/236/237 have an internal reference generator,
therefore, an external voltage is not required. VROUT must be
connected to VRIN when using the internal reference voltage.
Two reference voltages are generated internally, 1.3V and
3.3V, for a fully differential input range of ±2V.
The difference between the converter's two internal reference
voltages is 2V. For the AC coupled differential input, figure 3.2,
if VIN is a 2Vp-p sinewave with –VIN 180 degrees out of phase
with VIN, then VIN+ is a 2Vp-p sinewave riding on a DC bias
voltage equal to VDC. Consequently, the converter will be at a
positive full scale when the VIN+ input is at VDC+1V and the
VIN– input is at VDC-1V (VIN+ - VIN– = 2V). Conversely, the ADS
will be at negative full scale when the VIN+ input is equal to
VDC-1V and VIN– is at VDC+1V (VIN+ - VIN– = –2V). Thus, the
converter has a peak-to-peak differential analog input voltage
range of ±2V.
An external reference may be used by connecting the external
voltage reference to the VRIN pin with VROUT left open. These
units are tested with VRIN equal to 3.5V.
In order to minimize overall converter noise it is recommended
that adequate high frequency decoupling be provided at the
VRIN pin.
Digital I/O and Clock
The analog input can be DC coupled, figure 3.3, as long as the
inputs are within the analog input common mode voltage range
(1.0V £ VDC £ 4.0V). The resistors, R, are not absolutely
necessary but may be used as load setting resistors. A
capacitor, C, connected from VIN+ to VIN– will help filter high
frequency noise. Values of approximately 20pF are normally
Analog Input,
VIN
The ADS-235, ADS-236 and ADS-237 provide a standard
high-speed interface to external TTL/CMOS logic families. In
order to ensure rated performance the duty cycle of the clock
should be held at 50% ±5%, have low jitter and operate at
standard TTL levels. Performance is guaranteed for conversion
5 n sec typ.
tAP
5 p sec typ.
tAJ
TPW1
TPWO
A/D CLK
1.5V
1.5V
tOD
tH
Data
Output
8 n sec typ.
8 n sec typ.
2.0V
N–1
0.5V
Figure 2B. Input-to-Output Timing
4
N
®
®
ADS-235, ADS-236, ADS-237
supplies and grounds. For best performance the supplies used
should be clean, linear regulated supplies. All power supplies
should be bypassed to ground with a 10uF tantalum capacitor
in parallel with a 0.1uF ceramic capacitor. Locate the bypass
capacitors as close to the converter as possible. If the converter
is to be powered from one supply then the analog supply and
ground pins should be isolated with ferrite beads from the
digital supply and ground pins. See the Typical Connection
Diagram, Figure 4.
rates above 0.5MHz in order to ensure proper performance of
the internal dynamic circuits.
Power Supplies and Grounding
The ADS-235, ADS-236 and ADS-237 have separate digital
and analog power supply pins and grounds (refer to the Input/
Output Connections table for pin numbers) to reduce digital
noise in the analog signal path. The digital data outputs also
have a separate supply pin, +DVS2, which can be powered
from either a 3.0V or 5.0V supply to allow the user the option
of interfacing with 3.0V logic.
In order to minimize overall converter noise it is recommended
that the VRIN pin be bypassed using a 4.7 uF tantalum capacitor
in parallel with a 0.01 uF ceramic capacitor. Locate the bypass
capacitors as close to the unit as possible.
The converters should be mounted on a board that provides
separate low impedance paths for the analog and digital
Figure 3.1 Analog Input Sample-and-Hold
Ø1
CH
Figure 3.2 AC Coupled Differential Input
VIN
Ø1
8
VIN+
CS
VIN+
Ø1
R
VOUT+
– +
Ø2
+ –
Ø1
VIN–
10 VDC
VOUT–
CS
R
–VIN
CH
Ø1
Ø1
9
Figure 3.3 DC Coupled Differential Input
Figure 3.4 AC Coupled Single Ended Input
VIN
8
VDC
VIN–
VIN+
8
VIN+
VIN
R
R
10
10 VDC
VDC
C
VDC
R
–VIN
9
VDC
VIN–
9
Figure 3.5 DC Coupled Single Ended Input
VIN–
Figure 3.6 Differential Analog Input Common
Mode Voltage Range
VIN
VDC
8
VIN+
+5V
VIN+
10 VDC
VIN+
C
+1.0<VDC<+4.0V
VDC
9
VIN–
2.0Vp-p
VIN–
VIN+
VDC=+1V
VIN–
Common Mode Voltage Range
2.0Vp-p
VDC=+4.0V
R
VIN–
2.0Vp-p
0V
Figure 3. Analog Input
5
Analog Input
Clock
6
Figure 4. Typical Connection diagram
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 12 (LSB)
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 (MSB)
ADS-235, ADS-236, ADS-237
®
®
®
®
ADS-235, ADS-236, ADS-237
5-1 Power Dissipation VS Temperature
5-2 Power Supply Current VS Temperature
5-3 VROUT VS Temperature and Load
BITS
5-4 ENOB VS Input Frequency
5-5 SINAD VS Input Frequency
5-6 THD VS Input Frequency
5-7 SFDR VS Input Frequency
5-8 ADS-236 FFT
5-9 ADS-237 FFT
Frequency Bin
Frequency Bin
Figure 5. Typical Performance Curve
7
®
®
ADS-235, ADS-236, ADS-237
Table 1. Output Coding
BIPOLAR
SCALE
DIFFERENTIAL
INPUT VOLTAGE
(using internal
reference)
+FS-1/4LSB
+FS-1¼LSB
+3/4 LSB
–1/4 LSB
–FS+1¾LSB
–FS+3/4 LSB
+1.99976V
+1.99878V
+732.4µV
–244.1µV
–1.99829V
–1.99927V
OFFSET
BINARY
MSB
1111
1111
1000
0111
0000
0000
LSB
1111
1111
0000
1111
0000
0000
1111
1110
0000
1111
0001
0000
MECHANICAL DIMENSIONS INCHES (mm)
ADS-235S
ADS-236S
ADS-237S
28 Lead Wide Body Versions
SMALL OUTLINE PLASTIC PACKAGES (SOIC)
N
E
INDEX AREA
H
-B-
L
1
INCHES
2 3
MILLIMETERS
SEATING PLANE
-A-
SYMBOL
D
h × 45°
-C-
A
e
B
C
A1
0.25(0.010) M A M B S
0.10(0.004)
Notes:
1. Controlling dimensions: MILLIMETER. Converted inch dimensions
are not necessarily exact.
2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold
flash, protrusions and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
3. Dimension "E" does not include interlead flash or protrusions. Interlead flash and
protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index feature must be
located within the crosshatched area.
5.
"L" is the length of terminal for soldering to a substrate.
6. Terminal numbers are shown for reference only.
7. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane,
shall not exceed a maximum value of 0.61mm (0.024 inch).
MIN.
MAX.
MIN.
MAX.
A
0.0926
0.1043
2.35
2.65
A1
0.0040
0.0118
0.10
0.30
B
0.013
0.0200
0.33
0.51
C
0.0091
0.0125
0.23
0.32
D
0.6969
0.7125
17.70
18.10
E
0.2914
0.2992
7.40
7.60
e
0.05 BSC
1.27 BSC
H
0.394
0.419
10.00
10.65
h
0.01
0.029
0.25
0.75
L
0.016
0.050
0.40
N
a
28
0°
1.27
28
8°
0°
8°
ORDERING INFORMATION
®
MODEL NUMBER
OPERATING
TEMP. RANGE
ADS-235S
ADS-236S
ADS-237S
0 to +70°C
–45 to +85°C
–45 to +85°C
SAMPLING
FREQUENCY
5MHz
5MHz
9MHz
ISO 9001
®
R E G I S T E R E D
DS-0409A
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151
Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356
Internet: www.datel.com Email: [email protected]
05/01
DATEL (UK) LTD. Tadley, England Tel: (01256)-880444
DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 01-34-60-01-01
DATEL GmbH München, Germany Tel: 89-544334-0
DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-6354-2025
DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein
do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.