NJRC NJU6541A

Preliminary
NJU6541A
Static 1/2 1/3 1/4 Duty LCD Driver
! GENERAL DESCRIPTION
! PACKAGE OUTLINE
The NJU6541A is a Static or 1/2,1/3,1/4 duty segment
type LCD driver. It incorporates 4 common driver circuits
and 120 segment driver circuits. The NJU6541A can
drive maximum 480 segments in 1/4 duty ratio, and can
2
use I C F/S mode.
In addition, the NJU6541A's useful functions meet a
wide range of applications.
! FEATURES
NJU6541A
# LCD driving circuit
:Max. 120outputs (4 outputs as for general purpose ports)
# Programmable Duty Ratio
Static
:Driving max. 120 segments
1/2 Duty Ratio
:Driving max. 240 segments
1/3 Duty Ratio
:Driving max. 360 segments
1/4 Duty Ratio
:Driving max. 480 segments
# General Purpose Port :Driving max 4outputs (SEG1-SEG4:4outputs as for general purpose ports)
# Key Scan Function
:Max 30Key(5-out x 6-in matrix)
# Programmable Bias Ratio
:1/2, 1/3 bias ratio (Static:1/1)
2
# I C-bus Interface
:F/S mode slave address 0111_000*
(*: Read/ Write mode distinction: 0=write, 1=read)
# Oscillator
:CR oscillation with external resistor and capacitance, or external oscillation
signal input
#
#
#
#
Operating Wave Form :A wave form, B wave form
Electrical Variable Resistance :8-steps
Power ON Initialize Circuit On-Chip
Useful Instruction Set
:Duty select, Bias select, Wave form select, Oscillation select, Segment or general
purpose ports select, Segment or Key scan output select, E.V.R select,
Display ON/OFF, Key scan ON/OFF
# Operating Voltage
:3.0V / 5.0V
# C-MOS Technology
:P-Sub
# Package Outline
:LQFP144 20mm*20mm t=1.7mm(max) Pin-pitch=0.5mm
! BLOCK DIAGRAM
REQ
S5 K1- K6
COM1
COM4
SEG1/P1
SEG4/P4
SEG5
SEG115 SEG117/S1 SEG120/S4
VDD
V0
EVR
Key Scan
Common
Driver
Segment Driver
V1
V2
Latch
V3
VSS
OSC
Display Reg
OSC
SDA
2
DNC
I C Control
Decoder
Command Reg
VSS
SCL
RSTB
Power ON Reset
TEST
Ver.2009-04-02
-1-
Preliminary
NJU6541A
! PIN CONFIGURATION
73
75
74
76
77
79
78
80
82
81
83
85
84
87
86
90
89
88
91
94
93
92
95
100
99
98
97
96
102
101
103
104
106
105
107
108
SEG69
SEG104
• QFP144
SEG68
SEG67
72
71
111
SEG66
112
SEG65
70
69
113
114
SEG64
SEG63
SEG62
68
67
SEG61
SEG60
65
109
110
SEG105
115
116
117
118
119
120
SEG59
SEG58
121
122
SEG116
SEG117/S1
SEG118/S2
123
124
SEG120/S4
SEG57
61
56
55
K1
K2
128
62
58
57
S5
127
64
63
60
59
NJU6541A
SEG119/S3
125
126
65
54
53
131
K6
50
132
V0
49
133
134
V1
V2
48
47
135
136
V3
46
VSS
45
137
138
OSC
TEST
44
43
139
140
REQ
RSTb
42
41
141
142
DNC
SDA
40
39
143
144
SCL
VDD
38
37
-2-
SEG32 36
34
35
33
32
30
31
29
27
28
26
24
25
22
23
19
20
21
18
17
16
15
SEG7 11
SEG8 12
SEG9 13
SEG10 14
SEG3/P3 7
SEG4/P4 8
SEG5 9
SEG6 10
SEG33
3
4
SEG1/P1 5
SEG2/P2 6
2
52
51
COM1
COM2
COM3
COM4
1
129
130
K3
K4
K5
Ver.2009-04-02
Preliminary NJU6541A
! TERMINAL DISCRIPTION
No.
Pad Name
Function
LCD driving voltage
132
V0
133
134
135
V1
V2
V3
136
VSS
137
OSC
138
TEST
139
REQ
Request operation outputs for Key scan
140
RSTb
Reset
When RSTb is “L", command register and latch circuit is reset.
When this terminal is not used, should be VDD short. (keep power supply
condition when hardware reset circuit is used)
141
142
143
144
1-4
DNC
SDA
SCL
VDD
COM1 ~ COM4
5-8
SEG1/P1~SEG4/P4
9~120
SEG5 ~ SEG116
121~124
SEG117/S1 ~
SEG120/S4
125
126~131
S5
K1 ~ K6
Ver.2009-04-02
V0 ≥VDD
Bias
At 1/3 bias ratio, keep V2- V3 open.
At 1/2 bias ratio, short V2- V3.
GND
VSS =0V
External resistor and capacitance connection terminal for CR oscillation, or
external clock input terminal
TEST
Keep TEST-VSS short
Don’t connect
2
I C Serial data I/O terminal
Serial data Transmission clock input
Power supply: 3V /5V
Common driver outputs
Segment driver outputs/general purpose output ports
These 4 terminals can be used as segment outputs or general
purpose output ports by setting Command Register.
When selected as general purpose ports, data can be outputted via
these ports during COM1 timing.
According to transferred data, "H"=VDD or "L"=VSS will be outputted.
Segment driver outputs
Segment driver outputs / Key scanning output
These 4 terminals can be used as segment outputs or Key scanning
output terminal by the instruction.
Key scanning output
Key scanning inputs
-3-
NJU6541A
Preliminary
! FUNCTION DESCRIPTION
(1) Block Function
• Interface
2
I C Interface circuit. F/S mode control
•
Oscillator
The oscillator includes an external capacitor and an resistor.
When use external clock, input the clock signal to OSC.
It generates clock signal for LCD driving.
•
Decoder
Input serial data is decoded and sent to the appropriate block.
•
Command Register
Command data is written to this 8 bits command register to control the NJU6541A operation.
•
Display Data Register
Data is written to this 8 bits register as display data.
•
Latch Circuit
Data stored in display data register is assigned to the corresponding SEG/port.
•
Segment Driver/Key scan/General Purpose Ports
Basing on display data, segment drivers output LCD SEG driving signal.
And, SEG1/P1 ~ SEG4/P4 terminals can be selected as segment driver output or general-purpose ports by
instruction, SEG117/S1~SEG120/S4 terminals can be selected as segment driver output or Key scan outputs
by instruction.
•
Common Driver
Common drivers output LCD COM driving signal.
•
Power On Reset
When power is on, The NJU6541A is automatically initialized. And if RSTb=”L”, The NJU6541A is reset
too.
•
Electrical Variable Resistance (E.V.R.)
The Electrical Variable Resistance adjusts LCD Driving Voltage from V1 to V3.
•
Key scan
The Key scan controls to input from external Key data.
-4-
Ver.2009-04-02
Preliminary NJU6541A
2
(2) I C Serial Data Transfer
2
The NJU6541A transfer of data comply with I C specification.
Data format is show below(Fig1). After input the slave address, the input of the instruction data or the display
data becomes possible.
S
Slave address
SCL
1
2
Write
A
8
9
1
2
3
8
9
1
2
3
8
9
RW
ACK
D7
D6
D5
D0
ACK
D7
D6
D5
D0
ACK
7
SDA
MSB
S: Start condition
A: Acknowledge
P: Stop condition
Sｒ: Repeat start condition
LSB
Instruction
A
MSB
Instruction
LSB
A
MSB
P
LSB
Fig1
After input the instruction data, It becomes possible to write the display data continuously by setting the
display address.
S
Slave address
SCL
1
2
7
SDA
MSB
S: Start condition
A: Acknowledge
P: Stop condition
Sｒ: Repeat start condition
Write
A
8
9
1
2
3
8
9
1
2
3
8
9
1
2
3
8
9
RW
ACK
D7
D6
D5
D0
ACK
D7
D6
D5
D0
ACK
D7
D6
D5
D0
ACK
LSB
Instruction
A
MSB
LSB
Address set
A
MSB
Display data
LSB
MSB
A
P
LSB
Fig2
However, after setting the display address, it becomes possible to input only the display data. Therefore, the
acceptance of the instruction data is impossible as long as the repeat start condition or the stop condition is
not executed.
Display data
SCL
A
Slave address
A
Instruction
A
1
2
3
8
9
1
2
3
8
9
1
2
3
8
9
D7
D6
D5
D0
ACK
D7
D6
D5
D0
ACK
D7
D6
D5
D0
ACK
SDA
MSB
S: Start condition
A: acknowledge
P: Stop condition
Sｒ: Repeat start condition
LSB
MSB
LSB
MSB
LSB
Fig3
1) Start condition
A fall edge of the SDA terminal while the SCL terminals “H”, which situation define the Start conditions.
2) Slave address
First bite defines the slave address of the NJU6541A. Slave address is (0111_000*). When the NJU6062
acknowledge coincidence its own address with the address in the first byte, it output the acknowledge just
the first byte( at ninth bit timing) through the SDA terminal.
3) Read/Write condition
The data is R/W signal in the first byte( at eighth bit timing) . The eighth bit timing “H” is write. The eighth
bit timing “L” is read.
4) Data
After 2nd bite, transfer the display bite. After input the slave address, the input of the instruction data or
the display data(series) becomes possible.
5) Stop condition
A rise edge of the SDA terminal while the SCL terminal is “H”, which situation defines the STOP condition.
6) Repeat start condition
After start condition set, a fall edge of the SDA terminal while the SCL terminals “H”, which situation next
data read start.
Ver.2009-04-02
-5-
Preliminary
NJU6541A
Note)
The NJU6541A read the rising edge of SCL after eight clock. When the master execute stop condition after eighth
clock(before ACK ), eighth data is valid. However, when the master execute stop condition under eight clock, data
is invalid.
8 bit data
SCL
P
1
2
3
8
D7
D6
D5
D0
7bitdata（7
SCL
Bit or less）
P
1
2
3
7
D7
D6
D5
D1
SDA
SDA
MSB
S: Start condition
A: Acknowledge
P: Stop condition
Sｒ: Repeat start condition
MSB
LSB
S: Start condition
A: Acknowledge
P: Stop condition
Sｒ: Repeat start condition
8 bitData valid
Fig4
LSB
8 Bit under data is invalid
Fig5
Instruction
Code
Instruction
Content
D7
D6
D5
D4
D3
D2
D1
D0
Command
Register1
1
0
0
0
EXOSC
KEY2
KEY1
KEY0
Command
Register2
1
0
0
1
WSEL
TSEL2
TSEL1
TSEL0
Command
Register3
1
0
1
0
BS
E2
E1
E0
Command
Register4
1
0
1
1
SK1
SK0
DS1
DS0
Address counter
0
1
Ｃ1
Ｃ0
S3
S2
S1
S0
-6-
・FOSC select
・Segment/ Key scan select
・Operating wave form
・ Segment/ general output
select
・Bias select
・E.V.R select
・Display control
・Key scan ON/OFF
・Duty select
・Output address register
Ver.2009-04-02
Preliminary NJU6541A
Command Register1
Command Register1 is used to set the duty ratio, the bias ratio, and the SEG driver/Key scan.
st
When the D7 ~ D4 bits of the 1 word are (1,0,0,0), the D3 ~ D0 bits are recognized as command data1.
The contents of Command Register will be initialized as following when applying Power On Reset or Reset.
The Default Value of Command Register
• SEG driver/Key scan : SEG drivers(SEG117,SEG118, SEG119, SEG120)
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
EXOSC
KEY2
KEY1
KEY0
Flag bits
•
•
Oscillator selection
EXOSC
0
1
Oscillator
selection
SEG driver or Key scan selection
Oscillator circuit
External resistor and capacitor
External oscillation signal input
SEG driver or Key scan
KEY2
KEY1
KEY0 SEG117/K1 SEG118/K2 SEG119/K3 SEG120/K4
0
0
0
SEG117
SEG118
SEG119
SEG120
0
0
1
SEG117
SEG118
SEG119
K4
0
1
0
SEG117
SEG118
K3
K4
0
1
1
SEG117
K2
K3
K4
1
0
0
K1
K2
K3
K4
*) If KEY2 ~ KEY0 is set to (1, 0, 1), (1, 1, 0), (1, 1, 1) all outputs are used as segment drivers.
Ver.2009-04-02
-7-
Preliminary
NJU6541A
(5) Command Register2
Command Register2 is used to set the duty ratio, the bias ratio, and the SEG driver/general purpose ports.
st
When the D7 ~ D4 bits of the 1 word are (1,0,0,1), the D3 ~ D0 bits are recognized as command data2.
The contents of Command Register will be initialized as following when applying Power On Reset or Reset.
The Default Value of Command Register
• SEG driver/General purpose ports
: SEG drivers(SEG1,SEG2, SEG3, SEG4)
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
WSEL
TSEL2
TSEL1
TSEL0
Flag bits
Driving
wave form
SEG driver or General purpose ports selection
•
Driving waveform
Driving waveform is chosen according to the characteristic of a panel.
WSEL
Driving waveform
0
A(Time sharing system frequency) waveform
1
B(Flame reversal) waveform
*) Do not change the driving waveform during display ON.
•
SEG driver or General purpose ports
TSEL2 TSEL1 TSEL0
SEG1/P1
SEG2/P2
SEG3/P3
SEG4/P4
0
0
0
SEG1
SEG2
SEG3
SEG4
0
0
1
SEG1
SEG2
SEG3
P4
0
1
0
SEG1
SEG2
P3
P4
0
1
1
SEG1
P2
P3
P4
1
0
0
P1
P2
P3
P4
*) If TSEL2 ~ TSEL0 is set to (1, 0, 1), (1, 1, 0), (1, 1, 1) all outputs are used as segment drivers.
-8-
Ver.2009-04-02
Preliminary NJU6541A
(6) Command Register3
st
• Command Register3 is used to set the Bias ratio and E.V.R. resister set. When the D7 to D4 bits of the 1
• word are (1,0,1,0), the D3 ~ D0 bits are recognized as command data3.
The contents of Command Register will be initialized as following when applying Power On Reset or Reset.
The Default Value of Command Register
• Oscillator selection
• Bias ratio selection
• E.V.R. Register Set
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
BS
E2
E1
E0
Bias ratio
Flag bits
•
: External resistor and capacitor
: 1/3
: V0(0,0,0)
E.V.R. register set
Bias ratio
BS
0
1
Bias ratio
1/3
1/2
*) Do not change the Bias ratio during display ON.
**)If Bias is set to 1/2, short V2-V3.
**)If 1/1 Duty is select, Bias is set to 1/1 Bias regardless of Bias ration selection.
•
E.V.R. resister set
E.V.R. resistor set instruction adjusts the contrast of the LCD, by 3-bits selects(E2,E1,E0).
One LCD driving voltage VLCD out of 8 voltage-stages by setting E.V.R. register.
Set the binary code “000” when contrast adjustment is unused.
V1
E2
E1
E0
V0 (V0~VSS )
1/2bias
1/3bias
0
0
0
0
1
1
1
1
Ver.2009-04-02
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V0
0.933V 0
0.875V 0
0.824V 0
0.778V 0
0.737V 0
0.700V 0
0.667V 0
V0
0.955V 0
0.913V 0
0.875V 0
0.840V 0
0.808V 0
0.778V 0
0.750V 0
High
:
:
:
:
:
:
Low
-9-
Preliminary
NJU6541A
(7) Command Register4
• Command Register4 is used to set the Key scan ON/OFF, Display ON/OFF, Duty ratio. When the D7 to D4 bits
st
of the 1 word are (1,0,1,1), the D3 ~ D0 bits are recognized as command data4.
The contents of Command Register will be initialized as following when applying Power On Reset or Reset.
The Default Value of Command Register
• Display control
• Key scan ON/OFF selection
• Duty ratio selection
: Display ON
: Key scan OFF
: 1/4 Duty
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
SK1
SK0
DS1
DS0
Flag bits
Key scan ON/OFF
Display ON/OFF
Duty ratio
•
Display control and Key scan ON/OFF
It is used to set the Key scan ON/OFF, Display control.
The Oscillator circuit stop(OFF) only when the Display and Key scan are OFF((SK1,SK0)=(0,0)).
The Key-input is not accepted at all when Key scan is OFF.
Even during Display OFF, interface can be accessed, and data can be written into the command
register, address counter and data register
SK1
SK0
Display
Key scan
Oscillator
0
0
OFF
OFF
OFF
0
1
OFF
ON
ON
1
0
ON
OFF
ON
1
1
ON
ON
ON
*) When Display OFF
• All segment and common terminal output are VSS
(When general purpose output ports are selected, even Display OFF, these ports can output data)
• V1 , V2 and V3 become V0 (no current pass through the bleeder resistors)
•
Duty ratio
!
It is used to set the Duty selection. When duty select 1/1, Bias is 1/1,
between from V1 to Vss.
!
DS1
DS0
Duty ratio
0
0
1/4
0
1
1/3
1
0
1/2
1
1
1/1
*) Do not change the duty ratio during display ON.
- 10 -
breeder resostance is open
Ver.2009-04-02
Preliminary NJU6541A
(8) Output Address Counter
Output Address Counter will specify the addresses of the SEG and COM drivers for the display data.
st
When the MSB (D7 to D6) of the 1 data is “01”, the LSB 6 bits (D5 to D0) specify the addresses of COM and
nd
st
SEG drivers, and the 2 data is the display data which will be sent to the 1 -data-specified drivers. At the
same time, SEG and COM driver addresses will be increased automatically shown in Table 1. In other words,
as of the SEG and COM driver addresses specified by the first data in the Output Address Counter, display
data can be transferred to the SEG and COM drivers without further address setting.
The address setting range is from "00_0000" to "11_1110. if the data transferred additionally , then it will be
reset to “00_0000” and renew the auto-increment operation. If it set the data without range by Duty select, the
data can not show the display.
Output Address counter default setting
Output Address counter
(C1, C0, S3, S2, S1, S0)=(0, 0, 0, 0, 0, 0)
•
Address Data
D7
0
D6
D5
D4
D3
D2
D1
D0
1
C1
C0
S3
S2
S1
S0
Flag bits
COM driver Address
SEG driver Address
Address range depend on Duty
DUTY
1/1
1/2
1/3
1/4
Address range
00_0000～00_1110
00_0000～01_1110
00_0000～10_1110
00_0000～11_1110
Address range＝[C1][C0]_[S3][S2][S1][S0]
Ver.2009-04-02
- 11 -
Preliminary
NJU6541A
Increment Direction
Table 1. The Relationship Between Output Address and SEG/COM Drivers
C1
C0
S3
S2
S1
S0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
#
#
#
- 12 -
COM
Driver
COM1
COM2
COM3
COM4
D7
SEG1
SEG9
SEG17
SEG25
SEG33
SEG41
SEG49
SEG57
SEG65
SEG73
SEG81
SEG89
SEG97
SEG105
SEG113
SEG1
SEG9
SEG17
SEG25
SEG33
SEG41
SEG49
SEG57
SEG65
SEG73
SEG81
SEG89
SEG97
SEG105
SEG113
SEG1
SEG9
SEG17
SEG25
SEG33
SEG41
SEG49
SEG57
SEG65
SEG73
SEG81
SEG89
SEG97
SEG105
SEG113
SEG1
SEG9
SEG17
SEG25
SEG33
SEG41
SEG49
SEG57
SEG65
SEG73
SEG81
SEG89
SEG97
SEG105
SEG113
D6
SEG2
SEG10
SEG18
SEG26
SEG34
SEG42
SEG50
SEG58
SEG66
SEG74
SEG82
SEG90
SEG98
SEG106
SEG114
SEG2
SEG10
SEG18
SEG26
SEG34
SEG42
SEG50
SEG58
SEG66
SEG74
SEG82
SEG90
SEG98
SEG106
SEG114
SEG2
SEG10
SEG18
SEG26
SEG34
SEG42
SEG50
SEG58
SEG66
SEG74
SEG82
SEG90
SEG98
SEG106
SEG114
SEG2
SEG10
SEG18
SEG26
SEG34
SEG42
SEG50
SEG58
SEG66
SEG74
SEG82
SEG90
SEG98
SEG106
SEG114
D5
SEG3
SEG11
SEG19
SEG27
SEG35
SEG43
SEG51
SEG59
SEG67
SEG75
SEG83
SEG91
SEG99
SEG107
SEG115
SEG3
SEG11
SEG19
SEG27
SEG35
SEG43
SEG51
SEG59
SEG67
SEG75
SEG83
SEG91
SEG99
SEG107
SEG115
SEG3
SEG11
SEG19
SEG27
SEG35
SEG43
SEG51
SEG59
SEG67
SEG75
SEG83
SEG91
SEG99
SEG107
SEG115
SEG3
SEG11
SEG19
SEG27
SEG35
SEG43
SEG51
SEG59
SEG67
SEG75
SEG83
SEG91
SEG99
SEG107
SEG115
SEG Driver
D4
D3
SEG4
SEG5
SEG12
SEG13
SEG20
SEG21
SEG28
SEG29
SEG36
SEG37
SEG44
SEG45
SEG52
SEG53
SEG60
SEG61
SEG68
SEG69
SEG76
SEG77
SEG84
SEG85
SEG92
SEG93
SEG100
SEG101
SEG108
SEG109
SEG116
SEG117
SEG4
SEG5
SEG12
SEG13
SEG20
SEG21
SEG28
SEG29
SEG36
SEG37
SEG44
SEG45
SEG52
SEG53
SEG60
SEG61
SEG68
SEG69
SEG76
SEG77
SEG84
SEG85
SEG92
SEG93
SEG100
SEG101
SEG108
SEG109
SEG116
SEG117
SEG4
SEG5
SEG12
SEG13
SEG20
SEG21
SEG28
SEG29
SEG36
SEG37
SEG44
SEG45
SEG52
SEG53
SEG60
SEG61
SEG68
SEG69
SEG76
SEG77
SEG84
SEG85
SEG92
SEG93
SEG100
SEG101
SEG108
SEG109
SEG116
SEG117
SEG4
SEG5
SEG12
SEG13
SEG20
SEG21
SEG28
SEG29
SEG36
SEG37
SEG44
SEG45
SEG52
SEG53
SEG60
SEG61
SEG68
SEG69
SEG76
SEG77
SEG84
SEG85
SEG92
SEG93
SEG100
SEG101
SEG108
SEG109
SEG116
SEG117
D2
SEG6
SEG14
SEG22
SEG30
SEG38
SEG46
SEG54
SEG62
SEG70
SEG78
SEG86
SEG94
SEG102
SEG110
SEG118
SEG6
SEG14
SEG22
SEG30
SEG38
SEG46
SEG54
SEG62
SEG70
SEG78
SEG86
SEG94
SEG102
SEG110
SEG118
SEG6
SEG14
SEG22
SEG30
SEG38
SEG46
SEG54
SEG62
SEG70
SEG78
SEG86
SEG94
SEG102
SEG110
SEG118
SEG6
SEG14
SEG22
SEG30
SEG38
SEG46
SEG54
SEG62
SEG70
SEG78
SEG86
SEG94
SEG102
SEG110
SEG118
D1
SEG7
SEG15
SEG23
SEG31
SEG39
SEG47
SEG55
SEG63
SEG71
SEG79
SEG87
SEG95
SEG103
SEG111
SEG119
SEG7
SEG15
SEG23
SEG31
SEG39
SEG47
SEG55
SEG63
SEG71
SEG79
SEG87
SEG95
SEG103
SEG111
SEG119
SEG7
SEG15
SEG23
SEG31
SEG39
SEG47
SEG55
SEG63
SEG71
SEG79
SEG87
SEG95
SEG103
SEG111
SEG119
SEG7
SEG15
SEG23
SEG31
SEG39
SEG47
SEG55
SEG63
SEG71
SEG79
SEG87
SEG95
SEG103
SEG111
SEG119
D0
SEG8
SEG16
SEG24
SEG32
SEG40
SEG48
SEG56
SEG64
SEG72
SEG80
SEG88
SEG96
SEG104
SEG112
SEG120
SEG8
SEG16
SEG24
SEG32
SEG40
SEG48
SEG56
SEG64
SEG72
SEG80
SEG88
SEG96
SEG104
SEG112
SEG120
SEG8
SEG16
SEG24
SEG32
SEG40
SEG48
SEG56
SEG64
SEG72
SEG80
SEG88
SEG96
SEG104
SEG112
SEG120
SEG8
SEG16
SEG24
SEG32
SEG40
SEG48
SEG56
SEG64
SEG72
SEG80
SEG88
SEG96
SEG104
SEG112
SEG120
If general purpose ports are selected by Command Register, under (C1, C0, S3, S2, S1, S0)=(0, 0, 0,
0, 0, 0), D4 ~ D7 bits are the addresses of (P1, P2, P3, P4) ports which corresponds to (SEG1,SEG2,
SEG3, SEG4).
When SEG1~SEG4 are set as general purpose output ports, data for SEG1~SEG4 during
COM2~COM4 scanning will be ignored.
When SEG117~SEG120 are set as Key ports, data for SEG117~SEG120 will be ignored.
Ver.2009-04-02
Preliminary NJU6541A
(9) Power ON Reset
After power ON, NJU6541A is initialized to the following values:
• Address counter
(C1, C0, S3, S2, S1, S0)=(0, 0, 0, 0, 0, 0)
• Display data register
all "0"
• Duty ratio
1/4 duty
• Bias ratio
1/3 bias
• Oscillator selection
External resistor and capacitor
• Driving waveform
A waveform
• E.V.R. resister
V0(E2, E1, E0)=(0, 0, 0)
• Segment/General purpose port
Segment output(SEG1,SEG2, SEG3, SEG4)
• Segment/Key scan
Segment output(SEG117,SEG118, SEG119, SEG120)
• Display
OFF
• Key scan
OFF
(10) Sequence of Initialization
1/4 duty,1/3 bias,SEG1 ~ SEG4 used as SEG drivers, SEG117 ~ SEG120, external resister and capacitor, B
waveform, E.V.R. V0(E2, E1, E0)=(0, 0, 0) data written in from COM1.
Power on
Set Command Resister1
D7
1
D6
0
D5
0
D4
0
D3
0
D2
1
D1
0
D0
0
External R&C
K1 ~ K4
Set Command Register2
D7
1
D6
0
D5
0
D4
1
D3
1
D2
0
D1
0
D0
0
B waveform
Segment port
Set Command Register3
D7
1
D6
0
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
Set output address
D7
0
D6
1
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
D7 D6
1
0
D5
1
D4
1
D3
1
D2
1
D1 D0 Display ON, Key scan ON
0
0 1/4 Duty, O.S.C ON
1/3 Bias
V0(E2, E1, E0)=(0, 0, 0)
COM driver address =00
SEG driver address=0000
Display data written in
Set Command Register4
Ver.2009-04-02
- 13 -
NJU6541A
Preliminary
(10) LCD driving voltage generation circuit
LCD driving voltage generation circuit generates LCD driving bias voltages V1 , V2 and V3. It adjusts
the voltage by 8 steps electrical volume from V0 and allots the voltage to V0, V1 , V2 and V3 by
resistor-voltage-dividing as shown in below.
V0, V1, V2 and V3 terminals requires external capacitors for bias voltage stabilization for display quality.
These values of capacitors should be fixed in accordance with evaluation in the application.
NJU6541A internal
E.V.R (8steps)
V0
4kohm(typ.)
V1
4kohm(typ.)
V2
4kohm(typ.)
VLCD
V3
4kohm(typ.)
VSS
Fig6
When the E.V.R. is not used, V1 terminal should connect to V0.
When the NJU6541A operates as 1/2 bias operation, V2 terminal should connect to V3.
When it select 1/1 duty, between V1 and Vss do not pass current by COS switch open.
(11) Oscillator circuit
The oscillator includes an external capacitor and an resistor.
When use external clock, input the clock signal to OSC.
It generates clock signal for LCD driving.
VDD
390kOhm
NJU6541A
OSC
120pF
(fOSC=15.4kHz TYP)
Fig7
- 14 -
Ver.2009-04-02
Preliminary NJU6541A
(12) Keyscan circuit
The Key scan circuit consists of a detector block of key pressing and a fetching block of key status. It
scans 5x6 key matrix and fetches conditions of 30 keys. Furthermore, it operates correctly against the key
roll over input.
Key matrix
NJU6541A
K6 K5 K4 K3 K2 K1
S5 S4 S3 S2 S1
ON
OFF
Fig8
(12-1) Timing of Key scan
Key scan cycle is 160 x T[S](T=1/fosc). The data of key scan is a result of comparison with a couple of
Key scan for correct judge whether Key On or Off. When the result of comparison is correct (accord), the
NJU6541A recognizes Key On and outputs “L” level from REQ terminal after 416 x T[S] from start of Key
scan for a request to read key data out to external CPU. When the REQ terminals outputs “L” signal, the
key scan does not operate until end of key data reading by CPU, and scanned key data is kept. When
the result of comparison is incorrect (not accord), Key scan operates again if any key is On. It read Key
scan data without regard to REQ “H” or “L”.
Key turn
turn ON
Key knowledge
Key scan start
Key data fix
REQ signal output
fosc
64×T[s]
64 T[s]
Key scan clock
（Internal signal）
signal）
S1
S2
S3
1
1
2
2
3
3
S4
4
S5
4
5
5
2nd Key scan
1st Key scan
160×T[s]
REQ
Max416×T[s]
Fig9
Ver.2009-04-02
- 15 -
NJU6541A
Preliminary
12-2) Request signal output
When the NJU6541A detect the key-in to scan start by the key scan circuit, it outputs “L” signal as the
request signal from the “REQ” terminal to notice the key pressing information to an application system.
The request signal resets to “H” level after key scan data read.
12-3) Contents of key register renewal
Contents of key register are no fixed in case of no key operation.
Contents of key register are not changed in busy of key data reading operation.
It stops when a couple of data by continuously twice key scan operations are accorded and fixed as a
correct key status. The correct key status data is stored and newly key scan operation does not start
until external CPU reads data out after key status is fixed.
When a key on the key matrix is pressed, the bit corresponding to terminals (S1 to S5, K1 to K6)
connected the switch goes to “1” and another bits go to “0”.
In case of Example 1, when the switch connecting to K5 and S5 is pressed, bit (KD29) corresponding to
S5 and K5 go to “1” but another bits go to “0”.
Example 1. One key is pressed
Key matrix
K6 K5 K4 K3 K2 K1
NJU6541A
S5 S4 S3 S2 S1
ON
OFF
Fig10
Key register
S1
S2
S3
S4
S5
K1
KD1
KD7
KD13
KD19
KD25
K2
KD2
KD8
KD14
KD20
KD26
K3
KD3
KD9
KD15
KD21
KD27
K4
KD4
KD10
KD16
KD22
KD28
K5
KD5
KD11
KD17
KD23
KD29
K6
KD6
KD12
KD18
KD24
KD30
12-4) Format of Key scan data
Key register data was outputted by I2C bus. Key register reading is two method, one is REQ signal
method, another is a method of always requesting reading.
12-4-1) REQ signal method
When there is "Read" mastering request when REQ is "L", after the slave address is specified, the
method of outputting data outputs the key register data to KD30-KD1 separately for five of every eight
bits (upper 2bits is dummy data =”H”) data. NJU6541A doesn't reset the data of the Key register until all
the Key register data of KD30-KD1 is sent to the master, and the stop condition is executed. The key
input is not accepted. The ACK data is not sent from the master, and data in the key register is
maintained when ending on the way of the data transfer. The key data is output from KD30 when the
master reads NJU6541A the key data again.
12-4-2) REQ signal is not used.
NJU6541A can transmit the data of the key register If reading is requested by the master when the REQ
signal is "H".
- 16 -
Ver.2009-04-02
Preliminary NJU6541A
When the key is pushed
: The key register is maintained until reading the key data is completed.
When the key is not pushed : "L" is output.( NJU6541A doesn't output the data of the key register, and
"L" is output. All the time, "L" is output to the master though the key data is maintained in the key register
when the key is pushed. When the key data is read again after reading ends, the data of the key register
is output.)
12-5) Example of Key scan output
After the slave address is fixed, the data of the key register is output from KD30. The first two bits are
the dummy data(“H”) at the key register data transfer. Six bits are three bit key data from now on.
This is forwarded five times, and the data of 30 keys is transmitted. The terminal REQ is fixed to "H"
when the STOP condition is executed after key register 1-5 is transmitted, and all data in the key register
is fixed to "L".
REQ
S
SCL
Slave address
1
2
SDA
MSB
S: Start condition
A: Acknowledge
P: Stop condition
Sｒ: Repeat start condition
7
Read
A
8
9
1
2
3
8
9
1
2
3
8
9
RW
ACK
*
*
KD30
KD24
ACK
*
*
KD6
KD1
ACK
LSB
Key register data1
A
MSB
Key register data5
LSB
MSB
A
LSB
Fig11
12-6) Key More Input
non-pressed key data may change pressed key data in triple or more key Input as shown in Fig. 1 and
incorrect key data may be output to external CPU. For prevention of miss-recognition by incorrect key
data, diodes should be inserted or control program of CPU should ignore the combination of key data
miss-recognition. For example, 4 keys and more ON data should be ignored.
In case of 3 keys operation in left
picture, if S4 terminal outputs “L”
signal, this signal goes around on
the dotted line and non-pressed key
is miss-recognized as pressed
key.
NJU6541
K6 K5 K4 K3 K2 K1
S5 S4 S3 S2 S1
Pressed key
Miss-recognized key
Miss-recognized route
Fig12
Ver.2009-04-02
- 17 -
P
Preliminary
NJU6541A
For prevention of miss-recognition
by incorrect key data, diodes should
be inserted. An precision key can be
recognized.
NJU6541A
NJU6541A
K6 K5 K4 K3 K2 K1 S5 S4 S3
S2 S1
Pressed key
Miss-recognized route
Fig13
NJU6541
NJU6541
K6 K5 K4 K3 K2 K1
S5 S4 S3 S2 S1
K6 K5 K4 K3 K2 K1
S5 S4 S3 S2 S1
Pressed key
Pressed key
NJU6541
K6 K5 K4 K3 K2 K1
S5 S4 S3 S2 S1
Pressed key
Fig14
12-7) Key scan OFF mode
Key scan operation is turned ON or OFF by the instruction. After the scanning ends, the key scanning is
turned off. The request signal is output until reading out data even if the turn off command enters while
scanning the key. The REQ signal outputs "L" if it reads out data. The REQ signal doesn't change into
"H" until reading out data though the key scan stops when the REQ signal inputs the key scan on
instruction by "L" after scan the key. The key register data can be reading in case of either case.
- 18 -
Ver.2009-04-02
Preliminary NJU6541A
12-8) Key scan operates shown as follows
1, Key scan signal output terminals S1 – S5 output “L” signals when key scan does not operate, and output
key scan signals after start of key scan operation. The conditions of key scan signal input terminals K1 –
K6 are “H” state with internal pull-up resistances, though “L” signal comes in to K1 – K6 corresponding to
the turned on keys.
2, The function of key scan starts twice operations when any key is turned on. It stops when a couple of
data by continuously twice key scan operations are accorded and fixed as a correct key status. It
operates more 2 times when the key status is not fixed and any keys are still turning on. It repeats again
and again until key status is fixed. The correct key status data is stored and newly key scan operation
does not start until external CPU reads data out after key status is fixed.
3, When the key status is fixed, REQ terminal outputs “L” signal as Key data read out request to the Master.
should read key data out at detection of this “L” signal. The Key data read out request signal is released
and REQ terminal outputs “H” signal after finish of the Master key data read out for newly key scan
operation.
Key scan example
Key data read request
Key data read request
Key data read request
Key input 1
Key unput2
Key scan
1 2 3 4 5 1 2 3 4 5
S S S S S S S S S S
1 2 3 4 5 1 2 3 4 5
S S S S S S S S S S
1 2 3 4 5 1 2 3 4 5
S S S S S S S S S S
320ｘT
320ｘT
320ｘT
REQ
SCL
SDA
Key data take in
Key data read
Key data take in
End of Key data read
Key data read
Key data take in
End of Key data read
Key data read
End of Key data read
Fig15
Ver.2009-04-02
- 19 -
NJU6541A
Preliminary
13) General port output
The terminal SEG specified by command register 2 can be used as a general-purpose port. And, SEG1 ~
SEG4 terminals can be selected as segment driver output or general-purpose ports by instruction. The output
setting of a general-purpose port sets the data of SEG1-SEG4 of COM1.Data is “1”=Output “H”, Data is
“0”=Output “L”.
! ABSOLUTE MAXIMAM RATINGS
(VSS=0V, Ta=25°C)
CONDITIONS
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage 1
VDD
-0.3 ~ +7.0
V
Supply Voltage 2
V0
-0.3 ~ +7.0
V
Supply Voltage 3 V1, V2, V3
-0.3 ~ V0+0.3
V
Input Voltage
VIN
-0.3 ~ VDD+0.3
V
INHb, CSb, SCL, SDA, RSTb, OSC applicable.
Operating Temp.
Topr
-40 ~ +105
°C
Storage Temp.
Tstg
-55 ~ +125
°C
Dissipation
The power dissipation is value mounted on glass
PD
1000
mW
Power
epoxy board in size 76.2mm x 114.3mm x 1.6tmm
Note-1)
Do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to
the IC. It is also recommended that the IC be used within the range specified in the DC electrical
characteristics, or the electrical stress may cause mulfunctions and impact on the reliability.
Note-2)
All voltages are relative to VSS = 0V reference.
Note-3)
The following relationship shall be maintained.
V0 ≥ V1 ≥ V2 ≥ V3 ≥ VSS, V0 ≥VDD, and V0 shall be input after VDD.
Note-4)
To stabilize the LSI operation, place decoupling capacitors between VDD-VSS and between V0-VSS.
- 20 -
Ver.2009-04-02
Preliminary NJU6541A
! ELECTRICAL CHARACTERISTICS
•
DC characteristics 1
(VDD=2.4 to 3.6V, VSS=0V, Ta=-40 to 105°C)
PARAMETER
Power Supply
LCD Driving Voltage
LCD Bias Voltage
SYM
BOL
VDD
V0
V2
V3
"H" Level Input Voltage1
"L" Level Input Voltage1
"H" Level Input Voltage2
"L" Level Input Voltage2
"H" Level Input Voltage3
"L" Level Input Voltage3
Hysteresis Voltage1
Hysteresis Voltage2
VIH1
VIL1
VIH2
VIL2
VIH3
VIL3
VH1
VH2
"H" Level Input Current
IIH
"L" Level Input Current
IIL
"H" Level Output
Voltage1
"L" Level Output Voltage1
"H" Level Output
Voltage2
"L" Level Output Voltage2
VOH1
VOL1
VOH2
V0 ≥VDD
Ta=25°C
Testing via COM/SEG terminals
COM/SEG without load
CSb, RESb, OSC
CSb, RESb, OSC
K1-K6
K1-K6
SCL, SDA
SCL, SDA
CSb, RESb
SCL, SDA
VIN= VDD
CSb, SCL, SDA, RESb
VIN= VSS
CSb, SCL, SDA, RESb
VDD =3V, IO=5mA, P1 to P4
VDD =3V, IO=5mA, P1 to P4
VDD =3V, IOH=-10uA, S1 to S5
RCOM
VDD =3V, IOL2=250uA, S1 to S5
VDD=3V, REQ IO=+3mA
(open drain)
VDD=3V, SDA IO=+3mA
(open drain)
±Id=1µA, VLCD=3V/5.5V
RSEG
±Id=1µA, VLCD=3V/5.5V
VOL2
"L" Level Output Voltage3
VOL3
"L" Level Output Voltage4
VOL4
Driver-on Resistance
(COM)
Driver-on Resistance
(SEG)
Pull up MOS current
IP
Oscillating Frequency
fOSC
External Clock Frequency
External Clock Duty
Bleeder Resistor
E.V.R
fCP
duty
RB
REVR
IDD1
IDD2
Operating Current
CONDITIONS
ILCD1
ILCD2
VDD=3V, VIN=Vss, K1-K6
VDD =3V, ROSC=390kOhm,
Cosc=120pF, Ta=25°C
Input into OSC
Input into OSC
V1-VSS Ta=25°C
V0-V1 Ta=25°C E.V.R.=V0(1,1,1)
VDD =3V, Display OFF,
Key scan OFF, Ta=25°C
VDD =3V, Ta=25°C, Display ON
Checker flag display, 1/3 bias
Using external R & C, output open
VDD=3V, V0=5V, Display OFF
Ta=25°C
VDD =3V, V0=5V, Ta=25°C, Display
ON, Key scan ON
Checker flag display, 1/3 bias
output open, E.V.R.=(1,1,1)
Not
e
MIN
TYP
MAX
UNIT
2.4
2.4
-
3.6
5.5
2/3 V1-0.2
2/3 V1
2/3 V1+0.2
V
V
V
1/3 V1-0.2
1/3 V1
1/3 V1+0.2
0.8 VDD
0
0.8 VDD
0
0.7 VDD
0(-0.5)
0.05VDD
0.2VDD
-
VDD
0.2 VDD
VDD
0.2 VDD
3.6
0.3 VDD
-
V
V
V
V
V
V
V
V
V
-
-
1.0
µA
-
-
1.0
µA
VDD-0.6
-
-
V
-
-
0.6
V
0.8VDD
-
VDD
V
VSS
-
0.2 VDD
V
0
-
0.4
V
0
-
0.4
V
-
-
10
kOhm
5
-
-
10
kOhm
5
-5
-15
-25
µA
12.6
15.4
18.2
kHz
12.6
40
9
3
15.4
50
12
4
18.2
60
15
5
kHz
%
kOhm
-
3
10
µA
-
15
30
µA
-
-
1
µA
-
320
450
µA
6
kOhm
Note-5) Driver-On resistance (RSEG/RCOM) is measured from V0, VSS, V1 , V2 or V3 terminal to each SEG/COM
terminal when Id current flows through COM/SEG terminals.
Note-6) The range of the oscillatory frequency is recommended. Please decide it noting flicker and the display
quality when changing.
Ver.2009-04-02
- 21 -
Preliminary
NJU6541A
DC characteristics 2
(VDD=4.5 to 5.5V, VSS=0V, Ta=-40 to 105°C)
PARAMETER
Power Supply
LCD Driving Voltage
LCD Bias Voltage
SYM
BOL
VDD
V0
V0 ≥VDD
RCOM
Ta=25°C
Testing via COM/SEG terminals
COM/SEG without load
RESb, OSC
RESb, OSC
SCL, SDA ( Open drain)
SCL, SDA (Open drain)
RESb
SCL, SDA
VIN= VDD
CSb, SCL, SDA, RESb
VIN= VSS
CSb, SCL, SDA, RESb
VDD =5V, IO=-10mA, P1 to P4
VDD =5V, IO=+10mA, P1 to P4
VDD =5V, IOH=-20uA, S1 to S5
VDD =5V, IO=+500uA, P1 to P4
VDD =5V , REQ IO=+3mA
(open drain)
VDD =5V , SDA IO=-3mA
(open drain)
±Id=1µA, VLCD=4.5V/5.5V
RSEG
V2
V3
"H" Level Input Voltage1
"L" Level Input Voltage1
"H" Level Input Voltage3
"L" Level Input Voltage3
Hysteresis Voltage1
Hysteresis Voltage2
VIH1
VIL1
VIH3
VIL3
VH1
VH2
"H" Level Input Current
IIH
"L" Level Input Current
IIL
"H" Level Output Voltage1
"L" Level Output Voltage1
"H" Level Output Voltage2
"L" Level Output Voltage2
VOH1
VOL1
VOH2
VOL2
"L" Level Output Voltage3
VOL3
"L" Level Output Voltage4
VOL4
Driver-on Resistance
(COM)
Driver-on Resistance
(SEG)
Pull up MOS Current
CONDITIONS
IP
Oscillating Frequency
fOSC
External Clock Frequency
External Clock Duty
Bleeder Resistor
fCP
duty
RB
E.V.R
REVR
IDD1
IDD2
Operating Current
ILCD1
ILCD2
MIN
TYP
MAX
UNIT
4.5
4.5
-
5.5
5.5
2/3 V1-0.2
2/3 V1
2/3 V1+0.2
V
V
V
1/3 V1-0.2
1/3 V1
1/3 V1+0.2
0.8 VDD
0
0.7 VDD
0(-0.5)
0.05VDD
0.2VDD
-
VDD
0.2 VDD
5.5
0.3 VDD
-
V
V
V
V
V
V
V
-
-
1.0
µA
-
-
1.0
µA
VDD-1.0
0.8VDD
VSS
-
1.0
VDD
0.2 VDD
V
V
V
V
0
0.4
V
0
0.4
V
Not
e
-
-
10
kOhm
7
±Id=1µA, VLCD=4.5V/5.5V
-
-
10
kOhm
7
VDD =5V, VIN=VSS, K1-K6
-10
-25
-65
µA
12.6
15.4
18.2
kHz
12.6
40
9
15.4
50
12
18.2
60
15
kHz
%
kOhm
3
4
5
kOhm
-
5
12.5
µA
-
30
60
µA
-
-
1
µA
-
320
450
µA
VDD =5V, ROSC=390kOhm,
Cosc=120pF, Ta=25°C
Input into OSC
Input into OSC
V1-VSS Ta=25°C
V0-V1 Ta=25°C
E.V.R.=V0(1,1,1)
VDD =5V, Display off
Ta=25°C, Key scan off
VDD =5V, Ta=25°C, Display ON
Checker flag display, 1/3 bias
Using external R & C, Output
open
VDD=5V, V0=5V, Display off
Ta=25°C
VDD =5V, V0=5V, Ta=25°C,
Checker flag display, 1/3 bias
Output open, E.V.R.=(1,1,1)
8
Note-7) Driver-On resistance (RSEG/RCOM) is measured from V0, VSS, V1 , V2 or V3 terminal to each SEG/COM
terminal when Id current flows through COM/SEG terminals.
Note-8) The range of the oscillatory frequency is recommended. Please decide it noting flicker and the display
quality when changing.
- 22 -
Ver.2009-04-02
Preliminary NJU6541A
AC characteristics
VDD=2.4V to 5.5V, Ta=-40 to 105°C
記号
Item
条
件
MIN
TYP
MAX
UNIT
-
-
400
kHz
SCL, SDA
0.6
-
-
us
SCL
SCL
1.3
0.6
-
-
us
us
tSU;STA
SCL, SDA
0.6
-
-
us
Data hold time
tHD;DAT
SCL, SDA
0
-
0.9
us
Data set up time
tSU;DAT
SCL, SDA
100
-
-
ns
Rising time1
tr1
SCL, SDA
-
-
300
ns
Rising time2
tr2
EN, RSTb, OSC
-
-
300
ns
Falling time1
tf1
SCL, SDA
-
-
300
ns
Falling time2
tf2
EN, RSTb, OSC
-
-
300
ns
SCL, SDA
0.6
-
-
us
SDA
1.3
-
-
us
SCL Click frequency
Hold Time (repetition)
[Start] condition
SCL Clock “L” time
SCL Clock “H” time
Repetition[Start] condition
Set up time
fSCL
tHD;STA
tLOW
tHIGH
[Stop] condition
Set up time
[Stop] [Start]
Bus free time
tSU;STO
tBUF
SCL
2
The I C-bus timing of NJU6541A conforms to a F/S mode.
2
I C bus timing
SDA
tf1
tr1
tSU;DAT
tBUF
tHD;STA
tLOW
tf1
tr1
SCL
tHD;STA
S
tHD;DAT
tHIGH
tSU;SAT
Sr
tSU;STO
P
S
S: Start condotion
Sr: Repeat start condition
P: Stop condition
Ver.2009-04-02
- 23 -
Preliminary
NJU6541A
•
Input condition when hardware reset circuit is used
PARAMETER
Reset Input “L” Level Width
Reset Rising Time
Reset Falling Time
SYMBOL
tRSL
trRS
tfRS
tfRS
CONDITIONS
fOSC= 15.4kHz
tRSL
MIN
1.5
TYP
(Ta=25°C)
UNIT
ms
100
ns
100
ns
MAX
trRS
VIH
RSTb
VIL
•
Power supply condition when hardware reset circuit is used
PARAMETER
Power-on Rising Time
Power-off Time
SYMBOL
trDD
tOFF
CONDITIONS
MIN
0.1
1
(Ta=-40 to 105°C(T.B.D))
TYP
MAX
UNIT
5
ms
ms
2.2V
VDD
0.2V
0.2V
trDD
tOFF
Note 10) tOFF is the off time when power-supply turns off suddenly or cycles on/off.
- 24 -
Ver.2009-04-02
Preliminary NJU6541A
! LCD DRIVING WAVEFORM
1/1duty, 1/1bias, (A/B wave form)
A wave form: fosc/192, B wave form: fosc/384
COM1
COM2
COM3
V1
VSS
V1
VSS
V1
VSS
COM4
V1
VSS
"OFF" segment output correspond to
COM1.
V1
"ON" segment output correspond to
COM1.
V1
VSS
,V
VSS
Note) COM2-COM4 must open when 1/1duty is selected.
1/1duty, 1/1bias
Ver.2009-04-02
- 25 -
NJU6541A
Preliminary
1/2 duty, 1/2 bias, A waveform
fosc/192
V1
COM1
V2,V3
VSS
COM2
V1
V2,V3
VSS
COM3
V1
V2,V3
VSS
COM4
V1
V2,V3
VSS
V1
V2,V3
VSS
"OFF" segment output correspond to
COM1 and 2.
"ON" segment output correspond to
COM1.
V1
V2,V3
VSS
"ON" segment output correspond to
COM2.
V1
V2,V3
VSS
"ON" segment output correspond to
COM1 and 2.
V1
V2,V3
VSS
1/2duty, 1/2bias
- 26 -
Ver.2009-04-02
Preliminary NJU6541A
1/2duty, 1/3bias, Awaveform
fosc/192
COM1
V1
V2
V3
VSS
COM2
V1
V2
V3
VSS
V1
V2
V3
VSS
COM3
V1
V2
V3
VSS
COM4
V1
V2
V3
VSS
"OFF" segment output correspond to
COM1 and 2.
V1
V2
V3
VSS
"ON" segment output correspond to
COM1.
"ON" segment output correspond to
COM2
V1
V2
V3
VSS
"ON" segment output correspond to
COM1 and 2
V1
V2
V3
VSS
1/2duty, 1/3bias
Ver.2009-04-02
- 27 -
NJU6541A
Preliminary
1/3duty, 1/2bias, Awaveform
fosc/192
V1
V2,V3
VSS
COM1
COM2
V1
V2,V3
VSS
COM3
V1
V2,V3
VSS
COM4
V1
V2,V3
VSS
V1
V2,V3
VSS
"OFF" segment output correspond to
COM1, 2, and 3.
V1
V2,V3
VSS
"ON" segment output correspond to
COM1.
V1
V2,V3
VSS
"ON" segment output correspond to
COM2.
V1
V2,V3
VSS
"ON" segment output correspond to
COM1 and 2.
V1
V2,V3
VSS
"ON" segment output correspond to
COM3.
V1
V2,V3
VSS
"ON" segment output correspond to
COM1 and 3.
V1
V2,V3
VSS
"ON" segment output correspond to
COM2 and 3.
V1
V2,V3
VSS
"ON" segment output correspond to
COM1, 2 and 3.
1/3duty, 1/2bias
- 28 -
Ver.2009-04-02
Preliminary NJU6541A
1/3duty, 1/3bias, Awaveform
fosc/192
COM1
V1
V2
V3
VSS
COM2
V1
V2
V3
VSS
COM3
V1
V2
V3
VSS
V1
V2
V3
VSS
COM4
V1
V2
V3
VSS
"OFF" segment output correspond to
COM1, 2 and 3.
V1
V2
V3
VSS
"ON" segment output correspond to
COM1.
V1
V2
V3
VSS
"ON" segment output correspond to
COM2.
"ON" segment output correspond to
COM1 and 2.
V1
V2
V3
VSS
"ON" segment output correspond to
COM3.
V1
V2
V3
VSS
V1
V2
V3
VSS
"ON" segment output correspond to
COM1 and 3.
"ON" segment output correspond to
COM2 and 3.
V1
V2
V3
VSS
"ON" segment output correspond to
COM1, 2 and 3.
V1
V2
V3
VSS
1/3duty, 1/3bias
Ver.2009-04-02
- 29 -
NJU6541A
Preliminary
fosc/192
1/4duty, 1/2bias, A waveform
V1
V2,V3
VSS
COM1
V1
V2,V3
VSS
COM2
COM3
V1
V2,V3
VSS
COM4
V1
V2,V3
VSS
V1
V2,V3
VSS
"OFF" segment output correspond to
COM1, 2, 3 and 4.
V1
V2,V3
VSS
"ON" segment output correspond to
COM1.
V1
V2,V3
VSS
"ON" segment output correspond to
COM2.
V1
V2,V3
VSS
"ON" segment output correspond to
COM1 and 2.
V1
V2,V3
VSS
"ON" segment output correspond to
COM3.
V1
V2,V3
VSS
"ON" segment output correspond to
COM1 and 3.
V1
V2,V3
VSS
"ON" segment output correspond to
COM2 and 3.
V1
V2,V3
VSS
"ON" segment output correspond to
COM1, 2 and 3
V1
V2,V3
VSS
"ON" segment output correspond to
COM4.
V1
V2,V3
VSS
"ON" segment output correspond to
COM2 and 4
V1
V2,V3
VSS
"ON" segment output correspond to
COM1, 2, 3 and 4.
1/4duty, 1/2bias
- 30 -
Ver.2009-04-02
Preliminary NJU6541A
1/4duty, 1/3bias, A waveform
fosc/192
COM1
V1
V2
V3
VSS
COM2
V1
V2
V3
VSS
COM3
V1
V2
V3
VSS
COM4
V1
V2
V3
VSS
"OFF" segment output correspond to
COM1, 2, 3 and 4
V1
V2
V3
VSS
"ON" segment output correspond to
COM1.
V1
V2
V3
VSS
"ON" segment output correspond to
COM2.
V1
V2
V3
VSS
"ON" segment output correspond to
COM1 and 2.
V1
V2
V3
VSS
"ON" segment output correspond to
COM3.
V1
V2
V3
VSS
"ON" segment output correspond to
COM1 and 3.
V1
V2
V3
VSS
"ON" segment output correspond to
COM2 and 3.
V1
V2
V3
VSS
"ON" segment output correspond to
COM1, 2 and 3.
V1
V2
V3
VSS
"ON" segment output correspond to
COM4.
V1
V2
V3
VSS
"ON" segment output correspond to
COM2 and 4.
V1
V2
V3
VSS
"ON" segment output correspond to
COM1, 2, 3 and 4.
V1
V2
V3
VSS
1/4duty, 1/3bias
Ver.2009-04-02
- 31 -
NJU6541A
Preliminary
1/2duty, 1/2bias, B waveform
Tfosc/192
COM1
V1
V2,V3
VSS
COM2
V1
V2,V3
VSS
COM3
V1
V2,V3
VSS
COM4
V1
V2,V3
VSS
"OFF" segment output correspond to
COM1 and 2
V1
V2,V3
VSS
V1
V2,V3
VSS
"ON" segment output correspond to
COM1.
V1
V2,V3
VSS
"ON" segment output correspond to
COM2.
V1
V2,V3
VSS
"ON" segment output correspond to
COM1 and 2.
1/2duty, 1/2bias
- 32 -
Ver.2009-04-02
Preliminary NJU6541A
1/2duty, 1/3bias,B waveform
fosc/192
COM1
V1
V2
V3
VSS
COM2
V1
V2
V3
VSS
COM3
V1
V2
V3
VSS
COM4
V1
V2
V3
VSS
"OFF" segment output correspond to
COM1 and 2.
V1
V2
V3
VSS
"ON" segment output correspond to
COM1.
V1
V2
V3
VSS
"ON" segment output correspond to
COM2.
V1
V2
V3
VSS
"ON" segment output correspond to
COM1 and 2
V1
V2
V3
VSS
1/2duty, 1/3bias
Ver.2009-04-02
- 33 -
NJU6541A
Preliminary
1/3duty, 1/2bias, B waveform
fosc/192
COM1
V1
V2,V3
VSS
COM2
V1
V2,V3
VSS
COM3
V1
V2,V3
VSS
COM4
V1
V2,V3
VSS
"OFF" segment output correspond to
COM1, 2, and 3.
V1
V2,V3
VSS
"ON" segment output correspond to
COM1.
V1
V2,V3
VSS
"ON" segment output correspond to
COM2.
V1
V2,V3
VSS
V1
V2,V3
VSS
"ON" segment output correspond to
COM1 and 2.
V1
V2,V3
VSS
"ON" segment output correspond to
COM3.
V1
V2,V3
VSS
"ON" segment output correspond to
COM1 and 3.
V1
V2,V3
VSS
"ON" segment output correspond to
COM2 and 3.
V1
V2,V3
VSS
"ON" segment output correspond to
COM1, 2 and 3.
1/3duty, 1/2bias
- 34 -
Ver.2009-04-02
Preliminary NJU6541A
fosc/192
1/3duty, 1/3bias, B waveform
V1
V2
V3
VSS
COM1
COM2
V1
V2
V3
VSS
COM3
V1
V2
V3
VSS
COM4
V1
V2
V3
VSS
"OFF" segment output correspond to
COM1, 2 and 3.
V1
V2
V3
VSS
V1
V2
V3
VSS
"ON" segment output correspond to
COM1.
V1
V2
V3
VSS
"ON" segment output correspond to
COM2.
"ON" segment output correspond to
COM1 and 2.
V1
V2
V3
VSS
"ON" segment output correspond to
COM3.
V1
V2
V3
VSS
"ON" segment output correspond to
COM1 and 3.
V1
V2
V3
VSS
"ON" segment output correspond to
COM2 and 3.
V1
V2
V3
VSS
"ON" segment output correspond to
COM1, 2 and 3.
V1
V2
V3
VSS
1/3duty, 1/3bias
Ver.2009-04-02
- 35 -
NJU6541A
Preliminary
1/4duty, 1/2bias, B waveform
fosc/192
COM1
V1
V2,V3
VSS
COM2
V1
V2,V3
VSS
COM3
V1
V2,V3
VSS
COM4
V1
V2,V3
VSS
V1
V2,V3
VSS
"OFF" segment output correspond to COM1,
2, 3 and 4.
V1
V2,V3
VSS
"ON" segment output correspond to
COM1.
V1
V2,V3
VSS
"ON" segment output correspond to
COM2.
V1
V2,V3
VSS
"ON" segment output correspond to
COM1 and 2.
V1
V2,V3
VSS
"ON" segment output correspond to
COM3.
V1
V2,V3
VSS
"ON" segment output correspond to
COM1 and 3.
V1
V2,V3
VSS
"ON" segment output correspond to
COM2 and 3.
V1
V2,V3
VSS
"ON" segment output correspond to
COM1, 2 and 3.
V1
V2,V3
VSS
"ON" segment output correspond to
COM4.
V1
V2,V3
VSS
"ON" segment output correspond to
COM2 and 4.
V1
V2,V3
VSS
"ON" segment output correspond to COM1,
2, 3 and 4.
1/4duty, 1/2bias
- 36 -
Ver.2009-04-02
Preliminary NJU6541A
1/4duty, 1/3bias, B waveform
fosc/192
V1
V2
V3
VSS
COM1
V1
V2
V3
VSS
COM2
COM3
V1
V2
V3
VSS
COM4
V1
V2
V3
VSS
"OFF" segment output correspond to COM1,
2, 3 and 4.
V1
V2
V3
VSS
"ON" segment output correspond to
COM1.
V1
V2
V3
VSS
"ON" segment output correspond to
COM2.
V1
V2
V3
VSS
V1
V2
V3
VSS
"ON" segment output correspond to
COM1 and 2.
"ON" segment output correspond to
COM3.
V1
V2
V3
VSS
"ON" segment output correspond to
COM1 and 3.
V1
V2
V3
VSS
"ON" segment output correspond to
COM2 and 3.
V1
V2
V3
VSS
"ON" segment output correspond to
COM1, 2 and 3.
V1
V2
V3
VSS
"ON" segment output correspond to
COM4.
V1
V2
V3
VSS
"ON" segment output correspond to
COM2 and 4.
V1
V2
V3
VSS
"ON" segment output correspond to COM1,
2, 3 and 4.
V1
V2
V3
VSS
1/4duty, 1/3bias
Ver.2009-04-02
- 37 -
Preliminary
NJU6541A
INPUT and OUTPUT Curcuit
VDD
IN
IN
VSS
VSS
RSTb, TEST, CSb,
VSS
SDA、SCL、REQ
VDD
VDD
IN
IN
VSS
VSS
OSC
- 38 -
VDD
K1~K6
Ver.2009-04-02
Preliminary NJU6541A
V0
VDD
VSS
OUT
OUT
V0
VSS
VSS
S5
SEG5~SEG116, COM1~COM4
V0
V0
VSS
VSS
OUT
OUT
V0
V0
VSS
VSS
VDD
VDD
VSS
SEG1/P1~SEG4/P4
Ver.2009-04-02
VSS
SEG117/S1~SEG120/S4
- 39 -
NJU6541A
Preliminary
! APPLICATION CIRCUIT
• 1/4duty,
1/3bias SEG1~SEG120
VDD
V0
VDD
COM1
V0
COM4
V1
LCD Panel
SEG1/P1
NJU6541A
V2
SEG4/P4
SEG5
V3
VSS
VSS
VDD
SEG116
SEG117/S1
SEG120/S4
RSTb
SDA
SCL
S5
K1
OSC
K6
Key switch
• 1/3duty,
1/2bias 30Key
VDD
VDD
COM1
V0
COM3
V1
SEG1/P1
LCD Panel
V0
V2
NJU6541A
SEG4/P4
SEG5
V3
VSS
VSS
VDD
SEG116
SEG117/S1
SEG120/S4
RSTb
SDA
SCL
S5
K1
OSC
K6
Key switch
- 40 -
Ver.2009-04-02
Preliminary NJU6541A
1/1duty, 1/1bias, 30Key, P1~P4port
VDD
VDD
COM1
LCD Panel
V0
V0
V1
SEG1/P1
NJU6541A
V2
(a)
SEG4/P4
SEG5
V3
VSS
VSS
VDD
SEG116
SEG117/S1
SEG120/S4
RSTb
SDA
SCL
S5
K1
OSC
K6
Key switch
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.2009-04-02
- 41 -