DATA SHEET MOS INTEGRATED CIRCUIT µPD16431A 1/2, 1/3, 1/4-DUTY LCD CONTROLLER/DRIVER The µPD16431A is an LCD controller/driver that enables display of segment type LCDs of 1/2, 1/3, or 1/4 duty cycle. This controller/driver has 56 segment output lines of which eight can also be used as LED output lines. Because the LCD driver contained in the µPD16431A has separate logic and power supply, up to 6.5 V of LCD drive voltage can be set. In addition, key source output lines for key scanning and key input data lines are also provided, so that the µPD16431A is ideal for applications in the front panel of an automobile stereo system. FEATURES • Various display modes 1/2 duty: 112 segment outputs or 96 segment outputs + 8 LED outputs 1/3 duty: 168 segment outputs or 144 segment outputs + 8 LED outputs 1/4 duty: 224 segment outputs or 192 segment outputs + 8 LED outputs • Key scan circuit (key source outputs are shared with LCD driver outputs) • Independent LCD driver power supply VLCD (can be set to VDD to 6.5 V) • Serial data input/output (SCK, STB, DATA) • On-chip oscillator incorporated • Power-ON reset circuit ORDERING INFORMATION Part Number Package µPD16431AGC-7ET 80-pin plastic QFP (0.65 pitch, 14 × 14) Document No. IC-3414 (O.D. No. IC-8885) Date Published January 1995 P Printed in Japan © 1995 µPD16431A 48 COM4 8 8 Segment driver COM1 S56/LED8 S48 S49/LED1 S8/KS8 S1/KS1 S1/KS2 BLOCK DIAGRAM OE LED driver Common driver 56 4 56 4 Output latch (56 × 4) 56 CLK I/O control Timing generator 2 Read address STB DATA SYNC Selector circuit 56 Write address LCD/LED Level shifter Level shifter (56) Key counter OE OSCIN OSC 56-bit shift register OSCOUT 8-bit shift register 8 Command decoder key1 Key counter Key latch S/R key4 KEY REQ VDD VSS VLCD VLC1 VLC2 VLC3 2 µPD16431A SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 PIN CONFIGURATION 60 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49/LED1 SEG50/LED2 SEG51/LED3 SEG52/LED4 SEG53/LED5 SEG54/LED6 SEG55/LED7 SEG56/LED8 61 80 21 20 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8/KS8 SEG7/KS7 SEG6/KS6 SEG5/KS5 SEG4/KS4 SEG3/KS3 SEG2/KS2 SEG1/KS1 COM4 COM3 COM2 COM1 VSS KEY1 KEY2 KEY3 KEY4 KEY REQ SCK DATA STB LCD/LED OE OSCIN OSCOUT SYNC VDD VLCD VLC1 VLC2 VLC3 VEE 1 41 40 Note Though VSS and VEE are internally connected, be sure to connect all the power supply pins (VDD, VSS, VLCD, and VEE). 3 µPD16431A PIN FUNCTIONS Symbol Name No. Description SEG1/KS1 to SEG8/KS8 Segment output/key source output 25 to 32 These pins serve as LCD segment output pins and key source output pins for key scanning. SEG9 to SEG48 Segment output 33 to 72 LCD segment output pins SEG49/LED1 to SEG56/LED8 Segment output/LED output pins 73 to 80 These pins can be used as LCD segment output or LED output pins depending on the setting of the LCD/LED pin. COM1 to COM4 Common output 21 to 24 LCD common output pins SCK Shift clock input 7 Data shift clock. Data is read at the rising edge, and is output at the falling edge of this clock. DATA Data input/output 8 This pin inputs a command or display data, or outputs key data. A command or data is input at the rising edge of the shift clock, starting from the most significant bit. Key data is output at the falling edge of the shift clock, starting from the most significant bit. This pin serves as an open-drain pin in the output mode. STB Strobe input 9 Data can be input when this signal goes low. When it goes high, command processing is performed. LCD/LED LCD/LED select 10 When this signal goes high, the SEGn/LEDm pins function as LCD segment output pins; when it goes low, they function as LED driver output pins. The LED driver has a drive capability of 15 mA and is N-ch open drain. Output enable input 11 When this signal goes low, all the segment output and LED output pins are off (SEGn = COMn = VLCD). Internal OE Note data are saved. OSCIN Oscillation input 12 OSCOUT Oscillation output 13 SYNC Synchronizing signal 14 Connect a resistor for oscillation circuit across these pins. A synchronizing signal input pin. When two or more µPD16431A’s are used, each device is wired-ORed. This pin must be pulled up when this chip is used alone. 2 to 5 KEY1 to KEY4 Key data input KEY REQ Key request output 6 VDD Logic power supply 15 VSS Logic GND VLCD LCD drive power supply 16 Power supply pin for LCD drive VEE LCD GND 20 GND pin for LCD drive VLC1 to VLC3 Power supply for LCD drive 1 17 to 19 Key data input pins for key scanning This signal goes high when a key is pressed (key data = H). Read the key data only while this pin is high. Power supply pin for internal logic GND pin for internal logic and LED output Power supply for driving dot matrix LCD Note At OE = L, the key data cannot be written correctly, even when the display ON/OFF of the status command is set to the “normal operation” (10). Also, in this state, unnecessary waveforms are generated from between SEG1/KS1 to SEG8/KS8 during the key scanning period. (The display is OFF.) 4 µPD16431A CONFIGURATION OF SHIFT REGISTER Two shift registers, an 8-bit command register and a 56-bit display register, are provided. The first 8 bits of input data are recognized as a command and are sent to the command register, and the 9th bit and those that follow are recognized as display data and are sent to the display register. 8-bit shift register MSB LSB b7 b0 Command 56-bit shift register MSB LSB SEG1 SEG56/LED8 Transfer direction Display data (LCD, LED) The meaning of the display data is as follows: LCD: 0 → off, 1 → on LED: 0 → on, 1 → off Be sure to transfer 56 bits of display data. CONFIGURATION OF OUTPUT LATCH MSB LSB SEG56/LED8 SEG1 COM1 (latch addressNote: 00) SEG56/LED8 SEG1 COM2 (latch addressNote: 01) SEG56/LED8 SEG1 COM3 (latch addressNote: 10) SEG56/LED8 SEG1 COM4 (latch addressNote: 11) Note Bits b3 and b4 of status command (Refer to page 8.) 5 µPD16431A KEY MATRIX CONFIGURATION An example of key matrix configurations is shown below. 1) When pressing three or more times is assumed: A configuration example is shown below. In this configuration, 0 to 32 ON switches can be recognized. C KEY1 = KEY2 KEY3 KEY4 KS1 KS2 KS3 KS4 KS5 KS6 KS7 KS8 2) When pressing twice or more times is assumed: A configuration example is shown below. In this configuration, 0 to 2 ON switches can be recognized. KEY1 = KEY2 KEY3 KEY4 Diode A KS1 KS2 KS3 KS4 KS5 KS6 KS7 KS8 In this configuration, pressing three or more times may cause OFF switches to be determined to be ON. For example, if SW2 to SW4 are ON and KS1 has been selected (high level) as shown below, SW3 in which current I1 is running is supposed to be detected to be ON. However, since SW2 and SW4 are ON, current I2 runs thus resulting in SW1 to be recognized as being ON. SW1 SW2 SW3 SW4 KEY1 I2 KEY2 = I1 KEY3 KEY4 KS1 Select 6 KS2 KS3 KS4 KS5 KS6 KS7 KS8 µPD16431A If diode A is not available, not only the key data may not be read normally but the LCD display may be affected or ICs may be damaged or deteriorated. For example, if SW1 and SW2 are ON and KS1 has been selected (high level) as shown below, this will cause not only current I1 which is supposed to run but also short-circuited current I2 of KS1 to KS2 to run. It is possible that this will then cause the following three problems: (1)Since the level to KEY2 is not correctly sent, the key data cannot be latched correctly. (2)If KS2 is used as SEG2 as well, the LCD display may be distorted (such as causing unintended segments to light up). (3)Since the short-circuited current (current I2) of KS2 (high level) to KS2 (low level) runs, ICS may be damaged or deteriorated KEY1 SW1 = SW2 KEY2 I1 KEY3 KEY4 I2 KS1 KS2 Select (high level) KS3 KS4 KS5 KS6 KS7 KS8 Non Select (low level) 7 µPD16431A CONFIGURATION OF KEY DATA LATCH The key data is latched as illustrated below and is read by a read command, starting from the most significant bit. Key data is read once a frame and latched when coinciding with the immediadtely preceding data. In other words, it requires at least 2 frames from the time the key is pressed till data is confirmed to be the key data (the key request becoming H). 32-bit latch/SHIFT register MSB LSB KS8 KS7 KS6 KS5 KS4 KS3 KS1 KS2 KEY4 KEY3 KEY2 KEY1 The key data is 0 when off and 1 when on. KEY INPUT EQUIVALENT CIRCUIT To key latch KEY n Pull-down control signal • The pull-down control signal goes high only during key source output and turns on the pull-down transistor. • The on-resistance of the pull-down transistor is several kΩ. 8 µPD16431A COMMAND A command sets a display mode and a status. The first 1 byte input after the STB pin has fallen is regarded as a command. If the STB pin is made low while a command/data is transferred, serial communication is initialized, and the command/data being transferred is made invalid (the command/data that has been already transferred remains valid, however). (1) Display setting command This command initializes the µPD16431A and sets a duty cycle, frame frequency, drive voltage supply method, test mode, and whether the µPD16431A operates as the master or a slave. When this command is executed, display is forcibly turned off and key scanning is stopped. To resume the display, the normal operation of the “status command” must be executed. Note, however, that nothing is executed if the same mode is selected. MSB 0 LSB b6 b5 b4 b3 b2 b1 b0 Sets duty. 00: 1/4 duty, 1/3 bias 01: 1/3 duty, 1/3 bias 10: 1/2 duty, 1/2 bias 11: 1/2 duty, 1/2 bias Sets frame frequency. 00: (fOSC/128) × n 01: (fOSC/256) × n 10: (fOSC/512) × n 11: (fOSC/1024) × n n= duty (1/2, 1/3, 1/4) Sets drive voltage supply method. 0: Internal 1: External Sets master or slave. 0: Master 1: Slave Sets test mode. 0: Normal operation 1: Test mode Values when power is applied 0 0 0 0 0 0 0 9 µPD16431A (2) Status command This command sets a data write/read mode, turns on/off display, and sets a latch address. MSB 1 LSB × × b4 b3 b2 b1 b0 × : Don’t Care Sets data write/read mode. 0: Writes display data to output latch 1: Reads key data Turns on/off display 00: Forcibly turns off display (all segments and LEDs off). Stops key scanning. 01: Prohibited 10: Normal operation 11: Don’t care Sets latch address. 00: COM1 01: COM2 10: COM3 11: COM4 Values when power is applied × 10 × 0 0 0 0 0 µPD16431A OUTPUT SELECT VOLTAGE 1. COM + – VLCD VLCD GND GND When not selected 1/2 VLCD VLC2 1/2 VLCD VLC2 When key scanned 1/2 VLCD VLC2 1/2 VLCD VLC2 When selected VLCD VLCD GND GND When not selected 1/3 VLCD VLC3 2/3 VLCD VLC1 When key scanned 1/2 VLCD VLC2 1/2 VLCD VLC2 When selected Bias 1/2 bias Top : with internal power supply Bottom: with external power supply 1/3 bias 2. SEG + – When selected GND GND VLCD VLCD When not selected VLCD VLCD GND GND When key scanned GND GND VLCD VLCD When key not scanned VLCD VLCD GND GND When selected GND VLCD GND VLCD When not selected 2/3 VLCD VLC1 1/3 VLCD VLC3 When key scanned GND GND VLCD VLCD When key not scanned VLCD VLCD GND GND Bias 1/2 bias 1/3 bias 11 µPD16431A OUTPUT WAVEFORM (1) 1/2 duty (1/2 dias) * K 0 VLCD COM1 VLC2 VEE VLCD COM2 VLC2 VEE VLCD SEG1 VLC2 VEE VLCD SEG9 VLC2 VEE VLCD 1/2VLCD SEG1-COM1 0 -1/2VLCD -VLCD VLCD 1/2VLCD SEG1-COM2 0 -1/2VLCD -VLCD 1 KEY REQ (w/key) 2 KEY REQ (w/key→w/o key) 3 KEY REQ (w/o key→w/key) 12 0 * K 1 1 * K 0 0 * K 1 1 * K 0 *: key scan period (16/fc) µPD16431A KEY SCAN PERIOD (K0) EXPANSION 1 K0 1 2 3 4 0 5 6 7 8 VLCD COM1 VLC2 VEE VLCD SEG1 VLC2 VEE VLCD SEG2 VLC2 VEE VLCD SEG3 VLC2 VEE VLCD SEG4 VLC2 VEE VLCD SEG5-SEG40 VLC2 VEE = Key source output 13 µPD16431A KEY SCAN PERIOD (K1) EXPANSION 0 K1 1 2 VLCD COM1 VLC2 VEE VLCD SEG1-SEG4, SEG9-SEG40 VLC2 VEE VLCD SEG5 VLC2 VEE VLCD SEG6 VLC2 VEE VLCD SEG7 VLC2 VEE VLCD SEG8 VLC2 VEE 1 KEY REQ (w/key) 2 KEY REQ (w/key→w/o key) 3 KEY REQ (w/o key→w/key) = Key source output 14 3 4 1 5 6 7 8 µPD16431A (2) 1/3 duty (1/3 bias) * K 0 COM1 VLCD VLC1 VLC2 VLC3 VEE COM2 VLCD VLC1 VLC2 VLC3 VEE COM3 VLCD VLC1 VLC2 VLC3 VEE SEG1 VLCD VLC1 VLC2 VLC3 VEE SEG9 VLCD VLC1 VLC2 VLC3 VEE 0 * K 1 1 * K 2 2 * K 0 0 * K 1 *: key scan period (16/fc) VLCD SEG1-COM1 1/2VLCD 1/3VLCD 0 -1/3VLCD -1/2VLCD -VLCD VLCD SEG1-COM2 1/2VLCD 1/3VLCD 0 -1/3VLCD -1/2VLCD -VLCD 15 µPD16431A KEY SCAN PERIOD (K0) EXPANSION 2 K0 1 COM1 VLCD VLC1 VLC2 VLC3 VEE SEG1 VLCD VLC1 VLC2 VLC3 VEE SEG2 VLCD VLC1 VLC2 VLC3 VEE SEG3 VLCD VLC1 VLC2 VLC3 VEE SEG4 VLCD VLC1 VLC2 VLC3 VEE SEG5-SEG8 VLCD VLC1 VLC2 VLC3 VEE 2 = Key source output 16 3 4 0 5 6 7 8 µPD16431A KEY SCAN PERIOD (K1) EXPANSION 0 K1 1 COM1 SEG1-SEG4, SEG9-SEG40 2 3 4 1 5 6 7 8 VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE SEG5 VLCD VLC1 VLC2 VLC3 VEE SEG6 VLCD VLC1 VLC2 VLC3 VEE SEG7 VLCD VLC1 VLC2 VLC3 VEE SEG8 VLCD VLC1 VLC2 VLC3 VEE = Key source output 17 µPD16431A KEY SCAN PERIOD (K2) EXPANSION 1 K2 1 18 COM1 VLCD VLC1 VLC2 VLC3 VEE SEG1-SEG40 VLCD VLC1 VLC2 VLC3 VEE 2 3 4 2 5 6 7 8 µPD16431A (3) 1/4 duty (1/3 bias) * K 0 COM1 VLCD VLC1 VLC2 VLC3 VEE COM2 VLCD VLC1 VLC2 VLC3 VEE COM3 VLCD VLC1 VLC2 VLC3 VEE COM4 VLCD VLC1 VLC2 VLC3 VEE SEG1 VLCD VLC1 VLC2 VLC3 VEE SEG9 VLCD VLC1 VLC2 VLC3 VEE SEG1-COM1 VLCD 2/3VLCD 1/2VLCD 1/3VLCD 0 -1/3VLCD -1/2VLCD -2/3VLCD -VLCD SEG1-COM2 VLCD 2/3VLCD 1/2VLCD 1/3VLCD 0 -1/3VLCD -1/2VLCD -2/3VLCD -VLCD 0 * K 1 1 * K 2 2 * K 3 3 * K 0 0 * K 1 *: key scan period (16/fc) 19 µPD16431A KEY SCAN PERIOD (K0) EXPANSION 3 K0 1 COM1 VLCD VLC1 VLC2 VLC3 VEE SEG1 VLCD VLC1 VLC2 VLC3 VEE SEG2 VLCD VLC1 VLC2 VLC3 VEE SEG3 VLCD VLC1 VLC2 VLC3 VEE SEG4 VLCD VLC1 VLC2 VLC3 VEE SEG5-SEG40 VLCD VLC1 VLC2 VLC3 VEE 2 = Key source output 20 3 4 0 5 6 7 8 µPD16431A KEY SCAN PERIOD (K1) EXPANSION 0 K1 1 COM1 SEG1-SEG4, SEG9-SEG40 2 3 4 1 5 6 7 8 VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE SEG5 VLCD VLC1 VLC2 VLC3 VEE SEG6 VLCD VLC1 VLC2 VLC3 VEE SEG7 VLCD VLC1 VLC2 VLC3 VEE SEG8 VLCD VLC1 VLC2 VLC3 VEE = Key source output 21 µPD16431A KEY SCAN PERIOD (K2) EXPANSION 1 K2 1 COM1 VLCD VLC1 VLC2 VLC3 VEE SEG1-SEG40 VLCD VLC1 VLC2 VLC3 VEE 2 3 4 2 5 6 7 8 KEY SCAN PERIOD (K3) EXPANSION 2 K3 1 22 COM1 VLCD VLC1 VLC2 VLC3 VEE SEG1-SEG40 VLCD VLC1 VLC2 VLC3 VEE 2 3 4 3 5 6 7 8 µPD16431A SERIAL COMMUNICATION FORMAT (1) Receive (command/data write) If data continues STB b7 DATA SCK b6 1 2 b5 b2 3 b1 6 b0 7 8 (2) Transmit (command/data read) STB DATA SCK 7 1 6 2 5 3 2 6 1 7 0 8 1 7 6 5 4 3 2 3 4 5 6 1 µs Data read command set Wait time tWAIT Data read Note Because the DATA pin is an N-ch open-drain output pin, be sure to connect an external pull-up resistor to this pin (1 kΩ to 10 kΩ). 23 µPD16431A APPLICATION 1. Example of initial setting + display data write Command/data Parameter STB Remarks b7 b6 b5 b4 b3 b2 b1 b0 Start H Set display command L 0 0 0 0 0 0 0 0 1/4 duty, frame frequency = fosc/128 × 1/4, internal drive voltage, master H Status command L 1 0 0 0 0 0 0 0 Display data write, display off, latch address: COM1 Display data 1 L × × × × × × × × × × × × × × × × Display data 7 L COM1 data (7 bytes) H Status command L 1 0 0 0 1 0 0 0 Display data write, display off, latch address: COM2 Display data 1 L × × × × × × × × × × × × × × × × Display data 7 L COM2 data (7 bytes) H Status command L 1 0 0 1 0 0 0 0 Display data write, display off, latch address: COM3 Display data 1 L × × × × × × × × × × × × × × × × Display data 7 L COM3 data (7 bytes) H Status command L 1 0 0 1 1 0 0 0 Display data write, display off, latch address: COM4 Display data 1 L × × × × × × × × × × × × × × × × 1 0 0 0 0 1 0 0 Display data write, display on Display data 7 L COM4 data (7 bytes) H 24 Status command L End H µPD16431A 2. Example of display data write (rewrite, 1/4) Command/data Parameter STB Remarks b7 b6 b5 b4 b3 b2 b1 b0 Start H Status command L 1 0 0 0 0 1 0 0 Display data write, display on, latch address: COM1 Display data 1 L × × × × × × × × Display data 7 L × × × × × × × × COM1 data (7 bytes) H Status command L 1 0 0 0 1 1 0 0 Display data write, display on, latch address: COM2 Display data 1 L × × × × × × × × Display data 7 L × × × × × × × × COM2 data (7 bytes) H Status command L 1 0 0 1 0 1 0 0 Display data write, display on, latch address: COM3 Display data 1 L × × × × × × × × Display data 7 L × × × × × × × × COM3 data (7 bytes) H Status command L 1 0 0 1 1 1 0 0 Display data write, display on, latch address: COM4 Display data 1 L × × × × × × × × Display data 7 L × × × × × × × × COM4 data (7 bytes) End H 25 µPD16431A 3. Example of key data read Command/data Parameter STB Remarks b7 b6 b5 b4 b3 b2 b1 b0 KEY REQ check KEY REQ = H: Key data exists. → Start reading. KEY REQ = L: Key data does not exist (reading is inhibited). → Check KEY REQ again. 26 Start H Status command L Wait time L Key data 1 L × × × × × × × × Key data 4 L × × × × × × × × End H 1 0 0 0 0 1 0 1 Data read, display on 1 µs 4 bytes µPD16431A ABSOLUTE MAXIMUM RATINGS (Ta = 25 ˚C, VSS = 0 V) Parameter Symbol Ratings Unit Logic supply voltage VDD –0.3 to +7.0 V Logic input voltage VIN –0.3 to VDD + 0.3 V Logic output voltage (DATA) VOUT –0.3 to +7.0 V LCD drive supply voltage VLCD –0.3 to +7.0 V LCD drive supply input voltage VLC1 to VLC3 –0.3 to VLCD + 0.3 V Driver output voltage (segment, common, LED) VOUT2 –0.3 to VLCD + 0.3 V IO +20 mA Operating ambient temperature Topt –40 to +85 ˚C Storage temperature Tstg –55 to +150 ˚C Permissible package power dissipation PT 1 000 mW LED output current RECOMMENDED OPERATING CONDITIONS Parameter Symbol MIN. TYP. MAX. Unit Logic supply voltage VDD 2.7 5.0 5.5 V LCD drive supply voltage VLCD VDD 5.0 6.5 V Logic input voltage VIN 0 VDD V VLC1 to VLC3 0 VLCD V Driver output voltage 27 µPD16431A ELECTRICAL SPECIFICATIONS (Unless otherwise specified, Ta = –40 to +85 ˚C, VDD = VLCD = 5 V ±10%) Parameter Symbol MIN. Input voltage, high VIH Input voltage, low VIL Input current, high IIH Input current, low IIL MAX. Unit 0.7 VDD VDD V 0 0.3 VDD V CLK, STB, LCD/LED, OE 1 µA CLK, STB, LCD/LED, OE –1 µA 1.0 V Output voltage, low VOL1 LED1 to LED8. IOL1 = 15 mA Output voltage, high VOH2 OSCOUT, IOH2 = –1 mA Output voltage, low VOL2 DATA, OSCOUT, SYNC, IOL2 = 4 mA Leakage current, high ILOH2 Leakage current, low TYP. 0.9 VDD V 0.1 VDD V DATA, SYNC, VIN OUT = VDD 1 mA ILOL2 DATA, SYNC, VIN OUT = VSS –1 mA Common output ON resistance RCOM COM1 to COM4, | IO | = 100 µA 2.4 kΩ Segment output ON resistance RSEG SEG1 to SEG56, | IO | = 100 µA 4.0 kΩ Logic current dissipation IDD fOSC = 250 kHz 250 µA LCD drive current consumption ILCD With internal bias and no load 500 µA Remark The TYP. value is a reference value at Ta = 25 ˚C. 28 µPD16431A SWITCHING CHARACTERISTICS (Unless otherwise specified, Ta = –40 to +85 ˚C, VDD = VLCD = 5 V ±10%, RL = 5 kΩ, CL = 150 pF) MIN. TYP. MAX. Unit Oscillation frequency Parameter fOSC R = 100 kΩ 175 250 325 kHz Oscillation frequency fOSC R = 200 kΩ 105 150 195 kHz Propagation delay time tPZL SCK ↓ → DATA ↓ 100 ns Propagation delay time tPLZ SCK ↓ → DATA ↑ 300 ns 1.5 µs SYNC delay time Symbol Conditions tDSYNC TIMING REQUIREMENTS (Unless otherwise specified, Ta = –40 to +85 ˚C, VDD = VLCD = 5 V ±10%, RL = 5 kΩ, CL = 150 pF) Parameter Clock frequency Symbol Conditions MIN. TYP. MAX. Unit fC OSCIN external clock 50 325 kHz High-level clock pulse width tWHC OSCIN external clock 1.5 16 µs Low-level clock pulse width tWLC OSCIN external clock 1.5 16 µs Shift clock cycle tCYK SCK 900 ns High-level shift clock pulse width tWHK SCK 400 ns Low-level shift clock pulse tWLK SCK 400 ns tHSTBK STB ↓ → SCK ↓ 1.5 µs Data setup time tDS DATA → SCK ↑ 100 ns Data hold time tDH SCK ↑ → DATA 200 ns STB hold time tDKSTB SCK ↑ → STB ↑ 1 µs STB pulse width tWSTB 1 µs Wait time tWAIT 1 µs SYNC removal time tSREM 250 ns width Shift clock hold time CLK ↑ → CLK ↓ Output Load VDD 5 kΩ OUTPUT 150 pF 29 µPD16431A Switching Characteristic Waveform 1/fc tWHC VIH CSCIN VIL tWLC tWSTB VIH STB VIL tHKSTB tCYK tWLK tWHK tDS tDH VIH SCK VIL VIH VIL DATA SYNC timing (master) 1 frame 1 frame SYNC timing (slave) 1 frame 1 frame fOSC tDSYNC SYNC Internal reset 30 tSREM µPD16431A Switching Characteristic Waveform SCK VIL tPZL tPLZ DATA VOL2 Application Circuit Example (with LED, 1/4 duty, 1/3 bias) LCD 4 VDD 8 To microcomputer VDD 40 COMn R5 DATA SCK SEG1/KS1 to SEG8/KS8 STB KEY REQ 8 SEG9 to SEG48 OE LCD/LED µ PD16431A R6 Key matrix 8×4 VLCD R8 LED SYNC. LEDn OSCIN 8 KEYn R7 4 OSCOUT VDD VSS VLCD VLC1 R1 +5 V GND +6 V VLC2 R2 VLC3 R2 VEE R1 GND R1 R2 R5, R6 R7 R8 : 1 k to 10 kΩ : 1/2 R1 : 1 k to 10 kΩ : 100 kΩ TYP. : 330 to 1 kΩ R1 through R2 are not necessary when the internal drive voltage is selected (VLC1 through VLC3 are open). 31 µPD16431A Note Example of external source circuit (when 1/2 bias) VDD VSS VLC0 VLC1 R1 +5 V GND +6 V VLC2 VLC3 VEE R1 = 1 k to 10 kΩ (approx.) R1 GND The application circuits and their parameters are for references only and are not intended for use in actual design-in's. 32 µPD16431A 80 PIN PLASTIC LQFP ( 14) A B 60 61 41 40 F Q R S D C detail of lead end 80 1 G 21 20 H I M J M P K N NOTE L Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 16.0±0.2 0.630±0.008 B 14.0±0.1 0.551 +0.005 –0.004 C 14.0±0.1 0.551 +0.005 –0.004 D 16.0±0.2 0.630±0.008 F 0.825 0.032 G 0.825 0.032 H 0.30±0.10 0.012 +0.004 –0.005 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.0±0.2 0.039 +0.009 –0.008 L 0.5±0.2 0.020 +0.008 –0.009 M 0.125 +0.10 –0.05 0.005 +0.004 –0.002 N 0.10 0.004 P Q 1.4±0.1 0.055±0.004 0.125±0.075 0.005±0.003 R 3° +7° –3° 3° +7° –3° S 1.7 MAX. 0.067 MAX. S80GC-65-7ET-1 33 µPD16431A REFERENCE Document Name Document No. NEC Semiconductor Device Reliability/Quality Control System IEI-1212 Quality grade on NEC Semiconductor Devices IEI-1209 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: “Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11 34