TI TPS65131RGERG4

TPS65130, TPS65131
www.ti.com
SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
POSITIVE AND NEGATIVE OUTPUT DC-DC CONVERTER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Dual Adjustable Output Voltages Up to +15 V
and Down to –15 V
800-mA Typical Switch Current Limit at Boost
and Inverter Main Switches at TPS65130
2-A Typical Switch Current Limit at Boost and
Inverter Main Switches at TPS65131
Up to 89% Efficiency at Positive Output
Voltage Rail
Up to 81% Efficiency at Negative Output
Voltage Rail
Power-Save Mode for High Efficiency at Low
Load Currents
Independent Enable Inputs for Power Up and
Power Down Sequencing
Control Output for External PFET to Support
Completely Disconnecting the Battery
2.7-V to 5.5-V Input Voltage Range
Minimum 1.25-MHz Fixed Frequency PWM
Operation
Thermal Shutdown
Overvoltage Protection on Both Outputs
1-µA Shutdown Current
Small 4 mm x 4 mm QFN-24 Package (RGE)
Q1
L1
Small to Medium Size OLED Displays
(TFT) LCD and CCD Bias Supply
PDAs, Pocket PCs, Smartphones
Digital Cameras
Camcorders
DESCRIPTION
The TPS65130/1 is dual-output dc-dc converter generating a positive output voltage up to 15 V and a
negative output voltage down to -15 V with output
currents in a 200-mA range in typical applications,
depending on input voltage to output voltage ratio.
With a total efficiency up to 85%, the device is ideal
for portable battery-powered equipment. The input
voltage range of 2.7 V to 5.5 V allows the
TPS65130/1 to be directly powered from a Li-ion
battery, from 3 cells NiMH/NiCd or alkaline batteries.
The TPS65130/1 comes in a small 4 mm x 4 mm
QFN-24 package. Together with a minimum switching
frequency of 1.25 MHz it enables designing small
power supply applications because it requires only a
few small external components.
D1
VPOS
4.7 H
R1
R2
INP
VPOS
BSW
R7
C2
4.7 F
C3
0.1 F
C4
22 F
U1
C1
4.7 F
FBP
INN
VREF
VIN
FBN
ENP
VNEG
PSP
OUTN
ENN
CP
PSN
CN
GND
PGND
C8
0.22 F
R4
R3
VNEG
C7
C6
D2
L2
4.7 H
C5
22 F
TPS65130
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
TPS65130, TPS65131
www.ti.com
SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
The converter operates with a fixed frequency PWM control topology and, if power-save mode is enabled, it uses
a pulse-skipping mode at light load currents. It operates with only 500-µA device quiescent current. Independent
enable pins allow power up and power down sequencing for both outputs. The device has an internal current
limit overvoltage protection and a thermal shutdown for highest reliability under fault conditions.
ORDERING INFORMATION
TA
BOOST CONVERTER
(1)
PART NUMBER (1)
SWITCH CURRENT LIMIT
INVERTING CONVERTER
–40°C to 85°C
800 mA
800 mA
TPS65130RGE
–40°C to 85°C
1950 mA
1950 mA
TPS65131RGE
The RGE package is availabletaped and reeled. Add an R suffix to the device type (i.e.,
TPS65130RGER) toorder quantities of 3000 devices per reel. It is also available in minireels. Add a T
suffix to the device type (i.e., TPS65130RGET) toorder quantities of 250 devices per reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
TPS65130/1
VIN, INN
Input voltage range at pins
VPOS
Maximum voltage at pin
VNEG
Minimum voltage at pin
(2)
–0.3 V to +6.0 V
(2)
17 V
(2)
–17 V
Voltage at pins ENN, ENP, FBP, FBN, CN, CP, PSP, PSN, BSW
INP
Input voltage at pin
(2)
–0.3 V to VIN + 0.3 V
(2)
17 V
Differential voltage between pins OUTN to VINN (2)
24 V
TJ
Operating virtual junction temperature
–40°C to 150°C
TSTG
Storage temperature range
–65°C to 150°C
(1)
(2)
Stresses beyond those listedunder "absolute maximum ratings” may cause permanent damage to thedevice. These are stress ratings
only, and functional operation of the deviceat these or any other conditions beyond those indicated under "recommendedoperating
conditions” is not implied. Exposure to absolute-maximum-ratedconditions for extended periods may affect device reliability.
All voltage values are withrespect to network ground terminal, unless otherwisenoted.
DISSIPATION RATINGS TABLE (1)
PACKAGE
ΘJA
ΘJB
ΘJC
TA≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER
RATING
RGE
37.8 °C/W
27.8 °C/W
57.9 °C/W
2646 mW
26 mW/°C
1455 mW
1058 mW
(1)
2
This thermal data is based on assembly of the device on a JEDEC high K board. The PowerPAD must be soldered on a pad on the
board. There must be vias within the pad that contact the ground plane in the PCB. Exceeding the maximum junctiontemperature will
force the device into thermalshutdown.
TPS65130, TPS65131
www.ti.com
SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
VI
Input voltage range
2.7
5.5
V
TA
Operating free-air temperature range
-40
85
°C
TJ
Operating virtual junction temperature range
-40
125
°C
ELECTRICAL CHARACTERISTICS
Over recommended free-air temperature range and over recommended input voltage range, typical at an ambient
temperature of 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC-DC STAGE (VPOS, VNEG)
VPOS
Adjustable output voltage
range
VIN+ 0.5 V
15
V
VNEG
Adjustable output voltage
range
-15
-2
V
VREF
Reference voltage
IREF = 10 µA
1.225
V
IFBP
Positive feedback input
bias current
VFBP = VREF
50
nA
IFBN
Negative feedback input
bias current
VFBN = 0.1 VREF
50
nA
VFBP
Positive feedback regulation voltage
VIN = 2.7 V to 5.5 V
1.189
1.213
1.237
V
VFBN
Negative feedback regulation voltage
VIN = 2.7 V to 5.5 V
-0.024
0
0.024
V
1.2
Total Output DC accuracy
1.213
+3%
VIN = 3.6 V
440
620
VIN = 5.0 V
330
530
700
800
900
mA
1800
1950
2200
mA
VPOS = 5 V
230
300
VPOS = 10 V
170
200
700
800
900
mA
1800
1950
2200
mA
1500
kHz
RDS(ONN)
Inverter switch
on-resistance
ILIMN
TPS65130 Inverter switch
current limit
2.7 V < VIN < 5.5 V
ILIM
TPS65131 Inverter switch
current limit
VIN = 3.6 V
RDS(ONP)
Boost switch
on-resistance
ILIMP
TPS65130 Boost switch
current limit
2.7 V < VIN < 5.5 V
ILIMP
TPS65131 Boost switch
current limit
VIN = 3.6 V, VPOS = 8.0 V
DMAXP
Maximum duty cycle boost
converter
87.5%
DMAXN
Maximum duty cycle inverting converter
87.5%
DMINP
Minimum duty cycle boost
converter
12.5%
DMINN
Minimum duty cycle inverting converter
12.5%
mΩ
mΩ
CONTROL STAGE
fS
Oscillator frequency
VENP,ENN,PSP,PSN
High level input voltage
VENP,ENN,PSP,PSN
Low level input voltage
IENP,ENN,PSP,PSN
Input current
RBSW
Output resistance
VIN
Input voltage range
1250
1380
1.4
ENP, ENN, PSP,
PSN = GND or VIN
V
0.01
0.4
V
0.1
µA
27
2.7
kΩ
5.5
V
3
TPS65130, TPS65131
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SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
Over recommended free-air temperature range and over recommended input voltage range, typical at an ambient
temperature of 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIN
I(Q)
Quiescent current
ISD
Shutdown supply current
VUVLO
Undervoltage lockout
threshold
VPOS
VNEG
TYP
MAX
UNIT
VIN = 3.6 V, IOUTP = IOUTN = 0,
ENP = ENN = PSP = PSN =
VIN,
VPOS = 8 V, VNEG = -5 V
MIN
300
500
µA
100
120
µA
100
120
µA
ENN = ENP = GND
0.2
1.5
µA
2.35
2.7
V
2.1
Thermal shutdown
Thermal shutdown hyster- Junction temperature deesis
creasing
150
°C
5
°C
PIN ASSIGNMENTS
INP
VPOS
FBP
CP
NC
AGND
HTTSOP PowerPAD™
(TOP VIEW)
CN
VREF
FBN
VNEG
OUTN
OUTN
BSW
ENP
PSP
ENN
PSN
NC
INP
PGND
PGND
VIN
INN
INN
NC − No internal connection
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
INP
1, 24
I
Boost converter switch input.
INN
5, 6
I
Inverting converter switch input
PGND
2, 3
Power ground pin
AGND
19
Analog ground pin
ENN
10
I
Enable pin for the negative output voltage (0 V: disabled, VIN: enabled)
ENP
8
I
Enable pin for the positive output voltage (0 V: disabled, VIN: enabled)
FBN
16
I
Feedback pin for the negative output voltage divider
FBP
22
I
Feedback pin for the positive output voltage divider
OUTN
13, 14
O
Inverting converter switch output.
VREF
17
O
Reference output voltage. Bypass this pin with a 220-nF capacitor to ground. Connect the lower resistor of the
negative output voltage divider to this pin
CP
21
CN
18
VIN
4
I
Control supply input
VPOS
23
I
Positive output voltage sense input
VNEG
15
I
Negative output voltage sense input
4
Compensation pin for boost converter control
Compensation pin for inverting converter control
TPS65130, TPS65131
www.ti.com
SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
PIN ASSIGNMENTS (continued)
Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
PSP
9
I
Power-save mode enable for boost converter stage (0 V: disabled, VIN: enabled)
PSN
11
I
Power-save mode enable for inverter stage (0 V: disabled, VIN: enabled)
BSW
7
O
Gate control pin for external battery switch. This pin goes low when ENP is set high.
NC
12, 20
Not connected
FUNCTIONAL BLOCK DIAGRAM
INP
VPOS
VPOS
VIN
VIN
Gate
Control
VIN
ENP
PSP
CP
PGND
Boost Control
FBP
VREF
BSW
VIN
VIN
Temperature
Control
Oscillator
VIN
ENN
PSN
CN
VNEG
Inverting
Converter
Control
Gate
INN Control
FBN
VREF
VREF
INN
OUTN
GND
PGND
PGND
5
TPS65130, TPS65131
www.ti.com
SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS
PARAMETER MEASUREMENT INFORMATION
VIN
Q1
L1
D1
VPOS
4.7 H
R1
C1
4.7 F
C9
U1
INP
C2
4.7 F
C3
0.1 F
R2
VPOS
BSW
R7
C4
4x4.7 F
R8
FBP
INN
VREF
VIN
FBN
ENP
VNEG
PSP
OUTN
ENN
CP
PSN
CN
GND
PGND
C8
0.22 F
R4
R3
C10
R9
VNEG
C7
C6
D2
L2
4.7 H
TPS65130
List of Components
REFERENCE
DESCRIPTION
C1, C2
X7R/X5R ceramic
C4, C5
4x4.7 µF X7R/X5R ceramic
D1, D2
MBRM120
L1, L2
Wurth Elektronik 7447789004
(TPS65130), EPCOS B82462-G4472
(TPS65131)
PERFORMANCE GRAPHS
Table of Graphs
GRAPH
DESCRIPTION
Figure 1
TPS65130 maximum output current versus input voltage, VPOS = 12 V, 8 V, 5 V
Figure 2
TPS65131 maximum output current versus input voltage, VPOS = 15 V, 10 V, 5 V
Figure 3
TPS65130 maximum output current versus input voltage, VNEG = –4 V, –8 V, –10 V
Figure 4
TPS65131 maximum output current versus input voltage, VNEG = –4 V, –10 V, –15 V
Figure 5
TPS65130 efficiency versus output current, VPOS= 5 V
Figure 6
TPS65131 efficiency versus output current, VPOS= 5 V
Figure 7
TPS65130 efficiency versus output current, VPOS= 8 V
Figure 8
TPS65131 efficiency versus output current, VPOS= 10 V
Figure 9
TPS65130 efficiency versus output current, VPOS= 12 V
Figure 10
TPS65131 efficiency versus output current, VPOS= 15 V
Figure 11
TPS65130 efficiency versus output current, VNEG= –4 V, (VIN = 4 V, 3 V)
Figure 12
TPS65131 efficiency versus output current, VNEG= –4 V, (VIN = 5 V, 3 V)
Figure 13
TPS65130 efficiency versus output current, VNEG= –8 V, (VIN = 4.2 V, 3 V)
Figure 14
TPS65131 efficiency versus output current, VNEG= –10 V, (VIN = 5 V, 3 V)
Figure 15
TPS65130 efficiency versus output current, VNEG= –10 V, (VIN = 4.2 V, 3 V)
6
C5
4x4.7 F
TPS65130, TPS65131
www.ti.com
SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
Table of Graphs (continued)
GRAPH
DESCRIPTION
Figure 16
TPS65131 efficiency versus output current, VNEG= –15 V, (VIN = 5 V, 3 V)
Figure 17
TPS65130 efficiency versus input voltage, VPOS= 5 V in power-save mode
Figure 18
TPS65130 efficiency versus input voltage, VPOS= 8 V in power-save mode
Figure 19
TPS65130 efficiency versus input voltage, VPOS= 12 V in power-save mode
Figure 20
TPS65130 efficiency versus input voltage, VNEG= –4 V in power-save mode
Figure 21
TPS65130 efficiency versus input voltage, VNEG= –8 V in power-save mode
Figure 22
TPS65130 efficiency versus input voltage, VNEG= –10 V in power-save mode
Figure 23
TPS65130 efficiency versus output current, VO= 13.5 V (+9 V, –4.5 V), (VIN = 4.2 V, 3 V)
Figure 24
TPS65131 efficiency versus output current, VO= 30 V (±15 V, (VIN 5 V, 3 V)
Figure 25
TPS65130 efficiency versus input voltage, VO= 13.5 V (9 V, –4.5 V) in power save mode
Figure 26
TPS65130 output voltage versus output current, VPOS= 5 V, VIN = 3 V
Figure 27
TPS65131 output voltage versus output current, VPOS= 5 V, VIN = 4.2 V
Figure 28
TPS65130 output voltage versus output current, VPOS= 8 V, VIN = 3 V
Figure 29
TPS65131 output voltage versus output current, VPOS= 10 V, VIN = 5 V
Figure 30
TPS65130 output voltage versus output current, VPOS= 12 V (VIN = 3 V)
Figure 31
TPS65131 output voltage versus output current, VPOS= 15 V (VIN = 5 V)
Figure 32
TPS65130 output voltage versus output current, VNEG= –4 V, VIN = 3 V
Figure 33
TPS65131 output voltage versus output current, VNEG= –4 V, VIN = 5 V
Figure 34
TPS65130 output voltage versus output current, VNEG= –8 V, VIN = 3 V
Figure 35
TPS65131 output voltage versus output current, VNEG= –10 V, VIN = 5 V
Figure 36
TPS65130 output voltage versus output current, VNEG= –10 V, VIN = 3 V
Figure 37
TPS65131 output voltage versus output current, VNEG= –15 V, VIN = 5 V
Figure 38
No load supply current into VIN versus input voltage
Figure 39
No load supply current into VPOS versus input voltage
Figure 40
No load supply current into VNEG versus input voltage
Figure 41
Positive output voltage in continuous current mode
Figure 42
Negative output voltage in continuous current mode
Figure 43
Positive output voltage at power-save mode disabled
Figure 44
Negative output voltage at power-save mode disabled
Figure 45
Positive output voltage in power-save mode, VI = 3.6 V, VPOS = 5.5 V
Figure 46
Negative output voltage in power-save mode, VI = 3.6 V, VNEG = –8 V
Figure 47
Load transient response, VI = 3.6 V, VPOS = 8 V
Figure 48
Load transient response, VI = 3.6 V, VNEG = –8 V
Figure 49
Line transient response, VI = 3.6 V to 4.2 V, VPOS = 8 V
Figure 50
Line transient response, VI = 3.6 V to 4.2 V, VNEG = –8 V
Figure 51
Start-up after enable, VPOS = 8 V, VI = 3.6 V
Figure 52
Start-up after enable, VNEG = –8 V, VI = 3.6 V
7
TPS65130, TPS65131
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SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS
TPS65130
MAXIMUM OUTPUT CURRENT
vs
INPUT VOLTAGE
TPS65131
MAXIMUM OUTPUT CURRENT
vs
INPUT VOLTAGE
1000
2000
900
1800
Maximum Output Current − mA
Maximum Output Current − mA
TPS65131
800
700
VPOS = 5 V
600
500
VPOS = 8 V
400
300
VPOS = 12 V
200
VPOS = 5 V
1400
1200
1000
VPOS = 10 V
800
600
400
VPOS = 15 V
200
100
0
2.5
1600
2.9
3.3
3.7
4.1
4.5
4.9
0
2.5
5.3
2.9
VI − Input Voltage − V
Figure 1.
Figure 2.
TPS65130
MAXIMUM OUTPUT CURRENT
vs
INPUT VOLTAGE
TPS65131
MAXIMUM OUTPUT CURRENT
vs
INPUT VOLTAGE
400
4.9
5.3
1100
1000
Maximum Output Current − mA
VNEG = −4 V
350
Maximum Output Current − mA
3.3
3.7
4.1
4.5
VI − Input Voltage − V
300
250
VNEG = −8 V
200
150
VNEG = −10 V
100
TPS65131
900
VNEG = –4 V
800
700
600
VNEG = –10 V
500
400
300
VNEG = –15 V
200
50
100
0
2.5
2.9
3.3
3.7
4.1
4.5
VI − Input Voltage − V
Figure 3.
8
4.9
5.3
0
2.5
2.9
3.3
3.7
4.1
4.5
VI − Input Voltage − V
Figure 4.
4.9
5.3
TPS65130, TPS65131
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SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
TPS65130
EFFICIENCY
vs
OUTPUT CURRENT
TPS65131
EFFICIENCY
vs
OUTPUT CURRENT
100
90
100
VIN = 4.2 V
Power−Save Mode
VIN = 4.2 V
90
Power−Save Mode
80
80
VIN = 3 V
VIN = 3 V
70
Efficiency − %
Efficiency − %
70
60
50
40
30
60
50
40
30
Forced PWM
20
20
Forced PWM
10
VPOS = 5 V
0
0.10
1
10
100
TPS65131
VPOS = 5 V
10
0
0.1
1000
1
10
100
IO − Output Current − mA
IO − Output Current − mA
Figure 5.
Figure 6.
TPS65130
EFFICIENCY
vs
OUTPUT CURRENT
TPS65131
EFFICIENCY
vs
OUTPUT CURRENT
100
100
90
VIN = 4.2 V
90
Power−Save Mode
80
VIN = 5 V
VIN = 3 V
70
Efficiency − %
Efficiency − %
Power−Save Mode
80
VIN = 3 V
70
60
50
40
30
60
50
40
30
Forced PWM
20
20
10
0
0.10
1000
10
100
IO − Output Current − mA
Figure 7.
TPS65131
VPOS = 10 V
10
VPOS = 8 V
1
Forced PWM
1000
0
0.1
1
10
100
IO − Output Current − mA
1000
Figure 8.
9
TPS65130, TPS65131
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SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
TPS65130
EFFICIENCY
vs
OUTPUT CURRENT
TPS65131
EFFICIENCY
vs
OUTPUT CURRENT
100
90
100
VIN = 4.2 V
Power−Save Mode
80
80
VIN = 3 V
60
50
40
30
1
10
100
IO − Output Current − mA
Forced PWM
TPS65131
VPOS = 15 V
0
0.1
1000
1
10
100
1000
IO − Output Current − mA
Figure 9.
Figure 10.
TPS65130
EFFICIENCY
vs
OUTPUT CURRENT
TPS65131
EFFICIENCY
vs
OUTPUT CURRENT
100
VIN = 4 V
90
Power−Save Mode
80
60
50
40
Forced PWM
70
Efficiency − %
VIN = 3 V
30
VIN = 5 V
90
Power−Save Mode
70
Efficiency − %
40
10
VPOS = 12 V
100
60
VIN = 3 V
50
40
30
20
Forced PWM
20
10
1
10
100
Figure 11.
TPS65131
VNEG = −4 V
10
VNEG = −4 V
IO − Output Current − mA
10
50
20
10
0
0.10
60
30
Forced PWM
20
80
VIN = 3 V
70
Efficiency − %
Efficiency − %
70
0
0.10
VIN = 5 V
90
Power−Save Mode
1000
0
0.1
1
10
100
IO − Output Current − mA
Figure 12.
1000
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SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
TPS65130
EFFICIENCY
vs
OUTPUT CURRENT
TPS65131
EFFICIENCY
vs
OUTPUT CURRENT
100
100
VIN = 4.2 V
90
VIN = 5 V
90
Power−Save Mode
Power−Save Mode
80
Efficiency − %
70
VIN = 3 V
60
50
40
70
Efficiency − %
80
Forced PWM
30
VIN = 3 V
50
40
30
20
1
10
100
0
0.1
1000
1
10
100
IO − Output Current − mA
Figure 13.
Figure 14.
TPS65130
EFFICIENCY
vs
OUTPUT CURRENT
TPS65131
EFFICIENCY
vs
OUTPUT CURRENT
1000
100
100
90
VIN = 5 V
90
VIN = 4.2 V
Power−Save Mode
Power−Save Mode
80
VIN = 3 V
60
50
40
VIN = 3 V
70
Efficiency − %
70
Efficiency − %
TPS65131
VNEG = −10 V
10
VNEG = −8 V
IO − Output Current − mA
80
Forced PWM
20
10
0
0.10
60
60
50
40
Forced PWM
30
30
20
20
10
0
0.10
10
100
IO − Output Current − mA
Figure 15.
TPS65131
VNEG = −15 V
10
VNEG= −10 V
1
Forced PWM
1000
0
0.1
1
10
100
1000
IO − Output Current − mA
Figure 16.
11
TPS65130, TPS65131
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SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
TPS65130
EFFICIENCY
vs
INPUT VOLTAGE
TPS65130
EFFICIENCY
vs
INPUT VOLTAGE
100
100
IO = 100 mA
95
95
IO = 50 mA
90
90
75
70
70
60
60
VPOS = 5 V
In Power−Save Mode
2.9
3.3
3.7
4.1
4.5
VI − Input Voltage − V
4.9
50
2.5
5.3
2.9
3.3
3.7
4.1
4.5
VI − Input Voltage − V
Figure 17.
Figure 18.
TPS65130
EFFICIENCY
vs
INPUT VOLTAGE
TPS65130
EFFICIENCY
vs
INPUT VOLTAGE
100
95
95
IO = 100 mA
85
80
75
IO = 5 mA
70
IO = 50 mA
70
60
60
VPOS = 12 V
In Power−Save Mode
3.7
4.1
4.5
VI − Input Voltage − V
Figure 19.
4.9
IO = 5 mA
VNEG = −4 V
In Power−Save Mode
55
5.3
IO = 100 mA
75
65
3.3
5.3
80
65
55
4.9
90
IO = 50 mA
2.9
VPOS = 8 V
In Power−Save Mode
55
100
85
IO = 5 mA
75
65
90
Efficiency − %
80
65
55
12
Efficiency − %
IO = 5 mA
80
50
2.5
IO = 50 mA
85
Efficiency − %
Efficiency − %
85
50
2.5
IO = 100 mA
50
2.5
2.9
3.3
3.7
4.1
4.5
VI − Input Voltage − V
Figure 20.
4.9
5.3
TPS65130, TPS65131
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SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
TPS65130
EFFICIENCY
vs
INPUT VOLTAGE
100
100
95
95
90
90
IO = 100 mA
IO = 100 mA
IO = 50 mA
85
Efficiency − %
85
Efficiency − %
TPS65130
EFFICIENCY
vs
INPUT VOLTAGE
80
75
70
IO = 5 mA
80
75
70
65
65
60
60
VNEG = −8 V
In Power−Save Mode
55
50
2.5
2.9
3.3
3.7
4.1
4.5
VI − Input Voltage − V
4.9
IO = 5 mA
VNEG = −10 V
In Power−Save Mode
55
50
2.5
5.3
2.9
3.3
3.7
4.1
4.5
VI − Input Voltage − V
Figure 21.
Figure 22.
TPS65130
EFFICIENCY
vs
OUTPUT CURRENT
TPS65131
EFFICIENCY
vs
OUTPUT CURRENT
100
4.9
5.3
100
VIN = 4.2 V
90
Power−Save Mode
80
80
VIN = 3 V
VIN = 3 V
70
Efficiency − %
70
60
50
Forced PWM
40
30
60
50
40
30
20
Forced PWM
20
VO = 13.5 V
(9 V, −4.5 V)
10
0
0.10
VIN = 5 V
90
Power−Save Mode
Efficiency − %
IO = 50 mA
1
10
100
TPS65131
VO = 30 V
(15 V)
10
1000
0
0.1
1
10
100
IO − Output Current − mA
IO − Output Current − mA
Figure 23.
Figure 24.
1000
13
TPS65130, TPS65131
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SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
TPS65130
EFFICIENCY
vs
INPUT VOLTAGE
TPS65130
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
5.025
100
VPOS = 5 V
95
IO = 100 mA
IO = 50 mA
VPOS − Output Voltage − V
90
Efficiency − %
85
80
75
IO = 5 mA
70
65
VIN = 3 V
5
60
VO = 13.5 V
(9 V, −4.5 V)
55
50
2.5
4.975
2.9
3.3
3.7
4.1
4.5
VI − Input Voltage − V
4.9
5.3
0
Figure 26.
TPS65131
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
TPS65130
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
400
8.040
VPOS = 8 V
VPOS − Output Voltage − V
VO − Output Voltage − V
300
Figure 25.
TPS65131
VPOS = 5 V
VIN = 4.2 V
5
200
400
600
800
1000
IO − Output Current − mA
Figure 27.
14
200
I CC − Supply Current − mA
5.025
4.975
0
100
1200
VIN = 3 V
8
7.960
0
50
100
150
200
250
I CC − Supply Current − mA
Figure 28.
300
TPS65130, TPS65131
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SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
TPS65131
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
TPS65130
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
12.060
10.05
VPOS = 12 V
VPOS − Output Voltage − V
VO − Output Voltage − V
TPS65131
VPOS = 10 V
VIN = 5 V
10
9.95
0
200
400
600
VIN = 3 V
12
11.940
800
0
50
IO − Output Current − mA
Figure 29.
Figure 30.
TPS65131
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
TPS65130
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
15.075
150
200
−4.020
VNEG = −4 V
VNEG − Output Voltage − V
TPS65131
VPOS = 15 V
VO − Output Voltage − V
100
IO − Output Current − mA
VIN = 5 V
15
14.925
VIN = 3 V
−4
−3.980
0
100
200
300
400
500
IO − Output Current − mA
Figure 31.
600
0
50
100
150
200
250
IO − Output Current − mA
300
Figure 32.
15
TPS65130, TPS65131
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SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
TPS65131
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
TPS65130
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
−8.040
−4.05
VIN = 5 V
VNEG = −8 V
VNEG − Output Voltage − V
VO − Output Voltage − V
TPS65131
VNEG = −4 V
−4
−3.95
0
200
400
600
800
1000
VIN = 3 V
−8
−7.960
0
IO − Output Current − mA
Figure 33.
Figure 34.
TPS65131
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
TPS65130
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VNEG = − 10 V
VNEG − Output Voltage − V
VO − Output Voltage − V
TPS65131
VNEG = −10 V
VIN = 5 V
−10
VIN = 3 V
−10
−9.950
0
100
200
300
400
IO − Output Current − mA
Figure 35.
16
200
−10.050
−10.1
−9.9
50
100
150
IO − Output Current − mA
500
600
0
50
100
IO − Output Current − mA
Figure 36.
150
TPS65130, TPS65131
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SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
TPS65131
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
NO LOAD SUPPLY CURRENT INTO VIN
vs
INPUT VOLTAGE
−15.25
500
No Load Supply Current Into V IN − µ A
VO − Output Voltage − V
TPS65131
VNEG = −15 V
VIN = 5 V
−15
100
200
300
IO − Output Current − mA
400
250
200
150
NO LOAD SUPPLY CURRENT INTO VPOS
vs
INPUT VOLTAGE
NO LOAD SUPPLY CURRENT INTO VNEG
vs
INPUT VOLTAGE
105
TA = 85C
TA = 25C
90
TA = − 40C
80
75
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VI − Input Voltage − V
Figure 39.
No Load Supply Current Into VNEG µ−A
No Load Supply Current Into VPOS −
µA
TA = −40C
300
Figure 38.
95
85
TA = 25C
350
Figure 37.
105
100
TA = 85C
400
100
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VI − Input Voltage − V
−14.75
0
450
100
TA = 85C
95
TA = 25C
90
85
TA = − 40C
80
75
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3
VI − Input Voltage − V
Figure 40.
17
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SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
POSITIVE OUTPUT VOLTAGE
IN CONTINUOUS CURRENT MODE
VI = 3.6 V, RL = 20 Output Voltage
10 mV/div
NEGATIVE OUTPUT VOLTAGE
IN CONTINUOUS CURRENT MODE
VI = 3.6 V, RL = 30 Output Voltage
20 mV/div
Inductor Current
500 mA/div
Output Current
200 mA/div
VPOS = 5.5 V
VNEG = −8 V
t − Time − 500 ns/div
t − Time − 500 ns/div
Figure 41.
Figure 42.
POSITIVE OUTPUT VOLTAGE
AT POWER-SAVE MODE DISABLED
NEGATIVE OUTPUT VOLTAGE
AT POWER-SAVE MODE DISABLED
VI = 3.6 V, RL = 550 Output Voltage
10 mV/div
VI = 3.6 V, RL = 810 Output Voltage
10 mV/div
Inductor Current
200 mA/div
VPOS = 5.5 V
Inductor Current
200 mA/div
VNEG = −8 V
t − Time − 500 ns/div
Figure 43.
18
t − Time − 500 ns/div
Figure 44.
TPS65130, TPS65131
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SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
POSITIVE OUTPUT VOLTAGE
IN POWER-SAVE MODE
VI = 3.6 V, RL = 550 Output Voltage
20 mV/div, AC
NEGATIVE OUTPUT VOLTAGE
IN POWER-SAVE MODE
VI = 3.6 V, RL = 810 Output Voltage
50 mV/div, AC
VNEG = −8 V
Inductor Current
200 mA/div, DC
Inductor Current
200 mA/div, DC
VPOS = 5.5 V
t − Time − 10 s/div
t − Time − 50 s/div
Figure 45.
Figure 46.
LOAD TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
VI = 3.6 V, IL = 200 mA to 250 mA
Output Current
100 mA/div, DC
VI = 3.6 V, IL = 20 mA to 60 mA
Output Current
50 mA/div, DC
Output Voltage
200 mV/div, AC
VPOS = 8 V
Output Voltage
100 mV/div, AC
t − Time − 500 s/div
Figure 47.
VNEG = − 8 V
t − Time − 2 ms/div
Figure 48.
19
TPS65130, TPS65131
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SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
LINE TRANSIENT RESPONSE
VI = 3.6 V to 4.2 V, RL = 33 LINE TRANSIENT RESPONSE
VI = 3.6 V to 4.2 V, RL = 50 Input Voltage
500 mV/div, AC
Input Voltage
500 mV/div, AC
Output Voltage
200 mV/div, AC
VPOS = 8 V
Output Voltage
200 mV/div, AC
VNEG = −8 V
t − Time − 2 ms/div
t − Time − 2 ms/div
Figure 49.
Figure 50.
START-UP AFTER ENABLE
START-UP AFTER ENABLE
Enable
10 V/div, DC
Enable
5 V/div, DC
Output Voltage
5 V/div, DC
Output Voltage
5 V/div, DC
Inductor Current
500 mA/div, DC
Inductor Current
500 mA/div, DC
Voltage at SW
5 V/div, DC
VPOS = 8 V, VI =3.6 V,
RL = 80 Voltage at SW
10 V/div, DC
VNEG = −8 V, VI =3.6 V,
RL = 80 t − Time − 500 s/div
t − Time − 200 s/div
Figure 51.
Figure 52.
DETAILED DESCRIPTION
The TPS65130/1 operates with an input voltage range of 2.7 V to 5.5 V and can generate both a positive and
negative output. Both converters work independently of each other. They only share a common clock and a
common voltage reference. Both outputs are seperately controlled by a fixed-frequency, pulse-width-modulated
(PWM) regulator. In general, each converter operates at continuous conduction mode (CCM). At light loads, the
negative converter can enter discontinuous conduction mode (DCM). As the load current decreases, the
converters can enter a power-save mode if enabled. This works independently at both converters. Output
voltages can go up to 15 V at the boost output and down to –15 V at the inverter output.
20
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DETAILED DESCRIPTION (continued)
Power Conversion
Both converters operate in a fixed-frequency, PWM control scheme. So, the on-time of the switches varies
depending on input-to-output voltage ratio and the load. During this on-time, the inductors connected to the
converters are charged with current. In the remaining time, the time period set by the fixed operating frequency,
the inductors discharge into the output capacitors via the rectifier diodes. Usually at higher loads, the inductor
currents are continuous. At lighter loads, the boost converter uses an additional internal switch to allow current
flowing back to the input. This avoids inductor current becoming discontinuous in the boost converter. So, the
boost converter is always controlled in a continuous current mode. At the inverting converter, during light loads,
the inductor current can become discontinuous. In this case, the control circuit of the inverting controller output
automatically takes care of these changing conditions to always operate with an optimum control setup.
Control
The controller circuits of both converters are based on a fixed-frequency, multiple-feedforward controller
topology. Input voltage, output voltage, and voltage drop across the switches are monitored and forwarded to the
regulator. Changes in the operating conditions of the converters directly affect the duty cycle and must not take
the indirect and slow way through the output voltage control loops. Measurement errors in this feedforward
system are corrected by a self-learning control system. To avoid output voltage steps due to output changes of
this self-learning control system, its output is dampened by an external capacitor.
The voltage loops, determined by the error amplifiers, only have to handle small signal errors. The error
amplifiers are internally compensated. Their inputs are the feedback voltages on the FBP and FBN pins. These
voltages are compared with the internal reference voltage to generate an accurate and stable output voltage.
Power-Save Mode
The PSN and PSP can be used to select different operating modes. To enable power-save mode for the
corresponding converter, the dedicated PS pin must be set high. Power-save mode can be used to improve
efficiency at light load. In power-save mode, the converter only operates when the output voltage falls below a
set threshold voltage. It ramps up the output voltage with one or several operating pulses and goes again into
power-save mode once the inductor current goes discontinuous. The power-save mode can be disabled
seperately for each converter by setting the corresponding PS pin low.
Enable
Applying a low signal at the enable ENP or ENN pins shuts down the corresponding converter. When both
enable pins are tied low, the device enters shutdown mode, where all internal circuitry is turned off. The device
now just consumes low shutdown current flowing into the VIN pin. The output loads of the converters are
disconnected from the battery as described in the following paragraph. Pulling the enable pins high enables the
corresponding converter. Internal circuitry, necessary to operate the specific converter, is then turned on.
Load Disconnect
The device supports completely disconnecting the load, when the converters are disabled. At the inverting
converter, this is done by just turning off the internal PMOS switch. If the inverting converter is turned off, no DC
current path remains which could discharge the battery. This is different at the boost converter. The external
rectifying diode, together with the boost inductor, form a DC current path which could discharge the battery if any
load is connected at the output. The device has no internal switch to prevent current from flowing. For this
reason, a PMOS gate control output (BSW) is implemented. A PMOS switch can be placed into this DC current
path, ideally, directly between the boost inductor and battery. To be able to really disconnect the battery, the
forward direction of the parasitic backgate diode of this switch must point to the battery. The external PMOS
switch, connected to BSW, turns on when the boost converter is enabled and is turned off when the boost
converter is disabled.
21
TPS65130, TPS65131
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www.ti.com
DETAILED DESCRIPTION (continued)
Soft Start
Both converters have implemented soft-start functions. When each converter is enabled, the implemented switch
current limit ramps up slowly to its nominal programmed value in about 1 ms. Soft start is implemented to limit
the input current during start-up to avoid high peak currents at the battery which could interfere with other
systems connected to the same battery. Without soft start, uncontrolled input peak currents flow to charge up the
output capacitors and to supply the load during start-up. Their values could increase the implemented switch
current limit, which has serious impact to the converter itself and other parts of the system, by causing significant
voltage drops across the series resistance of the battery and its connections.
Overvoltage Protection
Both built-in converters have implemented overvoltage protection. If the feedback voltage under normal operation
exceeds the nominal value by typically 5%, the corresponding converter shuts down immediately to protect any
connected circuitry from possible damage.
Undervoltage Lockout
An undervoltage lockout prevents the device from starting up and operating if the supply voltage at VIN is lower
than the programmed threshold shown in the electrical characteristic table. The device automatically shuts down
both converters when the supply voltage at VIN falls below this threshold. Nevertheless, parts of the control
circuits remain active, which is different than device shutdown using EN inputs. The undervoltage lockout
function is implemented to prevent device malfunction.
Overtemperature Shutdown
The device automatically shuts down both converters if the implemented internal temperature detector detects a
chip temperature above the programmed theshold shown in the electrical characteristics table. It automatically
starts operating again when the chip temperature falls below this threshold. A built-in hysteresis avoids undefined
operation caused by ringing from shutdown and prevents operating at a temperature close to the
overtemperature shutdown threshold.
22
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SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
APPLICATION INFORMATION
Design Procedure
The TPS65130/1 dc-dc converter is intended for systems typically powered by a single-cell Li-ion or Li-polymer
battery with a terminal voltage between 2.7 V up to 4.2 V. Because the recommended input voltage goes up to
5.5 V, the device is also suitable for 3-cell alkaline, NiCd, or NiMH batteries, as well as any regulated supply
voltages between 2.7 V and 5.5 V. It provides two independent output voltage rails which are programmed as
follows.
Programming the Output Voltage
Boost Converter
The output voltage of the TPS65130/1 boost converter stage can be adjusted with an external resistor divider
connected to the FBP pin. The typical value of the voltage at the FBP pin is the reference voltage, which is 1.213
V. The maximum recommended output voltage at the boost converter is 15 V. To achieve appropriate accuracy,
the current through the feedback divider should be about 100 times higher than the current into the FBP pin.
Typical current into the FBP pin is 0.05 µA, and the voltage across R2 is 1.213 V. Based on those values, the
recommended value for R2 should be lower than 200 kΩ in order to set the divider current at 5 µA or higher.
Depending on the needed output voltage (VPOS), the value of the resistor R1 can then be calculated using
Equation 1:
V
R1 R2 POS 1
V
REF
(1)
As an example, if an 8-V output is needed, and a resistor of 180 kΩ has been chosen for R2, a 1-MΩ resistor is
needed to program the desired output voltage.
VIN
Q1
L1
D1
VPOS
4.7 H
R1
C1
4.7 F
C9
U1
INP
C2
4.7 F
C3
0.1 F
R2
VPOS
BSW
R7
C4
4x4.7 F
R8
FBP
INN
VREF
VIN
FBN
ENP
VNEG
PSP
OUTN
ENN
R3
C10
CN
GND
PGND
R9
VNEG
CP
PSN
C8
0.22 F
R4
C7
C6
D2
L2
4.7 H
C5
4x4.7 F
TPS65130
Inverting Converter
The output voltage of the TPS65130/1 inverting converter stage can also be adjusted with an external resistor
divider. It must be connected to the FBN pin. In difference to the feedback divider at the boost converter, the
reference point of the feedback divider is not GND; it is VREF. So the typical value of the voltage at the FBN pin is
0 V. The minimum recommended output voltage at the inverting converter is –15 V. Feedback divider current
23
TPS65130, TPS65131
SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
www.ti.com
APPLICATION INFORMATION (continued)
considerations are similar to the considerations at the boost converter. For the same reasons, the feedback
divider current should be in the range of 5 µA or higher. The voltage across R4 is 1.213 V. Based on those
values, the recommended value for R4 should be lower than 200 kΩ in order to set the divider current at the
required value. The value of the resistor R3, depending on the needed output voltage (VNEG), can be calculated
using Equation 2:
V
R3 R4 REF
V
V
NEG 1
REF
(2)
If as an example an output voltage of –5 V is needed and a resistor of 180 kΩ has been chosen for R4, a 750-kΩ
resistor is needed to program the desired output voltage.
Inductor Selection
An inductive converter normally requires two main passive components for storing energy during the conversion.
An inductor and a storage capacitor at the output are required. In selecting the right inductor, it is recommended
to keep the possible peak inductor current below the current-limit threshold of the power switch in the chosen
configuration. For example, the current-limit threshold of the switch for the boost converter and for the inverting
converter, is nominally 800 mA at TPS65130 and 1950 mA at TPS65131. The highest peak current through the
switches and the inductor depend on the output load, the input voltage (VIN), and the output voltages (VPOS,
VNEG). Estimation of the peak inductor current in the boost converter can be done using Equation 3. Equation 4
shows the corresponding formula for the inverting converter.
V
POS I
I
LP
OUTP
V 0.64
IN
(3)
V V
NEG I
I
IN
LN
OUTN
V 0.64
IN
(4)
The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it is
advisable to work with a ripple of less than 20% of the average inductor current. A smaller ripple reduces the
losses in the inductor, as well as output voltage ripple and EMI. But in the same way, output voltage regulation
gets slower, causing higher voltage changes at fast load changes. In addition, a larger inductor usually increases
the total system cost. Keeping those parameters in mind, the possible inductor value can be calculated using
Equation 5 for the boost converter and Equation 6 for the inverting converter.
V V
V
IN
POS
IN
L P
I f V
LP
S
POS
V V
IN
NEG
L N
V
I
f V
NEG
IN
LN
S
(5)
(6)
Parameter f is the switching frequency and ∆IL is the ripple current in the inductor, i.e., 20% x IL. VIN is the input
voltage, which is assumed to be at 3.3 V in this example. So, the calculated inductance value for the boost
inductor is 5.1 µH and for the inverting converter inductor is 5.1 µH. With these calculated values and the
calculated currents, it is possible to choose a suitable inductor. In typical applications, a 4.7-µH inductor is
recommended. The device has been optimized to work with inductance values between 3.3 µH and 6.8 µH.
Nevertheless, operation with higher inductance values may be possible in some applications. Detailed stability
analysis is then recommended. Care has to be taken for the possibility that load transients and losses in the
circuit can lead to higher currents as estimated in Equation 3 and Equation 4. Also, the losses caused by
magnetic hysteresis losses and copper losses are a major parameter for total circuit efficiency.
24
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SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
APPLICATION INFORMATION (continued)
The following inductor series from different suppliers have been used with the TPS65130/1 converter:
List of Inductors
VENDOR
EPCOS
INDUCTOR SERIES
B8246284-G4
7447789XXX
Wurth Elektronik
744031XXX
VLF3010
TDK
VLF4012
Cooper Electronics Technologies
SD12
Capacitor Selection
Input Capacitor
At least a 4.7-µF input capacitor is recommended for the input of the boost converter (INP) and for the input of
the inverting converter (INN) to improve transient behavior of the regulators and EMI behavior of the total power
supply circuit. A ceramic capacitor or a tantalum capacitor with a smaller ceramic capacitor (100 nF) in parallel,
placed close to the input pins, is recommended.
Output Capacitors
One of the major parameters necessary to define the capacitance value of the output capacitor is the maximum
allowed output voltage ripple of the converter. This ripple is determined by two parameters of the capacitor, the
capacitance and the ESR. It is possible to calculate the minimum capacitance needed for the defined ripple,
supposing that the ESR is zero, by using Equation 7 for the boost converter output capacitor and Equation 8 for
the inverting converter output capacitor.
I
V
V
OUTP
POS
IN
minP
f V V
S
P
POS
I
V
OUTN
NEG
C
minN
V
f V V
NEG
IN
S
N
C
(7)
(8)
Parameter f is the switching frequency and ∆V is the maximum allowed ripple.
With a chosen ripple voltage in the range of 10 mV, a minimum capacitance of 12 µF is needed. The total ripple
is larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using
Equation 9 for the boost converter and Equation 10 for the inverting converter.
V
I
R
ESRP
OUTP
ESRP
(9)
V
I
R
ESRN
OUTN
ESRN
(10)
An additional ripple of 2 mV is the result of using a typical ceramic capacitor with an ESR in a 10-mΩ range. The
total ripple is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the capacitor.
In this example, the total ripple is 10 mV. Additional ripple is caused by load transients. When the load current
increases rapidly, the output capacitor must provide the additional current until the inductor current has been
increased by the control loop by setting a higher on-time at the main switch (duty cycle). The higher duty cycle
results in longer inductor charging periods. But the rate of increase of the inductor current is also limited by the
inductance itself. When the load current decreases rapidly, the output capacitor needs to store the exessive
energy (stored in the inductor) until the regulator has decreased the inductor current by reducing the duty cycle.
The recommendation is to use higher capacitance values, as the aforegoing calculations show.
25
TPS65130, TPS65131
SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
www.ti.com
Stabilizing the Control Loop
Feedback Divider
To speed up the control loop, feedforward capacitors are recommended in the feedback divider, parallel to R1
(boost converter) and R3 (inverting converter). Equation 11 shows how to calculate the appropriate value for the
boost converter, and Equation 12 for the inverting converter.
6.8 s
C9 R1
(11)
7.5 s
C10 R3
(12)
To avoid coupling noise into the control loop from the feedforward capacitors, the feedforward effect can be
bandwith-limited by adding a series resistor. Any value between 10 kΩ and 100 kΩ is suitable. The higher the
resistance, the lower the noise coupled into the control loop system.
Compensation Capacitors
The control loops of both converters are completely compensated internally. The complex internal input voltage
output voltage, and input-current feedforward system has built-in error correction which requires external
capacitors. A 10-nF capacitor at CP of the boost converter and a 4.7-nF capacitor at CN of the inverting
converter is recommended.
Layout Considerations
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current paths and for the power ground
tracks. The input capacitors, output capacitors, the inductors, and the rectifying diodes should be placed as close
as possible to the IC to keep parasitic inductances low. Use a common ground node for power ground and a
different node for control grounds to minimize the effects of ground noise. Connect these ground nodes at any
place close to one of the ground pins of the IC.
The feedback dividers should be placed as close as possible to the control ground pin (boost converter) or the
VREF pin (inverting converter) of the IC. To lay out the control ground, it is recommended to use short traces as
well, seperated from the power ground traces. This avoids ground shift problems, which can occur due to
superimposition of power ground current and control ground current.
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues, such as thermal coupling, airflow, added
heatsinks and convection surfaces, and the presence of heat-generating components affect the
power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance follow.
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow to the system
The maximum recommended junction temperature (TJ) of the TPS65130/1 devices is 125°C. The thermal
resistance of the 24-pin QFN, 4x4-mm package (RGE) is RθJA = 37.8°C/W. Specified regulator operation is
ensured to a maximum ambient temperature TA of 85°C. Therefore, the maximum power dissipation is about
1058 mW. More power can be dissipated if the maximum ambient temperature of the application is lower.
T
T
A
P
JMAX
DMAX
R JA
(13)
26
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TPS65130RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS6
5130
TPS65130RGERG4
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS6
5130
TPS65130RGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS6
5130
TPS65130RGETG4
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS6
5130
TPS65131RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS6
5131
TPS65131RGERG4
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS6
5131
TPS65131RGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS6
5131
TPS65131RGETG4
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS6
5131
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS65131 :
• Automotive: TPS65131-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TPS65130RGER
VQFN
RGE
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
4.3
4.3
1.5
8.0
12.0
Q2
TPS65130RGET
VQFN
RGE
24
250
180.0
12.4
4.3
4.3
1.5
8.0
12.0
Q2
TPS65131RGER
VQFN
RGE
24
3000
330.0
12.4
4.3
4.3
1.5
8.0
12.0
Q2
TPS65131RGET
VQFN
RGE
24
250
180.0
12.4
4.3
4.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65130RGER
VQFN
RGE
24
3000
338.1
338.1
20.6
TPS65130RGET
VQFN
RGE
24
250
210.0
185.0
35.0
TPS65131RGER
VQFN
RGE
24
3000
338.1
338.1
20.6
TPS65131RGET
VQFN
RGE
24
250
210.0
185.0
35.0
Pack Materials-Page 2
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