SCAS133 − D3609, JULY 1990 − REVISED APRIL 1993 • • • • • • • DW PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible 3-State Inverted Outputs Back-to-Back Registers for Storage Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C CEBA A1 A2 A3 A4 GND GND GND GND A5 A6 A7 A8 CEAB description This 8-bit registered transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch enable (LEAB or LEBA) and output enable (GAB or GBA) inputs are provided for each register to permit independent control in either direction of data flow. The 74ACT11544 inverts data in both directions. 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 GBA LEBA B1 B2 B3 B4 VCC VCC B5 B6 B7 B8 LEAB GAB The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data to B. Having CEAB low and LEAB low makes the A-to-B latches transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and GAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B-to-A is similar, but requires the use of CEBA, LEBA, and GBA inputs. The 74ACT11544 is characterized for operation from − 40°C to 85°C. FUNCTION TABLE CEAB LEAB GAB LATCH STATUS A TO B† H X X Storing X H INPUTS OUTPUT BUFFERS B1 THRU B8 Z Storing X H Z L L L Transparent L H L Storing Current A Data Previous} A Data † A-to-B data flow is shown: B-to-A flow control is the same except uses CEBA, LEBA, and GBA. ‡ Data present before low-to-high transition of LEAB. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2−1 SCAS133 − D3609, JULY 1990 − REVISED APRIL 1993 logic symbol† GBA CEBA LEAB GAB CEAB LEAB A1 A2 A3 A4 A5 A6 A7 A8 28 1 27 15 14 16 logic diagram (positive logic) 1 EN3 G1 CEBA 1C5 2 EN4 LEBA G2 GAB 2C6 2 3 GBA 3 6D 5D 4 26 25 4 24 5 23 10 20 11 19 12 18 13 17 B1 B2 CEAB LEAB B3 A1 28 1 27 15 14 16 2 C1 1D 26 B1 B4 B5 C1 1D B6 B7 B8 To Seven Other Transceivers † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed. recommended operating conditions MIN NOM MAX 4.5 5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 IOL Dt /Dv TA Operating free-air temperature 2−2 High-level input voltage 2 UNIT V V 0.8 V VCC VCC V High-level output current −24 mA Low-level output current 24 mA 0 10 ns/ V − 40 85 °C Input transition rise or fall rate POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V SCAS133 − D3609, JULY 1990 − REVISED APRIL 1993 electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITIONS VCC IOH = − 50 mA A VOH II IOZ ICC Ci Control inputs 4.4 4.4 5.5 V 5.4 5.4 3.94 3.8 5.5 V 4.94 4.8 IOH = − 75 mA† 5.5 V MAX UNIT V 3.85 4.5 V 0.1 0.1 5.5 V 0.1 0.1 4.5 V 0.36 0.44 5.5 V 0.36 0.44 V IOL = 75 mA† VI = VCC or GND 5.5 V 5.5 V ± 0.1 ±1 mA VO = VCC or GND VI = VCC or GND, 5.5 V ± 0.5 ±5 mA 5.5 V 8 80 mA 5.5 V 0.9 1 mA IO = 0 One input at 3.4 V, Other inputs at GND or VCC DICC§ 4.5 V 4.5 V IOL = 24 mA Control inputs A or B ports‡ MIN IOH = − 24 mA IOL = 50 mA A VOL TA = 25°C MIN TYP MAX VI = VCC or GND VO = VCC or GND 5V 1.65 4.5 pF Co A or B ports 5V 12 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ For I/O ports, the parameter IOZ includes the input leakage current. § This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. pF timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration, LEAB or LEBA low Data before LEAB or LEBA↑ tsu Setup time th Hold time Data before CEAB or CEBA↑ Data after LEAB or LEBA↑ Data after CEAB or CEBA↑ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN 4 4 2.5 2.5 3 3 2 2 1.5 1.5 MAX UNIT ns ns ns 2−3 SCAS133 − D3609, JULY 1990 − REVISED APRIL 1993 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPLH tPHL LEBA or LEAB A or B tPZH tPZL CEBA or CEAB A or B tPHZ tPLZ CEBA or CEAB A or B tPZH tPZL GBA or GAB A or B tPHZ tPLZ GBA or GAB A or B MIN TA = 25°C TYP MAX MIN MAX 2.4 5.7 8.2 2.4 8.9 4.1 7.3 9.3 4.1 10.3 2.6 6 8.7 2.6 9.5 3.4 7.1 10.1 3.4 11 3.3 6.7 9.5 3.3 10.4 3.6 8.2 11.2 3.6 13 4.8 7.6 9.7 4.8 10.4 4.7 7.6 9.5 4.7 10.2 3 6.4 9 3 9.9 3.5 7.8 10.8 3.5 12.5 4.6 7.3 9.3 4.6 9.9 4.6 7.2 9.2 4.6 9.7 UNIT ns ns ns ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS Outputs enabled Cpd 2−4 Power dissipation capacitance per transceiver Outputs disabled POST OFFICE BOX 655303 TYP UNIT 47 CL = 50 pF, • DALLAS, TEXAS 75265 f = 1 MHz 14 pF SCAS133 − D3609, JULY 1990 − REVISED APRIL 1993 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND 500 Ω LOAD CIRCUIT 3V Timing Input (see Note B) 1.5 V 0V tw tsu 3V Input 1.5 V th 1.5 V 3V 1.5 V 1.5 V Data Input 0V 0V VOLTAGE WAVEFORMS Output Control (low-level enabling) 3V Input (see Note B) 1.5 V 1.5 V 0V tPHL tPLH In-Phase Output 50% VCC VOH 50% VCC VOL 50% VCC 3V VOH 50% VCC VOL Output Waveform 2 S1 at GND (see Note C) 1.5 V 1.5 V 0V tPZL tPLZ Output Waveform 1 S1 at 2 × VCC (see Note C) tPLH tPHL Out-of-Phase Output VOLTAGE WAVEFORMS 50% VCC 20% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS [ VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2−5 SCAS133 − D3609, JULY 1990 − REVISED APRIL 1993 2−6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74ACT11544DW OBSOLETE SOIC DW 28 TBD Call TI Call TI 74ACT11544NT OBSOLETE PDIP NT 28 TBD Call TI Call TI 74ACT11544NT OBSOLETE PDIP NT 28 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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