PAS106BCA-323 PAS106BBA-323 PAS106BCA-323 SINGLE-CHIP CMOS CIF COLOR DIGITAL IMAGE SENSOR PAS106BBA-323 SINGLE-CHIP CMOS CIF B&W DIGITAL IMAGE SENSOR General Description The PAS106BCA-323/PAS106BBA-323 is a highly integrated CMOS active-pixel image sensor that has a CIF resolution of 356H x 292V. To have an excellent image quality, the PAS106BCA-323/PAS106BBA-323 outputs 10-bit RGB raw data through a parallel data bus. It is available in color or monochrome in 32-pin LCC package. The PAS106BCA -323/PAS106BBA-323 can be programmed to set the exposure time for different luminance condition via I2CTM serial control bus. By programming the internal register sets, it performs on-chip frame rate adjustment, offset correction DAC and programmable gain control. Features § CIF(356 x 292 pixels) resolution, ~1/5” Lens Key Specification Supply Voltage 3.3V + 5% § On-chip 10-bit pipelined A/D converter Array formate 356(H) x 292(V) § Output format: 10-bit parallel RGB raw data Optical format ~1/5 ” § On-chip 6-bit (1 sign bit+ 5 magnitude bit) background compensation DAC Pixel Size 7.25µm x 7.25µm Frame rate 30 fps § Bayer-RGB color filter array § On-chip programmable gain amplifier q 5-bit color gain amplifier(x4) q 5-bit global gain amplifier (x5) § Continuous variable frame time(1/2sec~1/30sec) System clock Max. pixel rate Up to 48 MHz 4 MHz § Continuous variable exposure time § I2C Interface § Digitally programmable registers § Single 3.3V supply voltage § 100 mW low power dissipation Sensitivity 1.0V/Lux-sec PGA gain 31.6 dB max. Color filter Exposure Time RGB Bayer Pattern ~ Frame time to 1/ 160000 Scan Mode Progressive S/N Ratio >45dB Package 32-pin LCC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 1/14 V2.0, May 2002 PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC 1. Pin Assignment Pin No. Name Type Definition 1 2 VSSA VRB GND BYPASS Analog ground Analog voltage reference 3 4 5 VRT VCM VDDA BYPASS BYPASS PWR Analog voltage reference Analog voltage reference Analog VDD, 3.3V 6 7 8 VDDA VDDAY1 VDDAY2 PWR PWR PWR Analog VDD, 3.3V Analog VDD, 3.3V Analog VDD, 3.3V 9 10 11 VSSAY CSB PXD9 GND IN OUT Analog ground Chip select (Low, active, chip disable if high) Digital data out 12 13 14 PXD8 PXD7 PXD6 OUT OUT OUT Digital data out Digital data out Digital data out 15 16 17 PXD5 PXD4 VDDQ OUT OUT PWR Digital data out Digital data out Digital VDD, 3,3V 18 19 20 VSSQ PXD3 PXD2 GND OUT OUT Digital ground Digital data out Digital data out 21 22 23 PXD1 PXD0 PXCLK OUT OUT OUT Digital data out Digital data out Pixel clock output 24 25 26 HSYNC VSYNC SYSCLK OUT OUT IN Horizontal synchronization signal Vertical synchronization signal Master clock input 27 28 29 SCL SDA VDDD IN I/O PWR I2C clock I2C data Digital VDD, 3.3V 30 31 32 VSSD VSSA VLRST GND GND BIAS Digital ground Analog ground Fixed bias input voltage, 1.65V All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 2/ 14 V2.0, May 2002 PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC Row Decoders 2. Block Diagram 6-bit +/-1V DAC Sensor Array Color gain B,G1,G2,R 5-bits X4 CDS ckts Col. Decoders Global gain 5-bits X5 cmd Timing & Digital Control 10-bit pipelined ADC Pxo<9:0> PXCLK Vsync Hsync Register sets SDA SCL SysClk I2C Interface All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 3/ 14 V2.0, May 2002 PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC 3. Pixel Array And Pixel Color Pattern The output image format of PAS106BCA-323/PAS106BBA -323 is CIF (352x288 pixel array). To provide the co-processor with the extra information it needs for interpolation at the edges of the pixel array, an border of 2 pixels on all 4 sides of the array are available. Fig 3.1. illustrates the pixel array and pixel color pattern. 30 dark pixel 30 dark pixel 20 R pixel Dark pixel G2 R G2 R B G1 B G1 G2 R G2 R 30 dark pixel 20 G pixel R 30 dark pixel 20 B pixel G B 20 pixel No filter Dark pixel G2 R G2 R B G1 B G1 G2 R G2 R Row 293 Row 292 Array: 356(column)x 294(row) B G1 B G1 G2 R G2 R B G1 B G1 Dark pixel 30 dark pixel R G B No filter 20 R pixel 20 G pixel 20 B pixel 20 pixel 30 dark pixel 30 dark pixel 294 row lines B G1 B G1 G2 R G2 R B G1 B G1 Dark pixel Row 1 Row 0 30 dark pixel 356 column lines Fig 3.1. Pixel array and pixel color pattern Note: 1. Pixel color pattern does not apply to monochrome sensor. 2. Pixel read-out proceeds from left to right, and from bottom row to top row. 3. Pixel array not drawn to scale. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 4/ 14 V2.0, May 2002 PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC 4. Output timing: Fixed pixel clock for each line(row), 444pxclk. 4+4 blank pxclk for each line. ( See Fig 4.1. ) 1+1 Dark line for each frame.(See Fig 4.2. ) Dark line output format: Fig 4.3. line time = 80+4+2+352+2+4 = 444 pxclks Hsync. xx x 80 pxclks x x x x 2+352+2 pixels out B G1 B G1 Pxclk_a x xx x x x x x 2+352+2 pixels out Note: "x" indicates don't care PXD[9:0] Fig 4.1. Inter-line timing Frame time (=294 lines) Vsync. 80 Pxclks Hsync. Dark 80 Pxclks Dark B,G1,B,G1... Dark G2,R,G2,R... Dark Valid frame data (292 lines) Fig 4.2. Inter-frame timing 4+356+4=364 pxclks Hsync Hsync 80 pxclks 80 pxclks xxx x 28 dark pixels R G B No filfter 20 R pixels 20 G pixels 20 B pixels 20 pixels 30 dark pixels 30 dark pixels xxx x 30 dark pixels Note: "x" indicates don't care. Fig 4.3. Dark line output format All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 5/ 14 V2.0, May 2002 PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC 5. I2C Bus PAS106BCA-323/PAS106BBA-323 supports I2C-bus transfer protocol and is acting as slave device. The 7 bits unique slave address is 1000000 and supports receiving / transmitting speed up to 400kHz. 5.1 I2C bus overview § Only two wires SDA (serial data) and SCL (serial clock) carry information between the devices connected to the I2C bus. Normally both SDA and SCL lines are open collector structure and pull high by external pull-up resistors. § Only the master can initiates a transfer (start), generates clock signals, and terminates a transfer (stop). § Start and stop condition: A high to low transition of the SDA line while SCL is high defines a start condition. A low to high transition of the SDA line while SCL is high defines a stop condition. Please refer to Fig 5.1. § Valid data: The data on the SDA line must be stable during the high period of the SCL clock. Within each byte, MSB is always transferred first. Read/write control bit is the LSB of the first byte. Please refer to Fig 5.2. § Both the master and slave can transmit and receive data from the bus. § Acknowledge: The receiving device should pull down the SDA line during high period of the SCL clock line when a complete byte was transferred by transmitter. In the case of a master received data from a slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master read cycle. SDA SCL S P Start Condition Stop Condition Fig 5.1 Start and Stop Conditions All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 6/ 14 V2.0, May 2002 PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC SDA DATA CHANGE ALLOWED DATA STABLE SCL Fig 5.2 Valid Data 5.2 Data Transfer Format 5.2.1 Master transmits data to slave (write cycle) § S : Start § A : Acknowledge by slave § P : Stop § RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW=1 read cycle, RW=0 write cycle. § SUBADDRESS : The address values of PAS106BCA-323/PAS106BBA-323 internal control registers (Please refer to PAS106BCA-323/PAS106BBA-323 register description) 1ST BYTE S SLAVE ID (7 BIT) MSB 2ND BYTE RW A n BYTEs + A SUBADDRESS (8 BIT) A DATA A DATA A P LSB=0 During write cycle, the master generates start condition and then places the 1st byte data that are combined slave address (7 bits) with a read/write control bit to SDA line. After slave(PAS106BCA-323/PAS106BBA-323) issues acknowledgment, the master places 2nd byte (sub-address) data on SDA line. Again follow the PAS106BCA-323/PAS106BBA-323 acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS106BCA-323/PAS106BBA-323 control register (address was assigned by 2nd byte). After PAS106BCA-323/PAS106BBA-323 issue acknowledgment, the master can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the PAS106BCA-323/PAS106BBA-323 sub-address is automatically increment after each DATA byte transferred. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 7/ 14 V2.0, May 2002 PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC The data and A cycles is repeat until last byte write. Every control registers value inside PAS106BCA-323/PAS106BBA-323 can be programming via this way. (Please refer to Fig 5.3.) 5.2.2 Slave transmits data to master (read cycle) § The sub-address was taken from previous write cycle § The sub-address is automatically increment after each byte read § Am : Acknowledge by master § Note there is no acknowledgment from master after last byte read 1ST BYTE S 2ND BYTE SLAVE ADDRESS (7 BITS) RW A n BYTE DATA (8 BIT) Am DATA Am DATA 1 P NO ACK IN LAST BYTE During read cycle, the master generates start condition and then place the 1st byte data that are combined slave address (7 bits) with a read/write control bit to SDA line. After issue acknowledgment, 8 bits DATA was also placed on SDA line by PAS106BCA-323/PAS106BBA-323. The 8 bit data was read from PAS106BCA-323/PAS106BBA-323 internal control register that address was assigned by previous write cycle. Follow the master acknowledgment, the PAS106BCA-323/PAS106BBA-323 place the next 8 bits data (address is increment automatically) on SDA line and then transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read, Am is no longer generated by master but instead by keep SDA line high. The slave (PAS106BCA-323/PAS106BBA-323) must releases SDA line to master to generate STOP condition. (Please refer to Fig 5.3.) SDA SCL 1-7 8 9 1-7 8 9 1-7 8 9 P S Start Condition Address R/W ACK from Receiver Data ACK from Receiver Data ACK from Receiver Stop Condition Fig 5.3 Data Transfer Format All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 8/ 14 V2.0, May 2002 PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC 5.3 I2C Bus Timing SDA tf tHD;STA tf tLOW tr tBUF tr tSP tSU;DAT SCL S tHD;STA t HD;DAT tHIGH tSU;STA tSU;STO Sr P S 5.4 I2C Bus Timing Specification STANDARD-MODE PARAMETER SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated. Low period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time. For I2C-bus device Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START Capacitive load for each bus line Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) SYMBOL UNIT MIN. MAX. fscl tHD:STA 10 4.0 400 - kHz us tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb VnL 4.7 0.75 4.7 0 250 30 30 4.0 4.7 1 0.1 VDD 3.45 N.D. N.D. 15 - us us us us ns ns(note1) ns(note1) us us pF V VnH 0.2 VDD - V Note1: It depends on the "high" period time of SCL. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 9/ 14 V2.0, May 2002 PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC 6. Specifications Absolute Maximum Ratings Symbol Parameter Min Max Unit Vdd DC supply voltage -0.5 3.8 V Vin DC input voltage 0.5 Vdd+0.5 V Vout DC output voltage -0.5 Vdd+0.5 V Tstg Storage temperature 0 70 ℃ DC Electrical Characteristics (VDD=3.3V±5%, Ta=0°C~40°C ) Symbol Parameter Min. Typ. 3.15 3.3 Max. Unit Type :PWR VDD Analog and digital operating voltage IDD Operating Current Type :IN & I/O Reset and SYSCLK 3.45 35 V mA VIH Input voltage HIGH 2.0 VDD V VIL Input voltage LOW 0 0.8 V Cin Input capacitor 10 pF Ilkg Input leakage current 1.0 uA Type : OUT & I/O for PXD0:9, PXCLK, H/VSYNC & SDA, load 10pf, 1.2kΩ, 3.3 volts VOH Output voltage HIGH VOL Output voltage LOW Vdd-0.2 V 0.2 V Max. Unit 48 MHz 4 MHz AC Operating Condition Symbol Parameter fsysclk Master clock frequency fpxclk Pixel clock output frequency Min. Typ. 8 Sensor Characteristics (To be determined) Parameter Photo response non-uniformity Symbol Min. Typ. Max. Unit PRNU 1.02 % Saturation output voltage Vsat. 1.4 V Dark output voltage Vdark 52 mV/sec Dark signal non-uniformity DSNU 1.9 Lsb Sensitivity ( Red channel ) R 1.2 V/Lux-sec Sensitivity ( Green channel ) G 1.0 V/Lux-sec Sensitivity ( Blue channel ) B 0.8 V/Lux-sec Note All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 10/14 V2.0, May 2002 PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC 7. Package Information SDA 24 SCL 23 SYSCLK PXCLK 22 VSYNC PXD0 21 HSYNC PXD1 7.1. Pin Connection Diagram 25 26 27 28 VSSQ 18 31 VSSA VDDQ 17 32 VLRST PXD4 16 1 VSSA PXD5 15 2 VRB PXD6 14 3 VRT PXD7 13 4 VCM 12 11 10 9 8 7 6 5 VDDA VSSD VDDA 30 VDDAY1 19 VDDAY2 PXD3 VSSAY VDDD CSB 29 PXD9 20 PXD8 PXD2 -- Bottom View -- All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 11/ 14 V2.0, May 2002 PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC 7.2. Package Outline All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 12/14 V2.0, May 2002 PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC 7.3. Sensor center and Die&Package center bias Sensor Center = Package Center Chip Center Logo All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 13/14 V2.0, May 2002 PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC 8. Referencing Circuit Schematic CSB_SW VDDD 2 1 R1 VDDA CSB 300k PXD9 5 VDDA 7 6 VDDA VDDAY1 9 10 11 8 VDDAY2 VSSAY CSB PXD0 C3 C4 0.1uF 0.1uF 4 VDDA 3 2 C5 10uF R2 1 C6 32 C7 C8 VLRST 300k VLRST 1uF 1uF 1uF 31 R3 30 29 VDDD SDA PXD1 C2 0.1uF 0.1uF 300k C10 0.1uF 28 PAS106_32 VDDD SCL PXD2 SYSCLK 20 VSSD 27 PXD2 PXD3 26 19 VLRST VSSA VSYNC PXD3 VSSA VSSQ 25 0.1uF VDDQ HSYNC C9 18 24 17 DGND VRB PAS106BCA-323 PAS106BBA-323 PXCLK VDDD PXD5 PXD4 VCM VRT 23 16 PXD9 15 PXD4 C1 U2 PXD6 PXD0 PXD5 PXD7 PXD1 14 22 13 PXD6 21 PXD7 PXD8 12 AGND PXD8 3.3V R4 4.7k R5 4.7k PXCLK L1 HSYNC 3.3UH VSYNC VDDD VDDA SYSCLK C11 C12 C13 C14 1uF 10uF 10uF 1uF SCL SDA L2 3.3UH DGND AGND NOTES on capacitors: 1.The 0.1uF caps for power pins lengths LESS than 5mm. MUST have trace Title PAS106_SENSOR-32PINS.opj 2.C5,C7 and C8 for pins 2,3 and 4 MUST have trace lengths LESS than 5mm. Size A4 Date: Document Number Rev V2.1 Wednesday, May 22, 2002 All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] Sheet 1 14/14 V2.0, May 2002 of 1