PAS6371LT Specification PAS6371LT CMOS VGA DIGITAL IMAGE SENSOR General Description The PAS6371LT is a highly integrated CMOS active-pixel image sensor that has a VGA YUV output of 640 x 480 pixels. It embedded the new FinePixel™ sensor technology to perform the excellent image quality. PAS6371LT outputs YUV/YCbCr 4:2:2 or RGB565/555/444 data through a parallel data bus. It is available in 29-pin CSP. Features Resolution: 640 x 480 pixels Bayer-RGB color filter array Key Specification Resolution 640 (H) x 480 (V) Analog 2.5V ~ 3.0V I/O 1.8V ~ 3.3V Core 1.8V Output format (8-bit): z YUV/YCbCr 4:2:2 (VGA, QVGA … ) z RGB565/555/444 (VGA, QVGA … ) On-chip 10-bit pipelined A/D converter Power On-chip 2-stage background compensation DAC Pixel Size Continuous variable frame time & exposure time Lens Chief Ray Angle I2CTM Interface Frame rate Flash light timing Max. System clock 4.5µmx4.5µm 28degree 30fps, VGA YUV mode 48MHz Support 1.8V~3.3V I/O power 10uA low power-down dissipation (VDD-A = VDD-IO = 2.8V, VDD-C = 1.8V) Automatic Background Compensation AEC & AGC function DSP function: z AWB z Gamma z Color matrix z Sharpness z De-noise z Color saturation z Defect compensation z Lens shading compensation WOI & Sub-sampling Max. Pixel clock 24MHz, VGA YUV mode Sensitivity 2.1V/(Lux*Sec) Color filter RGB Bayer Pattern Exposure Time ~ Frame time to Line time Scan Mode Progressive S/N Ratio 41dB Dynamic range 60dB Package 29-pin CSP Critical Register table backward compatible with PAS6311 All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] V1.1, 1 2008/04/09 PixArt Imaging Inc. PAS6371LT 1. CMOS Image Sensor IC Pin Assignment Pin No. A1 A2 A3 A4 A5 B1 B2 B4 B5 C1 C2 C3 C4 C5 D1 D2 D3 D4 D5 E1 Name CSB VDDMA VREF1 VREF2 VREF3 VSYNC RSTN VREF4 VSSAY VDDMD HSYNC PX6 PX7 VSSA VDDD SDA PX2 PX5 VSSD VSSD Type IN PWR Ref Ref Ref OUT IN Ref GND PWR OUT OUT OUT GND PWR I/O OUT OUT GND GND Description Power down enable, active high Analog power, 2.5V ~ 3.0V Internal voltage reference Internal voltage reference Internal voltage reference Vertical synchronization signal output Reset mode enable, active low Internal voltage reference Sensor array ground I/O power, 1.8V ~ 3.3V Horizontal synchronization signal output Digital data output Digital data output Analog ground Digital core power, 1.8V I2C data Digital data output Digital data output Digital ground Digital ground All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] V1.1, 2 2008/04/09 PixArt Imaging Inc. PAS6371LT E2 E3 E4 E5 F1 F2 F3 F4 F5 CMOS Image Sensor IC SYSCLK PX1 PX3 PX9 SCL PXCLK PX0 PX4 PX8 IN OUT OUT OUT IN OUT OUT OUT OUT External clock input Digital data output Digital data output Digital data output I2C clock input Pixel clock output Digital data output Digital data output Digital data output All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] V1.1, 3 2008/04/09 PixArt Imaging Inc. PAS6371LT 2. CMOS Image Sensor IC Specifications Absolute Maximum Ratings Ambient Storage Temperature -25℃~125℃ Supply Voltage ( with respect to ground ) VDDD 3.0V VDDMA 4.5V VDDMD 4.5V All Input / Output Voltage ( with respect to ground ) -0.3V to VDDMD+0.5V Lead-free temperature, Surface-mount process 245℃ ESD rating, Human Body model 2000V DC Electrical Characteristics ( Ta = 0℃ ~ 70℃ ) Symbol Parameter Min. Typ. Max. Unit Type : POWER VDDMA DC supply voltage – Analog 2.5 2.8 3.0 V VDDD DC supply voltage – Digital core 1.62 1.8 1.98 V VDDMD DC supply voltage – I/O 1.62 3.3 V a IDD Operating Current (see Note ) 29 IPWDN Power Down Current (see Noteb) 10 mA 20 µA Type : IN & I/O Reset and System Clock(input clock) VIH Input Voltage HIGH VIL Input Voltage LOW VDDMD * 0.7 V VDDMD * 0.3 V Type : OUT & I/O for PX0 : 9, SDA, H/VSYNC and PXCLK(output clock) VOH Output Voltage HIGH VOL Output Voltage LOW VDDMD * 0.9 V VDDMD * 0.1 V Notea: VDDMA=2.8V, VDDD=1.8V, VDDMD=3.3V, 30fps VGA YUV output, without I/O loading Noteb: VDDMA=2.8V, VDDMD=3.3V AC Operating Condition Symbol Parameter fsysclk System clock frequency tsysclk_dc System clock duty cycle Min. Typ. Max. 24 45 MHz 55 All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] Unit V1.1, % 4 2008/04/09 PixArt Imaging Inc. PAS6371LT CMOS Image Sensor IC Sensor Characteristics Parameter Typ. Unit Sensitivity 2.1 V/Lux-sec Signal to Noise Ratio 41 dB Dynamic Range 60 dB All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] V1.1, 5 2008/04/09 PixArt Imaging Inc. PAS6371LT 3. CMOS Image Sensor IC Output timing VGA YUV output timing All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] V1.1, 6 2008/04/09 PixArt Imaging Inc. PAS6371LT 4. CMOS Image Sensor IC I2CTM Bus PAS6371LT supports I2C bus transfer protocol and acts as slave device. The 7-bits unique slave address is “1000000” and supports receiving / transmitting speed as maximum 400KHz. I2C Bus Overview z Only two wires SDA ( serial data ) and SCL ( serial clock ) carry information between the devices connected to the I2C bus. Normally both SDA and SCL lines are open collector structure and pulled high by external pull-up resistors. z Only the master can initiates a transfer ( start ), generates clock signals, and terminates a transfer ( stop ). z Start and stop condition : A high to low transition of the SDA line while SCL is high defines a start condition. A low to high transition of the SDA line while SCL is high defines a stop condition. Please refer to Figure 2.1. z Valid data : The data on the SDA line must be stable during the high period of the SCL clock. Within each byte, MSB is always transferred first. Read / Write control bit is the LSB of the first byte. Please refer to Figure 2.2. z Both the master and slave can transmit and receive data from the bus. z Acknowledge : The receiving device should pull down the SDA line during high period of the SCL clock line when a complete byte was transferred by transmitter. In the case of a master received data from a slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master read cycle. Figure 2.1 Start and Stop conditions Figure 2.2 Valid Data All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] V1.1, 7 2008/04/09 PixArt Imaging Inc. PAS6371LT CMOS Image Sensor IC Data Transfer Format Master transmits data to salve ( write cycle ) z S : Start. z A : Acknowledge by salve. z P : Stop. z RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW = 1 – Read cycle, RW = 0 – Write cycle. z SUBADDRESS : The address values of PAS6371LT internal control registers. ( Please refer to PAS6371LT register description ) During write cycle, the master generates start condition and then places the 1st byte data that are combined slave address ( 7 bits ) with a read / write control bit to SDA line. After slave ( PAS6371LT ) issues acknowledgment, the master places 2nd byte ( Sub Address ) data on SDA line. Again follow the PAS6371LT acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS6371LT control register ( address was assigned by 2nd byte ). After PAS6371LT issues acknowledgment, the master can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the PAS6371LT sub-address is automatically increment after each DATA byte transferred. The data and A cycles is repeat until last byte write. Every control registers value inside PAS6371LT can be programming via this way. Slave transmits data to master ( read cycle ) z The sub-address was taken from previous write cycle. z The sub-address is automatically increment after each byte read. z Am : Acknowledge by master. z Note there is no acknowledgment from master after last byte read. During read cycle, the master generates start condition and then place the 1st byte data that are combined slave address ( 7 bits ) with a read / write control bit to SDA line. After issue acknowledgment, 8 bits DATA was also placed on SDA line by PAS6371LT. The 8 bits data was read from PAS6371LT internal control register that address was assigned by previous write cycle. Follow the master acknowledgment, the PAS6371LT place the next 8 bits data ( address is increment automatically ) on SDA line and then transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read, Am is no longer generated by master but instead by keep SDA line high. The slave ( PAS6371LT ) must releases SDA line to master to generate STOP condition. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] V1.1, 8 2008/04/09 PixArt Imaging Inc. PAS6371LT CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] V1.1, 9 2008/04/09 PixArt Imaging Inc. PAS6371LT CMOS Image Sensor IC I2CTM Bus Timing I2CTM Bus Timing Specification Parameter Symbol Standard Mode Unit Min. Max fscl 10 400 KHz tHD:STA 4.0 - µs Low period of the SCL clock. tLOW 4.7 - µs High period of the SCL clock. tHIGH 0.75 - µs Set-up time for a repeated START condition. tSU;STA 4.7 - µs Data hold time. For I2C-bus device. tHD;DAT 0 3.45 µs Data set-up time. tSU;DAT 250 - ns Rise time of both SDA and SCL signals. tr 30 N.D. ns ( notel ) Fall time of both SDA and SCL signals. tf 30 N.D. ns ( notel ) tSU;STO 4.0 - µs Bus free time between a STOP and START. tBUF 4.7 - µs Capacitive load for each bus line. Cb 1 15 pF Noise margin at LOW level for each connected device. ( Including hysteresis ) VnL 0.1 VDD - V Noise margin at HIGH level for each connected device. ( including hysteresis ) VnH 0.2 VDD - V SCL clock frequency. Hold time ( repeated ) Start condition. After this period, the first clock pulse is generated. Set-up time for STOP condition. Note : It depends on the “high” period time of SCL. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] V1.1, 10 2008/04/09 PixArt Imaging Inc. PAS6371LT 5. CMOS Image Sensor IC Registers Register Table Bank0 (set address_0xEF=0) Address (Hex) 00 [7:0] 01 [7:0] 02 [3:0] 03 [7:0] 04 [4:0] 05 [7:0] 06 [0] 07 - 0C [7:0] [2:0] 0D [6:4] 0E [2:0] 0F [7:0] 10 [2:0] 11 [7:0] 12 [2:0] 13 - 14 [7:0] 15 [7:0] 16 [2:0] 17 [7:0] 18 [2:0] 19 - 25 [7:0] Register name I2C Slave ID for Write cycle I2C Slave ID for Read cycle PartID[15:8] PartID[7:0] VersionID[3:0] Reserved AE_stage_indoor[4:0] Reserved in_door Reserved AWB_RegionWeight_C[2:0] AWB_RegionWeight_B[2:0] AWB_RegionWeight_A[2:0] AWB_Window_X[7:0] AWB_Window_X[10:8] AWB_Window_Y[7:0] AWB_Window_Y[10:8] Reserved AE_Window_X[7:0] AE_Window_X[10:8] AE_Window_Y[7:0] AE_Window_Y[10:8] Reserved Default 0x80 0x81 0x63 0x71 0x00 xx 0x0c 0x01 0x00 0x00 0x01 0x01 0x01 0x90 0x01 0x2c 0x01 xx 0x90 0x01 0x2c 0x01 xx Description I2C Slave ID for Write cycle I2C Slave ID for Read cycle Part ID Part ID VersionID Reserved Min. AE stage clamp in door Reserved AE In door enable Reserved Weighting of AWB region C Weighting of AWB region B Weighting of AWB region A AWB window width AWB window width AWB window height AWB window height Reserved AE window width AE window width AE window height AE window height Reserved Color Correction Matrix enable (ISP_UpdateFlag=1, update ) 26 [0] CCMb_En 0x01 27 [7:0] CCMb0_0 0x4c Color Correction Matrix coefficient unsigned 8bit, 2.6 format, 0~+4 (ISP_UpdateFlag=1, update ) [7:0] CCMb0_1 0xf4 Color Correction Matrix coefficient signed 1.6 format, -2~0~+2 (ISP_UpdateFlag=1, update ) 7bit, 28 [7:0] CCMb0_2 0x00 Color Correction Matrix coefficient signed 1.6 format, -2~0~+2 (ISP_UpdateFlag=1, update ) 7bit, 29 [7:0] CCMb1_0 0xf2 Color Correction Matrix coefficient signed 1.6 format, -2~0~+2 (ISP_UpdateFlag=1, update ) 7bit, 2A 2B [7:0] CCMb1_1 0x66 Color Correction Matrix coefficient unsigned 8bit, 2.6 format, 0~+4 (ISP_UpdateFlag=1, update ) 2C [7:0] CCMb1_2 0xe8 Color Correction Matrix coefficient signed 1.6 format, -2~0~+2 (ISP_UpdateFlag=1, update ) All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] V1.1, 7bit, 11 2008/04/09 PixArt Imaging Inc. PAS6371LT CMOS Image Sensor IC [7:0] CCMb2_0 0x00 Color Correction Matrix coefficient signed 1.6 format, -2~0~+2 (ISP_UpdateFlag=1, update ) 7bit, 2D [7:0] CCMb2_1 0xe6 Color Correction Matrix coefficient signed 1.6 format, -2~0~+2 (ISP_UpdateFlag=1, update ) 7bit, 2E 2F [7:0] CCMb2_2 0x5a 34 - 4F [7:0] Reserved xx 50 [7:0] CSM1_1 0xa7 51 [7:0] CSM0_0 0xc2 52 [7:0] CSM1_0 0x1c 53 [7:0] CSM2_2 0xd4 54 [7:0] CSM0_2 0x0b 55 [7:0] CSM0_1 0x38 56 57 [7:0] AG_stage_UB [7:0] Reserved 0x3f xx 58 [7:0] ISP_Y0 0x04 59 [7:0] ISP_Y1 0x08 5A [7:0] ISP_Y2 0x10 5B [7:0] ISP_Y3 0x20 5C [7:0] ISP_Y4 0x32 5D [7:0] ISP_Y5 0x44 5E [7:0] ISP_Y6 0x71 5F [7:0] ISP_Y7 0x90 60 [7:0] ISP_Y8 0xae 61 [7:0] ISP_Y9 0xca 62 [0] ISP_Gamma_EnH 0x00 [4] [5] [0] ISP_EnH_update ISP_EnH saturation_En 0x00 0x01 0x01 63 64 Color Correction Matrix coefficient unsigned 8bit, 2.6 format, 0~+4 (ISP_UpdateFlag=1, update ) Reserved Color saturation Matrix coefficient unsigned 8bit, 1.7 format, 0~+2 Color saturation Matrix coefficient unsigned 8bit, 1.7 format, 0~+2 Color saturation Matrix coefficient unsigned 8bit, 1.7 format, 0~+2 Color saturation Matrix coefficient unsigned 8bit, 1.7 format, 0~+2 Color saturation Matrix coefficient unsigned 8bit, 1.7 format, 0~+2 Color saturation Matrix coefficient unsigned 8bit, 1.7 format, 0~+2 AG_stage upper bound at max AE_stage Reserved ISP Gamma Y0 (ISP_UpdateFlag=1, update ) ISP Gamma Y1 (ISP_UpdateFlag=1, update ) ISP Gamma Y2 (ISP_UpdateFlag=1, update ) ISP Gamma Y3 (ISP_UpdateFlag=1, update ) ISP Gamma Y4 (ISP_UpdateFlag=1, update ) ISP Gamma Y5 (ISP_UpdateFlag=1, update ) ISP Gamma Y6 (ISP_UpdateFlag=1, update ) ISP Gamma Y7 (ISP_UpdateFlag=1, update ) ISP Gamma Y8 (ISP_UpdateFlag=1, update ) ISP Gamma Y9 (ISP_UpdateFlag=1, update ) ISP gamma correction enable (ISP_UpdateFlag=1, update ) Flag: ISP enable is sync by vsync ISP enable Color saturation matrix enable All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] V1.1, 12 2008/04/09 PixArt Imaging Inc. PAS6371LT [1] 65 66 67 68 69 - 6A 6B 6C 6D - 6E 6F 70 71 72 73 - 8A 8B 8D - 8E CMOS Image Sensor IC CSM_mode 0x01 [7:0] Reserved xx [0] freq_60 0x01 [4] [7:5] [7:0] [6:0] [7:0] [4:0] [4:0] [7:0] [7:0] [2:0] [6:4] [7:0] [0] [4] [7:5] [7:0] [0] [1] [2] [3] [7:0] AE_EnH Reserved SysClk_freq[7:0] SysClk_freq[14:8] Reserved AE_minStage[4:0] AE_maxStage[4:0] Reserved Ytar8bit AE_wait_state AWB_wait_state Reserved AWB_EnH AWB_Gain_rst Reserved Reserved AE_DeOsc_En AE_DeOsc_Timer_En AWB_DeOsc_En AWB_DeOsc_Timer_En Reserved 0x01 xx 0x97 0x31 xx 0x01 0x1c xx 0x64 0x00 0x00 xx 0x01 0x00 xx xx 0x00 0x00 0x00 0x00 xx 8F [7:0] ImgEffect_c0 0x40 90 [7:0] ImgEffect_c1 0x40 91 [7:0] ImgEffect_c2 0x10 92 [7:0] ImgEffect_c3 0x80 [3:0] ImgEffectMode 0x00 [5:4] ImgEffectFilter 0x00 [0] [7:0] [4] [5] [0] [7:1] 0x00 xx 0x00 0x00 0x01 xx 93 94 95 - 96 97 98 ISP_ImgEffect_En Reserved Shading_EnH Shading_On ShadingAutoOff Reserved 1:HW Count CSMatrix(R2_x8a) 0:original Reserved Set de-flicker frequency 0/1: 50/60Hz AE enable Reserved Input_frequency / 2048 Input_frequency / 2048 Reserved Minimum AE stage Maximum AE stage (AE_maxStage<=28) Reserved 0~255, Target luminance of AE Frame wait-state for AE adjust Frame wait-state for AWB adjust Reserved Auto-white balance enable AWB gain gain reset Reserved Reserved AE DeOscillate enable AE DeOscillate escape timer enable AWB DeOscillate enable AWB DeOscillate escape timer enable Reserved Image Effect parameter 0 (ISP_UpdateFlag=1, update ) Image Effect parameter 1 (ISP_UpdateFlag=1, update ) Image Effect parameter 2 (ISP_UpdateFlag=1, update ) Image Effect parameter 3 (ISP_UpdateFlag=1, update ) Image Effect mode 1: monochrome; 2: negative 3: Sepia; 4: Emboss; 5: Sketch 6: Black Board; 7: White Board 8: Solarize; 9: Color range R 10: Color range G; 11: Color range B; 12: Contrast (ISP_UpdateFlag=1, update ) Image Effect emboss filter type (ISP_UpdateFlag=1, update ) (ISP_UpdateFlag=1, update ) Reserved Lens shading enable Shading on/off status 1:turn off shading Reserved All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] V1.1, 13 2008/04/09 PixArt Imaging Inc. PAS6371LT 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC B9 BD - BE BF [6:0] [6:0] [6:0] [6:0] [6:0] [6:0] [6:0] [6:0] [6:0] [6:0] [6:0] [6:0] [6:0] [6:0] [6:0] [6:0] [7:0] [1:0] [7:0] [1:0] [2:0] [7:0] [7:0] [5:0] C0 [6] [7] C1 - D4 [7:0] CMOS Image Sensor IC BYcoef_D BXcoef_R BYcoef_U BXcoef_L GbYcoef_D GbXcoef_R GbYcoef_U GbXcoef_L GrYcoef_D GrXcoef_R GrYcoef_U GrXcoef_L RYcoef_D RXcoef_R RYcoef_U RXcoef_L brightestX[7:0] brightestX[9:8] brightestY[7:0] brightestY[9:8] LensShfBit[2:0] Reserved Ycap8bit Reserved AWB_EnH_vs AE_EnH_vs Reserved 0x1f 0x1f 0x1f 0x1f 0x1f 0x1f 0x1f 0x1f 0x1f 0x1f 0x1f 0x1f 0x1f 0x1f 0x1f 0x1f 0x40 0x01 0xf0 0x00 0x00 xx 0x00 xx 0x00 0x00 xx D7 [7:0] ISP_HSize[7:0] 0xe0 D8 [2:0] ISP_HSize[10:8] 0x01 D9 [7:0] ISP_VSize[7:0] 0x68 DA [2:0] ISP_VSize[10:8] 0x01 DB – E6 [7:0] [0] ED [7:1] EE [7:0] Reserved ISP_Update Reserved Reserved xx xx xx Y coefficient of color B X coefficient of color B Y coefficient of color B X coefficient of color B Y coefficient of color Gb X coefficient of color Gb Y coefficient of color Gb X coefficient of color Gb Y coefficient of color Gr X coefficient of color Gr Y coefficient of color Gr X coefficient of color Gr Y coefficient of color R X coefficient of color R Y coefficient of color R X coefficient of color R brightest X brightest X brightest Y brightest Y Lens Shift Bit select Reserved Y sum report Reserved AWB enable sync by vsync AE enable sync by vysnc Reserved ISP output Horizontal size (before skip function) ISP output Horizontal size (before skip function) ISP output Vertical size (before skip function) ISP output Vertical size (before skip function) Reserved ISP_UpdateFlag Reserved Reserved All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] V1.1, 14 2008/04/09 PixArt Imaging Inc. PAS6371LT CMOS Image Sensor IC Bank2 (set address_0xEF=2) Address (Hex) 00 [0] 01 - 03 [7:0] 04 [7:0] 05 [7:0] 06 [7:0] 07 [7:0] 08 [7:0] 09 [7:0] 0A [0] 0E - 13 [7:0] 17 [0] 18 [7:0] 19 [7:0] 1A [7:0] 1B [7:0] 1C [7:0] 1D [7:0] 1E [7:0] 1F [7:0] 20 [7:0] 21 [7:0] 22 [3] 23 - 29 [7:0] [6:0] 2A [7] 2B - 69 [7:0] [2:0] 9B [4] 9C [7:0] [2:0] 9D [4] 9E [7:0] 9F [2:0] A0 [7:0] A1 [2:0] A2 [7:0] A3 - B3 [7:0] B4 [2:0] B5 [7:0] B6 [2:0] B7 [7:0] B8 [2:0] B9 [7:0] BA [2:0] BB [7:0] C0 [0] [1] Register name ISP2_Update Reserved ImgEffect_R_Gain[7:0] ImgEffect_G_Gain[7:0] ImgEffect_B_Gain[7:0] ImgEffect_R_offset[7:0] ImgEffect_G_offset[7:0] ImgEffect_B_offset[7:0] ISP_ImgEffect_1_En Reserved Curve_EnH Curve_Y0[7:0] Curve_Y1[7:0] Curve_Y2[7:0] Curve_Y3[7:0] Curve_Y4[7:0] Curve_Y5[7:0] Curve_Y6[7:0] Curve_Y7[7:0] Curve_Y8[7:0] Curve_Y9[7:0] Defect_EnH Reserved Reserved ISP_Edge_En0 Reserved ISP_WOI_HSize[10:8] ISP_WOI_H_En ISP_WOI_HSize[7:0] ISP_WOI_VSize[10:8] ISP_WOI_V_En ISP_WOI_VSize[7:0] ISP_WOI_HOffset[10:8] ISP_WOI_HOffset[7:0] ISP_WOI_VOffset[10:8] ISP_WOI_VOffset[7:0] Reserved R_ISP_WOIb_HSize[10:8] R_ISP_WOIb_HSize[7:0] R_ISP_WOIb_VSize[10:8] R_ISP_WOIb_VSize[7:0] R_ISP_WOIb_HOffset[10:8] R_ISP_WOIb_HOffset[7:0] R_ISP_WOIb_VOffset[10:8] R_ISP_WOIb_VOffset[7:0] UV_Swap YC_Swap Default 0x00 xx 0x00 0x00 0x00 0x00 0x00 0x00 0x00 xx 0x01 0x1a 0x34 0x49 0x5b 0x6d 0x7d 0x9a 0xb6 0xcf 0xe8 0x00 xx xx 0x01 xx 0x02 0x01 0x80 0x01 0x01 0xE0 0x00 0x00 0x00 0x00 xx 0x02 0x80 0x01 0xE0 0x00 0x00 0x00 0x00 0x00 0x00 Description ISP2_UpdateFlag Reserved (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) Reserved ISP tone curve Enable ISP tone curve Y0 ISP tone curve Y1 ISP tone curve Y2 ISP tone curve Y3 ISP tone curve Y4 ISP tone curve Y5 ISP tone curve Y6 ISP tone curve Y7 ISP tone curve Y8 ISP tone curve Y9 R_Defect_EnH Reserved Reserved ISP edge enhancement enable Reserved (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) Reserved WOIb_HSize (ISP2_UpdateFlag=1, update ) WOIb_HSize (ISP2_UpdateFlag=1, update ) WOIb_VSize (ISP2_UpdateFlag=1, update ) WOIb_VSize (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) U V Swap Y C Swap All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] V1.1, 15 2008/04/09 PixArt Imaging Inc. PAS6371LT CMOS Image Sensor IC [3:2] RGB565_mode[1:0] 0x00 [4] RGB565_En 0x00 [5] RGB555_En 0x00 [6] RGB444_En 0x00 [0] Vsync_INV [1] Hsync_INV E3 - EE [7:0] Reserved C1 0x00 0x00 xx RGB565_mode RGB565 Enable (ISP2_UpdateFlag=1, update ) RGB555 Enable (ISP2_UpdateFlag=1, update ) RGB444 Enable (ISP2_UpdateFlag=1, update ) Vsync inverse Hsync inverse Reserved All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] V1.1, 16 2008/04/09 L1 1 2 0.1u C8 DGND 3.3uH 2 VIN U2 DGND VOUT 1.8V Regulator 3 All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. V1.1, DGND SDA E1 D2 D1 C1 C2 B1 VSY NC HSY NC B2 A1 RSTN CSB All capacitors must be close to the sensor as possible AGND, analog ground DGND, digital ground VDDD, digital core power, 1.8V VDDMD, I/O power, 1.8V ~ 3.3V 1u C9 DGND 1u C7 AGND 1u C4 VSSD SDA VDDD VDDMD HSY NC VSY NC RSTN CSB U1 1u PAS6371LT 1u C5 PX8 PX3 PX9 PX5 VSSD PX6 PX7 VSSA VREF4 VSSAY PX4 PX7 PX1 PX6 E5 E4 F5 Date: Size A4 Title PX3 D4 D5 PX5 C3 0.1u C2 10u C1 C4 C5 B4 B5 AGND R3 10k R2 10k VDDMD Tuesday , April 08, 2008 Document Number By PixArt Imaging Inc. PAS6371LT ref erence circuit SDA SCL DGND AGND Sheet 1 of 1 Rev V1.1 PAS6371LT VDDMA, analog power, 2.5V ~ 3.0V Sensor pwdn pin, "CSB", high active (connect to DGND if un-used) Sensor reset pin, "RSTN", low active (connect pull-high resistor if un-used) Note: USB +5V DGND 10u_N.M. + C6 VDDMD 10u_N.M. + C3 C5 F1 SCL SCL SYSCLK E2 SYSCLK PXCLK F2 PXCLK GND A2 VDDMA A3 VREF1 AGND VREF2 A4 PX1 E3 1 VREF3 A5 PX0 F3 PX4 F4 PX2 PX2 PixArt Imaging Inc. E-mail: [email protected] D3 6. PX0 VDDMA PixArt Imaging Inc. CMOS Image Sensor IC Reference Circuit Schematic 17 2008/04/09 PixArt Imaging Inc. PAS6371LT 7. CMOS Image Sensor IC Package Information *Note: The formation of image is the result formed by package Top view(A1 : left-up) and general Lens(invert and mirror the image). All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] V1.1, 18 2008/04/09 PixArt Imaging Inc. PAS6371LT CMOS Image Sensor IC Recommended Layout PCB All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] V1.1, 19 2008/04/09 PixArt Imaging Inc. PAS6371LT CMOS Image Sensor IC Recommended Condition For Infrared Reflow Carefully observe the mounting conditions, recommended temperature profile when Mounting infrared reflows is show in the figure below. After mounting on the mother board, it must be dispense epoxy in side of the CSP package. ☉ Reflow Profile Recommend Reflow Profile Melting area 250 Temp. 200 150 Pre-heat 100 50 0 0 20 40 60 80 100 120 140 160 180 200 220 Time ( Sec ) Recommend Pb-free solder paste vender & type : Programming rate 1.5~2.5 oC/sec Pre-heat 170~200oC 90 +/- 30 sec ☉ Dispense Epoxy 1. Almit LFM-48W TM-HP 2. Senju M705-GRN360-K Melting area >220oC 30~50sec with peak temperature 230~245oC Epoxy All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] V1.1, 20 2008/04/09