PAS302BCA-32 CMOS Image Sensor IC PAS302BCA-32 CMOS VGA DIGITAL IMAGE SENSOR General Description The PAS302BCA-32 is a highly integrated CMOS active-pixel image sensor that has a VGA resolution of 644H x 484V. The PAS302BCA-32 outputs 10-bit RGB raw data through a parallel data bus and is available in 32-pin LCC package. The PAS302BCA-32 can be programmed to set the exposure time for different luminance condition via I 2 CTM serial control bus. By programming the internal register sets, it can perform on-chip frame rate adjustment, offset correction DAC and programmable gain control. Key Specification Features VGA(644 x 484 pixels) resolution, ~1/4” Lens Supply Voltage Bayer-RGB color filter array Resolution Output format: 10-bit parallel RGB raw data On-chip 10-bit pipelined A/D converter On-chip programmable gain amplifier 4-bit color gain amplifier (x1~x2) 4-bit global gain amplifier (x1~x2) Array diagonal Pixel Size Chief Ray Angle 2.5V ~ 3.3V 644(H) x 484(V) 4.5mm (~1/4”Optic) 5.6µmx5.6µm 12∘ ~ 14∘ ~30 fps Digital gain stage Frame rate Continuous variable frame time(1/2sec~1/30sec) System clock Up to 48 MHz Continuous variable exposure time Pixel clock Up to 12MHz Sensitivity 1.88 V/Lux-Sec Color filter RGB Bayer Pattern IC 2 TM Interface Support flash light timing Single 2.5V / 3.3V supply voltage < 15mA(~30 fps) power dissipation 2µA power dissipation when power down Exposure Time Scan Mode mode Window-Of-Interest (WOI) ~ Frame time to Line time Progressive S/N Ratio > 45 dB Package 32-pin LCC Sub-sampling Defect compensation Note1: Only two decoupling capacitors needed Note2: Good sensitivity compared to competitors Version 2.3, 13 Sep. 2004 E-mail: [email protected] PixArt Imaging Inc. 1 PAS302BCA-32 CMOS Image Sensor IC PX9 SYSCLK RESET PXCLK VDDQ VSYNC 12 VSSD PX7 1. Pin Assignment 11 10 9 8 7 6 5 VHRST 13 4 HSYC VLRST 14 3 P_OUTN PX8 15 2 P_OUTP 1 VRT 32 VDDMA VREF VDDD 16 PX6 17 PAS302BCA-32 -- Top View -- 21 22 23 24 25 26 27 28 VRB PWDN VSSA 29 VCM 20 SDA VDDA PX0 SCL 30 PX2 19 PX3 18 PX1 PX4 PX5 31 Figure 1.1. PAS302BCA-32 pin assignment Pin No. Name Type 1 2 3 4 5 6 7 8 VRT P_OUTP P_OUTN HSYNC VSYNC VDDQ PXCLK RESET BYPASS BYPASS BYPASS OUT OUT PWR OUT 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SYSCLK PX9 VSSD PX7 VHRST VLRST PX8 VDDD PX6 PX5 PX1 PX0 PX4 PX3 PX2 Description Voltage reference top Analog test output P Analog test output N Horizontal synchronization signal. Vertical synchronization signal. Digital VDD, 2.5V to 3.3V. Pixel clock output. Resets all registers to their default values (chip reset IN when high) IN Master clock input. OUT Digital data out. GND Digital ground. OUT Digital data out. BYPASS Sensor reset power BYPASS Sensor reset power OUT Digital data out. PWR Digital VDD, OUT Digital data out. OUT Digital data out. OUT Digital data out. OUT Digital data out. OUT Digital data out. OUT Digital data out. OUT Digital data out. Version 2.3, 13 Sep. 2004 E-mail: [email protected] PixArt Imaging Inc. 2 PAS302BCA-32 24 25 26 27 28 29 30 31 32 SCL SDA VCM VSSA VRB PWDN VDDA VREF VDDMA CMOS Image Sensor IC IN I/O BYPASS GND BYPASS IN PWR IN PWR Version 2.3, 13 Sep. 2004 E-mail: [email protected] I 2 CTM clock. I 2 CTM data. Internal pull high resister is 10KΩ. Voltage common mode Analog ground. Voltage reference bottom Power Down (chip power down when high) Analog VDD, Internal voltage reference. Analog VDD, 2.5V to 3.3V. PixArt Imaging Inc. 3 PAS302BCA-32 CMOS Image Sensor IC 2. Block Diagram Color Gain G F G C G G Row Decoder Sensor Array 644x484 Front Gain 4-Bit x1 ~ x2 4-Bit x1 ~ x2 3-Bit x2 ~ x4 DAC1 Global Gain 10-Bit A/D DAC2 CDS Column Decoder Timing Generator & Control Logic Companding Digital Gain Stage Defect Compensation PX(9 : 2) PXCLK HSYNC VSYNC SYSCLK SDA SCL Figure 2.1. PAS302BCA-32 sensor block diagram The PAS302BCA-32 is a 1/4” CMOS imaging sensor with 644x488 physical pixels. The active region of sensor array is 644x484 as shown in Fig. 2.1. The sensor array is covered with Bayer pattern color filters and micro-lens. The first pixel location <0,0> is programmable in 2 direction (X and Y) and the default value is at the left-down side of sensor array. After a programmable exposure time, the signals of image are sampled first with CDS (Correlated Double Sampling) block to improve S/N ratio and reduce fixed pattern noise. Three analog gain stages are implemented before signals are transferred to 10-Bit ADC. The front gain stage (FG) can be programmed to fit the saturation level of sensor to the full-range input of ADC. The programmable color gain stage (CG) is used to balance the luminance response difference between B, G and R color. The global gain stage (GG) is programmed to adapt the gain to the image luminance. After three gain stages, the signals will be digitized by the on-chip 10-Bit ADC. After the image data have been digitized, further adjustment to the signal can be applied before the data is output to next stage. Version 2.3, 13 Sep. 2004 E-mail: [email protected] PixArt Imaging Inc. 4 PAS302BCA-32 CMOS Image Sensor IC 3. Function Description 3.1. Defect Compensation The Defect Compensation block can detect the possible defect pixel and replace it with average output of like-colored pixels from near side of defect pixel. There is no limitation capability of defect pixel number. This function can be programmed to enable/disable by user. 3.2. Companding Curves The companding function which means compressing and expanding is used to simulate the gamma curve and do non-linear transformation before the data is output. There are 4 curves selected by setting Register Compand_Sel as shown in Fig. 3.1. This function can be programmed to enable/disable by user. O/P ( 10-Bit) 11,1111,1111 3 2 00,0xxx,xxxx 00,1xxx,xxxx 1 010 0 011 without companding 10,xxxx,xxxx 11,xxxx,xxxx I/P ( 10-Bit) Figure 3.1 Companding curves program by Compand_EnH and Compand_Sel. 3.3. Power Down Mode The PAS302BCA-32 can be powered down by setting register “Sw_PwrDn” = 1 or by enable Pwdn pin. The register value will sustain in the power down mode. PAS302BCA-32 supports 2 power down modes: z Software power down：Set register “Sw_PwrDn” = 1 to power down all the internal block except I 2 CTM . z Hardware power down：Pull Pwdn pin to high to power down the chip. The chip will go into standby mode. 3.4. Reset Mode The PAS302BCA-32 can be reseted by setting register “Sw_Reset” = 1 or by enable Reset pin. PAS302BCA-32 supports 2 reset modes: z Software reset：Set register “Sw_Reset” = 1 to reset all the I 2 CTM registers. z Hardware reset：Pull Reset pin to high to reset the full chip. Version 2.3, 13 Sep. 2004 E-mail: [email protected] PixArt Imaging Inc. 5 PAS302BCA-32 CMOS Image Sensor IC 4. Output Format 4.1. Physical Sensor Array 644 - Column Dark Line Dark Line Dark Line Dark Line 488 - Row G R G R G R G R B G B G B G B G G R G R G R G R G R G R G R G R B G B G B G B G G R G R G R G R 644 X 484 Active Pixels B G B G B G B G G R G R G R G R B G B G B G B G B G B G B G B G G R G R G R G R B G B G B G B G Figure 4.1 Physical Sensor Array Version 2.3, 13 Sep. 2004 E-mail: [email protected] PixArt Imaging Inc. 6 PAS302BCA-32 CMOS Image Sensor IC 4.2. Output Timing VGA mode ( 644 x 488 ) pixel readout: H_Start[9:0] = 0, V_Start[8:0] = 0, Nov_By2[7:0] = 87, H_Size[9:0] = 643, V_Size[8:0]= 487, NovSize = Nov_By2 *2 +1 = 175 Pixclks( default ) Line-time = NovSize + 644 = 819 Pixclks( default ) Hsync G R G R B G B G NovSize B G B G G R G R Valid pixel = 644 Pixclks Pixclk Figure 4.2 Inter-line timing ( default ) If Mask_Dark[3] = 0, Frame Time = LPF + 1 = 488 Line ( default ) Vsync Hsync Dark Dark Dark Dark Dark Line = 4 Line Dark Valid Line = 484 Line Figure 4.3 Inter-frame timing (LPF default setting = 487, Mask_Dark[3] =0) If Mask_Dark[3] = 1, Frame Time = LPF + 1 = 488 Line ( default ) Vsync Hsync Dark Line = 4 Line Valid Line = 484 Line Figure 4.4 Inter-frame timing (LPF default setting = 487, Mask_Dark[3] =1) 4.3. Hardware Windowing Users are allowed to define window size as well as window location in PAS302BCA-32, Window size can range from 20x14 to 644x484. The location of window can be anywhere in the sensor array. Window location and size is defined by register H_Start, V_Start, H_Size and V_Size; the H_Start defines the starting column while V_Start defines the starting row of the window; the H_Size define the column width of the window and V_Start define the row depth of the window. 4.4. Sub-sampling PAS302BCA-32 can be programmed to output image in QVGA and QQVGA size by setting Registers Skip_Digital or Skip_Analog. In QVGA sub-sampling mode, both vertical and horizontal pixels are sub-sampling at 1/2, while in QQVGA sub-sampling mode, both vertical and horizontal pixels are sub-sampling at 1/4. The maximum sub-sampling rate is 1/16. Version 2.3, 13 Sep. 2004 E-mail: [email protected] PixArt Imaging Inc. 7 PAS302BCA-32 CMOS Image Sensor IC 5. I 2 CTM Bus PAS302BCA-32 supports I 2 CTM bus transfer protocol and acts as slave device. The 7 bits unique slave address is 1000000 and the bus supports receiving / transmitting speed up to 400kHz. 5.1. I 2 CTM Bus Overview There are only two lines SDA (serial data) and SCL (serial clock) carry information between the devices which are connected by I 2 CTM bus. Normally both SDA and SCL lines are open collector structure and pulled high by external pull-up resistors. Only the master can initiate a transfer (start), generate clock signals, and terminate a transfer (stop). Start Condition : A high to low transition of the SDA line while SCL is high defines a start condition. Stop Condition : A low to high transition of the SDA line while SCL is high defines a stop condition. Valid Data: The data on the SDA line must be stable during the high period of the SCL clock. Within each byte, MSB is always transferred first. Read/write control bit is the LSB of the first byte. Both the master and slave can transmit and receive data from the bus. Acknowledge : The receiving device should pull down the SDA line during high period of the SCL clock line when a byte was transferred completely by transmitter. When in the case of that a master received data from a slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master read cycle. SDA SCL S P Start Condition Stop Condition Figure 5-1: Start and Stop Conditions SDA DATA STABLE DATA CHANGE ALLOWED SCL Figure 5-2: Valid Data Version 2.3, 13 Sep. 2004 E-mail: [email protected] PixArt Imaging Inc. 8 PAS302BCA-32 CMOS Image Sensor IC 5.2. Data Transfer Format 5.2.1. Master transmits data to slave (write cycle) S : Start A : Acknowledge by slave P : Stop RW : The LSB of 1st byte to decide whether current cycle is read or write cycle. If RW=1 that means read cycle, if RW=0 that means write cycle.. SUBADDRESS : The address values of PAS302BCA-32 internal control registers (Please refer to PAS302BCA-32 register description) 1ST BYTE S SLAVE ID (7 BIT) MSB 2ND BYTE RW A n BYTEs + A SUBADDRESS (8 BIT) A DATA A DATA A P LSB=0 During the write cycle, the master generates start condition and then places the 1st byte data that combined slave address (7 bits) with a read/write control bit on SDA line. After slave(PAS302BCA-32) issues acknowledgment, the master places 2nd byte (sub-address) data on SDA line. And then following the slave’s( PAS302BCA-32) acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS302BCA-32 control register (address was assigned by 2nd byte). After PAS302BCA-32 issue acknowledgment, the master can generate a stop condition to end this write cycle. In the condition of multi-byte write, the PAS302BCA-32 sub-address will be increased automatically after each DATA byte has been transferred. The Data and A cycles are repeated until last byte write. Every control registers value inside PAS302BCA-32 can be programming via this way. (Please refer to Figure 5.3.) 5.2.2. Slave transmits data to master (read cycle) The sub-address was assigned by previous write cycle The sub-address is automatically increased after each byte read Am : Acknowledged by master Note there is no acknowledgment from master after last byte read 1ST BYTE S SLAVE ADDRESS (7 BITS) 2ND BYTE RW A DATA (8 BIT) n BYTE Am DATA Am DATA 1 P NO ACK IN LAST BYTE During read cycle, the master generates start condition and then place the 1st byte data that combine slave address (7 bits) with a read/write control bit to SDA line. After slave issue acknowledgment, 8 bits DATA was placed on SDA line by PAS302BCA-32. The 8 bit data was read from PAS302BCA-32 internal control register that address was assigned by previous write cycle. Following the master acknowledgment, the PAS302BCA-32 place the next 8 bits data (address is increased automatically) on SDA line and then transfer to master serially. The DATA and Am cycles are repeated until the last byte read. After last byte read, Am is no longer Version 2.3, 13 Sep. 2004 E-mail: [email protected] PixArt Imaging Inc. 9 PAS302BCA-32 CMOS Image Sensor IC generated by master but instead of keeping SDA line as high. The slave (PAS302BCA-32) must releases SDA line back to master to generate STOP condition. (Please refer to Figure 5.3.) SDA SCL 1-7 8 9 1-7 8 9 1-7 8 9 P S Start Condition Address ACK from Receiver R/W ACK from Receiver Data Stop ACK from Condition Receiver Data Figure 5.3 Data Transfer Format 2 5.3. I C TM Bus Timing SDA tf tHD;STA tf tLOW tr tBUF tr tSP tSU;DAT SCL S tHD;STA tHD;DAT tSU;STA tHIGH tSU;STO Sr P S Figure 5.4 I 2 CTM Bus Timing 5.4. I 2 CTM Bus Timing Specification STANDARD-MODE PARAMETER SYMBOL SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated. Low period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time. For I 2 CTM bus device Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START Capacitive load for each bus line Noise margin at LOW level for each connected device (including hysteresis) Version 2.3, 13 Sep. 2004 E-mail: [email protected] fscl tHD:STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb VnL PixArt Imaging Inc. UNIT MIN. 10 MAX. 400 kHz 4.0 - µs 4.7 - µs 0.75 - µs 4.7 - µs 0 3.45 µs 250 - ns 30 N.D.(Note) ns 30 N.D. (Note) ns 4.0 - µs 4.7 - µs 1 15 pF 0.1 VDD - V 10 PAS302BCA-32 CMOS Image Sensor IC Noise margin at HIGH level for each VnH connected device (including hysteresis) Note: It depends on the "high" period time of SCL. Version 2.3, 13 Sep. 2004 E-mail: [email protected] PixArt Imaging Inc. 0.2 VDD - V 11 PAS302BCA-32 CMOS Image Sensor IC 6. Electrical Characteristics Absolute Maximum Ratings -40℃ ~ +125℃ Ambient Storage Temperature VDDD 3V Supply Voltages VDDA 3V ( with respect to Ground ) VDDMA 4V VDDQ 4V -0.3V to VDDQ + 1V All Input / Output Voltages ( with respect to Ground ) Lead Temperature, Surface-mount process +230℃ ESD Rating, Human Body model 2000V DC Electrical Characteristics ( VDD = 2.5V ± 4% , Ta =0℃ ~ 70℃ ) Symbol Parameter Min. Typ. Max. Unit Type :PWR VDDA DC Supply voltage – Analog 2.4 2.5 2.6 V VDDD DC Supply voltage – Digital 2.4 2.5 2.6 V VDDQ DC Supply voltage – I/O 2.4 - 3.3 V VDDMA DC Supply voltage – Analog 2.4 - 3.3 V IDD Operating Current IPWDN Power Down current Type :IN & I/O Reset and SYSCLK VIH Input voltage HIGH VIL Input voltage LOW CIN Input capacitor 15 mA 2 µA 0.7 x VDDQ V 0.3 x VDDQ 10 V pF Type : OUT & I/O for PXD0:7, PXCK, H/VSYNC & SDA, load 10pf, 1.2kΩ,2.5volts VOH Output voltage HIGH VOL Output voltage LOW 0.9 x VDDQ AC Operating Condition Symbol Parameter Min. V Typ. 0.1 x VDDQ V Max. Unit SYSCLK Master clock frequency 48 MHz PXCK Pixel clock output frequency 12 MHz Sensor Characteristics Parameter Typ. Unit Sensitivity 1.88 V/ Lux-Sec Signal to Noise Ratio > 45 dB dB Dynamic Range Temperature Operation 60 -10 ~ 70 Range Stable Image 0 ~ 50 Version 2.3, 13 Sep. 2004 E-mail: [email protected] PixArt Imaging Inc. Note ℃ 12 17 18 19 20 PX5 PX1 PX0 16 15 PX6 PX8 PX0 PX1 PX5 PX6 VDDD PX8 VLRST VDDQ PAS302BCA 21 PX4 14 VSSD 22 PX3 VHRST PX9 PX2 13 PX7 12 PX7 SYSCLK 23 PX2 24 SCL SCL PX4 PXCLK VCM 11 VSSD RESET SDA 25 SDA PX3 10 PX9 9 SYSCLK 8 RESET 7 PXCLK 6 27 PixArt Imaging Inc. 26 VDDQ VSSA VSYNC 5 VSYNC VRB E-mail: [email protected] 28 Version 2.3, 13 Sep. 2004 VSSA 29 PWDN VREF 31 30 VDDMA HSY NC 32 1 2 3 4 PAS302 PWDN VDDA VREF VDDMA VRT P_OUTP P_OUTN HSY NC U4 C1 0.1U C2 0.1U VSY NC SY SCLK SDA VDDMA PWDN PX2 PX8 PX6 PX4 2 4 6 8 10 12 14 16 18 20 22 RESET PXCLK HSY NC SCL PX9 PX7 PX5 VDDQ PX3 Notes: VDDQ is 2.5V to 3.3V sensor digital power. VDDMA is 2.5V to 3.3V sensor analog power. C1 should close to sensor VDDA and AGND. C2 should close to sensor VREF and AGND. SENSOR BOARD INTERFACE 1 3 5 7 9 11 13 15 17 19 21 JP1 PAS302BCA-32 CMOS Image Sensor IC 7. Reference Circuit Schematic 13 PAS302BCA-32 CMOS Image Sensor IC 8. Package Specification Unit:mm Version 2.3, 13 Sep. 2004 E-mail: [email protected] PixArt Imaging Inc. 14 PAS302BCA-32 CMOS Image Sensor IC 9. Recommended Lens and Holder Version 2.3, 13 Sep. 2004 E-mail: [email protected] PixArt Imaging Inc. 15