Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 DESCRIPTION PT6332 is a VFD driver IC driven on 1/2 to 1/3 duty factor. It can drive up to 168 segments. 56 segment output lines, 3 grid output lines, 4 general purpose output lines, control circuit, key scan circuit are all incorporated into a single chip to build a highly reliable peripheral device for a single chip micro controller. Pin configuration and application circuit are optimized for easy PCB layout and cost saving advantages. FEATURES • CMOS technology • Up to 168 segment outputs (3 Grid & 56 Segment drivers) or Up to 114 segment outputs (2 Grid & 57 Segment drivers) • Up to 25 key inputs • Up to 4 general purpose outputs • Sleep and dimmer mode • One-Pin oscillation circuit • Hard ware duty cycle selection 1/2 or 1/3 • Available in 80 pins, LQFP APPLICATION • Electronic equipment with VFD display PT6332 V1.0 -1- February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 G ri d D ri ve r SG2 SG1 S G 56/P 1 S G 55/P 2 S G 54/P 3 S G 53/P 4 G R1 G R2 G R3 /SG 57 BLOCK DIAGRAM S egm ent Dr iv er 57 /B LK M PX VFL 17 1 V DD La tch V SS 1 D im me r Tim in g G e ner ato r V SS 2 Con tro l R egi ste r 57 16 S hift Reg is ter Tim in g G e ner ato r K ey B uffer Di vi der PT6332 V1.0 -2- K I5 K I4 K I3 K I2 K I1 K S5 K S4 K S3 K S2 K S1 K ey S ca n CE CL DI DO Clo ck G e ner ato r DT O S CI C om ma nd Inte rfa ce February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 INPUT/OUTPUT PINS EQUIVALENT CIRCUIT • DI, CE, CL, /BLK, DT V DD • OSCI • DO • KSn • GRn, SGn • KIn V DD V DD V DD V DD V DD V FL PT6332 V1.0 -3- February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 SG13 SG14 SG15 SG16 SG17 SG18 SG19 SG20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PIN CONFIGURATION VSS1 61 40 SG21 KS1 62 39 SG22 KS2 63 38 SG23 KS3 64 37 SG24 KS4 65 36 SG25 KS5 66 35 SG26 KI1 67 34 SG27 KI2 68 33 SG28 KI3 69 32 SG29 KI4 70 31 SG30 KI5 71 30 SG31 DT 72 29 SG32 /BLK 73 28 SG33 DO 74 27 SG34 CE 75 26 SG35 CL 76 25 SG36 DI 77 24 SG37 VDD 78 23 SG38 OSCI 79 22 SG39 VSS2 80 21 SG40 PT6332 V1.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 G R1 G R2 GR3/SG 57 VFL SG 56/P1 SG 55/P2 SG 54/P3 SG 53/P4 SG 52 SG 51 SG 50 SG 49 SG 48 SG 47 SG 46 SG 45 SG 44 SG 43 SG 42 SG 41 P T6332 -4- February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 PIN DESCRIPTION Pin Name GR1 ~ GR2 GR3/SG57 VFL SG56/P1 ~ SG53/P4 SG52 ~ SG1 VSS1 KS1 ~ KS5 KI1 ~ KI5 I/O O O O O O I DT I /BLK I DO CE CL DI VDD OSCI VSS2 O I I I I - PT6332 V1.0 Description Grid driver output pin Grid/Segment driver output pin Driver power supply Segment driver/General purpose output pin Segment output pin Ground pin Key scan output pin Key scan input pin Duty cycle selection pin (DT=0, 1/3 duty) (DT=1, 1/2 duty) Blank input pin (Reset pin) When this pin is set to “Low” level, the display is turned off and key scan is disabled. All key data are reset to low. When this pin is set to “High”, the display is turned on and the key scan is enabled. (see note) Data output pin (open ~ drain) Chip enable input pin Clock input pin Data input pin Power supply Oscillation input pin Ground pin -5- Pin No. 1~2 3 4 5~8 9~ 60 61 62 ~ 66 67 ~ 71 72 73 74 75 76 77 78 79 80 February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 FUNCTION DESCRIPTION SERIAL DATA INPUT 1/3 DUTY When stopped with CL at the low level. CE CL DI 0 1 1 1 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 D1 D2 D 56 0 C0 0 0 0 0 P1 P2 P3 P4 Di sp l a y D at a A d d re ss S0 S1 D M0 D M1 D M2 D M3 D M4 D M5 D M6 D M7 D M8 D M9 0 Co n tr o l Da ta 0 DD CE 0 1 1 1 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 D 57 D 58 D 11 2 0 0 0 0 0 0 0 0 0 0 C1 C2 0 0 0 0 0 0 0 0 0 0 0 Di sp l a y D at a A d d re ss 0 1 1 1 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 A d d re ss D 11 3 D 11 4 D 168 1 DD 0 0 0 0 0 0 0 Di sp l a y D at a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 DD Figure 1 Note: DD=Direction Data PT6332 V1.0 -6- February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 When stopped with CL at the high level. CE CL DI 0 1 1 1 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 D1 D 56 D2 0 C0 0 0 0 0 P1 P2 P3 P4 Di sp l a y D at a A d d re ss S0 S1 D M0 D M1 D M2 D M3 D M4 D M5 D M6 D M7 D M8 D M9 0 Co n tr o l Da ta 0 DD CE 0 1 1 1 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 D 58 D 11 2 0 0 0 0 0 0 0 0 0 0 C1 C2 0 0 0 0 0 0 0 0 0 0 0 Di sp l a y D at a A d d re ss 0 1 1 1 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 A d d re s s D 57 D 11 3 D 11 4 D 168 1 DD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Di sp l a y D at a 0 1 0 DD Figure 2 Notes: 1. DD 2. Address 3. D1 to D56 4. D57 to D112 5. D113 to D168 6. D53 to D56 7. C0 to C2 PT6332 V1.0 : Direction Data : Applications must send the value (8EH) as shown in figure 1 & 2 : Segment display data for the GR1 digit output pin (when P1 ~ P4=0) Dn (n=1 to 56)=1: Segment on Dn (n=1 to 56)=0: Segment off : Segment display data for the GR2 digit output pin Dn (n=57 to 112)=1: Segment on Dn (n=57 to 112)=0: Segment off : Segment display data for the GR3 digit output pin Dn (n=113 to 168)=1: Segment on Dn (n=113 to 168)=0: Segment off : General purpose output pin (when P1~P4=1) Dn (n=53 to 56)=1: General purpose on (High level) Dn (n=53 to 56)=0: General purpose off (Low level) : Sleep Mode Current Setup Cn (n=0 to 2)=0: IDD1≤100µA (Normal mode) Cn (n=0 to 2)=1: IDD1≤5µA (Test mode) -7- February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 1/2 DUTY When stopped with CL at the low level. CE CL DI 0 1 1 1 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 D1 D2 D 56 D 57 C0 0 0 0 0 P1 P2 P3 P4 Di sp l a y D at a A d d re ss S0 S1 D M0 D M1 D M2 D M3 D M4 D M5 D M6 D M7 D M8 D M9 0 Co n tr o l Da ta 0 DD CE 0 1 1 1 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 D 58 D 59 D 11 3 D 11 4 0 0 0 0 0 0 0 0 0 C1 C2 0 0 0 0 0 0 0 0 0 0 0 Di sp l a y D at a A d d re ss 0 1 1 1 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 A d d re ss 0 0 0 1 DD 0 0 0 0 0 0 0 5 6 b its 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 DD Figure 3 Note: DD=Direction Data PT6332 V1.0 -8- February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 When stopped with CL at the high level. CE CL DI 0 1 1 1 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 D1 D2 D 56 D 57 C0 0 0 0 0 P1 P2 P3 P4 Di sp l a y D at a A d d re ss S0 S1 D M0 D M1 D M2 D M3 D M4 D M5 D M6 D M7 D M8 D M9 0 Co n tr o l Da ta 0 DD CE 0 1 1 1 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 D 58 D 11 3 D 11 4 0 0 0 0 0 0 0 0 0 C1 C2 0 0 0 0 0 0 0 0 0 0 0 Di sp l a y D at a A d d re ss 0 1 1 1 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 A d d re s s D 59 0 0 0 1 DD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 6 b its 0 1 0 DD Figure 4 Notes: 1. DD 2. Address 3. D1 to D57 4. D58 to D114 5. D53 to D56 6. C0 to C2 PT6332 V1.0 : Direction Data : Applications must send the value (8EH) as shown in figure 3 & 4 : Segment display data for the GR1 digit output pin (when P1 ~ P4 = 0) Dn (n=1 to 57) = 1: Segment on Dn (n=1 to 57) = 0: Segment off : Segment display data for the GR2 digit output pin Dn (n=58 to 114) = 1: Segment on Dn (n=58 to 114) = 0: Segment off : General purpose output pin (when P1 ~ P4=1) Dn (n=53 to 56) = 1: General purpose on (High level) Dn (n=53 to 56) = 0: General purpose off (Low level) : Sleep Mode Current Setup Cn (n=0 to 2)=0: IDD1≤100µA (Normal mode) Cn (n=0 to 2)=1: IDD1≤5µA (Test mode) -9- February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 CONTROL DATA P1 TO P4: SEGMENT DRIVER/GENERAL PURPOSE OUTPUT CONTROL DATA This control data controls switching SG56/P1~SG53/P4 between segment driver and general purpose output. When SG56/P1~SG53/P4 is used as general purpose output which will be not affected by dimming and segment control. Control Bit P1 P2 P3 P4 Data H/L H/L H/L H/L Output Pin Mode P1/SG56 P2/SG55 P3/SG54 P4/SG53 When SG56/P1~SG53/P4 is used as general purpose output. The table lists the relationship between the output pin and control bit as below. Output Pin Mode SG56/P1 SG55/P2 SG54/P3 SG53/P4 Control Bit D56 D55 D54 D53 S0, S1: SLEEP CONTROL DATA This control data controls switching between sleep mode and normal mode, and also sets the states of the KS1 to KS5 key scan output pins in key scan standby mode. Control Data S0 S1 0 0 0 1 1 0 1 1 Mode Normal Sleep Sleep Sleep Clock Generator (oscillator circuit) Oscillator operating Stopped Stopped Stopped Segment Outputs Digit Output Operating L L L Output Pin states during key scan standby KS1 KS2 KS3 KS4 KS5 H H H H H L L L L H L L L H H H H H H H CT0 TO CT3: SLEEP CURRENT CONTROL DATA CT0 0 1 PT6332 V1.0 Control Bit CT1 CT2 0 1 0 1 Current Mode IDD1≤100µA IDD1≤5µA Normal mode Test mode - 10 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 DM0 TO DM9: DIMMER DATA This data controls the duty of the SG1 to SG56 segment output pins. This data forms a 10-bit binary value in which D0 is the LSB. The brightness of the display can be controlled by adjusting the duty of the SG1 to SG56 segment output pins. The table lists the relationship between the dimmer data and the dimmer value. DM9 0 0 0 DM8 0 0 0 DM7 0 0 0 DM6 0 0 0 DM5 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DM4 0 0 0 DM3 0 0 0 DM2 0 0 0 DM1 0 0 1 DM0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 to Dimmer Value (t4/t3) 0/1024 1/1024 2/1024 to 1020/1024 1021/1024 1022/1024 1022/1024 t3 and t4: see figure 7 PT6332 V1.0 - 11 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 RELATIONSHIP BETWEEN THE DISPLAY DAT (D1 TO D168 AND THE SEGMENT OUTPUT PINS) 1/3 DUTY Segment Output Pin SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 SG13 SG14 SG15 SG16 SG17 SG18 SG19 GR1 GR2 GR3 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 D72 D73 D74 D75 D113 D114 D115 D116 D117 D118 D119 D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 Segment Output Pin SG20 SG21 SG22 SG23 SG24 SG25 SG26 SG27 SG28 SG29 SG30 SG31 SG32 SG33 SG34 SG35 SG36 SG37 SG38 GR1 GR2 GR3 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 D145 D146 D147 D148 D149 D150 Segment Output Pin SG39 SG40 SG41 SG42 SG43 SG44 SG45 SG46 SG47 SG48 SG49 SG50 SG51 SG52 SG53 SG54 SG55 SG56 GR1 GR2 GR3 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D95 D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D151 D152 D153 D154 D155 D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 As an example, the table below lists the operation of the SG11 segment output pin. Display Data D11 D67 D123 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 PT6332 V1.0 Segment Output Pin (SG11) State The segments corresponding to the GR1 to GR3 digit output pins are off The segment corresponding to the GR3 digit output pin is on The segment corresponding to the GR2 digit output pin is on The segments corresponding to the GR2 to GR3 digit output pins are on The segment corresponding to the GR1 digit output pin is on The segments corresponding to the GR1 and GR3 digit output pins are on The segments corresponding to the GR1 and GR2 digit output pins are on The segments corresponding to the GR1 to GR3 digit output pins are on - 12 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 RELATIONSHIP BETWEEN THE DISPLAY DAT (D1 TO D114 AND THE SEGMENT OUTPUT PINS) 1/2 DUTY Segment Output Pin SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 SG13 SG14 SG15 SG16 SG17 SG18 SG19 GR1 GR2 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 D72 D73 D74 D75 D76 Segment Output Pin SG20 SG21 SG22 SG23 SG24 SG25 SG26 SG27 SG28 SG29 SG30 SG31 SG32 SG33 SG34 SG35 SG36 SG37 SG38 GR1 GR2 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 Segment Output Pin SG39 SG40 SG41 SG42 SG43 SG44 SG45 SG46 SG47 SG48 SG49 SG50 SG51 SG52 SG53 SG54 SG55 SG56 SG57 GR1 GR2 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 As an example, the table below lists the operation of the SG11 segment output pin. Display Data D11 D68 0 0 0 1 1 0 1 1 PT6332 V1.0 Segment Output Pin (SG11) State The segments corresponding to the GR1 to GR2 digit output pins are off The segment corresponding to the GR2 digit output pin is on The segment corresponding to the GR1 digit output pin is on The segments corresponding to the GR1 to GR2 digit output pins are on - 13 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 SERIAL DATA OUTPUT When stopped with CL at the low level CE CL DI 1 1 1 B0 B1 B2 1 0 0 0 1 B3 A0 A1 A2 A3 A d d re ss DO ∗ KD 1 KD 2 KD 24 KD 25 ∗ SA ∗ ∗ ∗ ∗ O u tp u t Da ta When stopped with CL at the high level CE CL DI 1 1 1 1 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 A d d re ss DO ∗ KD 1 KD 2 KD 3 KD 24 KD 25 SA ∗ ∗ ∗ ∗ ∗ ∗ O u tp u t Da ta Figure 5 Note: * : Don’t Care Address : Applications must send the value (8FH) as shown in figure 5 KD1 to KD25 : Key Data SA : Sleep Acknowledge Data The key data (KD1 to KD25) and the sleep acknowledge data (SA) will be invalid if the key data is read when DO is high. PT6332 V1.0 - 14 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 OUTPUT DATA KD1 TO KD25: KEY DATA These bits represent the key output states when a key matrix with up to 25 keys is formed using the KS1 to KS5 key scan output pins and the KI1 to KI5 key scan input pins. When a key is pressed, the bit corresponding to that key will be set to 1. The correspondence is listed in the following table. Item KS1 KS2 KS3 KS4 KS5 KI1 KD1 KD6 KD11 KD16 KD21 KI2 KD2 KD7 KD12 KD17 KD22 KI3 KD3 KD8 KD13 KD18 KD23 KI4 KD4 KD9 KD14 KD19 KD24 KI5 KD5 KD10 KD15 KD20 KD25 SA: SLEEP ACKNOWLEDGE DATA This output data is set to the state when the key was pressed. In that case DO will go to the low level. If serial data is input during this period and the mode is set (normal mode or sleep mode), the IC will be set to that mode. SA is set to 1 in the sleep mode and to 0 in the normal mode. SLEEP MODE The IC is set to sleep mode by setting either S0 or S1 in the control data to 1. The segment outputs and the digit outputs are all set low, and the clock generator (oscillator circuit) is stopped (although it is restarted when a key is pressed), and thus power dissipation is reduced. This mode is cleared by setting S0 and S1 in the control data to 0. In sleep mode, the status of segment/general purpose output port will not be changed. PT6332 V1.0 - 15 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 KEY SCAN OPERATION KEY SCAN TIMING The scan period is 18000T [s]. A key scan is performed twice to reliably recognize the key on/off state by verifying that the key data for the two scans agrees. If the data agrees, the IC recognizes a key press and 38400T [s] after the start of key scan execution issues a key scan data read request by outputting a low level from DO. If the key data does not agree and a key was pressed at the later scan, the IC executes another key scan operation. Note that this means that this IC cannot recognize a key press shorter than 38400T [s]. KS1 ∗ KS2 ∗ KS3 ∗ KS4 ∗ ∗ 1 1 ∗ 2 2 ∗ 3 3 ∗ 4 4 KS5 5 5 36000T [s] Key on T= 1 [s] fosc Note: *: The high-level and low-level state in sleep mode are set according to the control data S0 and S1. Key scan output signals are not output from pins set to the “L” state. IN NORMAL MODE • The pins KS1 to KS5 are set high. • A key scan is started when any of the keys is pressed, and the keys are kept scanning until all keys are released. The controller can recognize simultaneous multiple key presses by checking the key data for multiple bits being set. • If a key is pressed for over 38400T [s] (where T=1/fosc), the IC outputs a key data read request to the controller by setting DO low. The controller acknowledges this state and reads the key data. However, note that DO will go high when CE is set high during the serial data transfer. • After the controller key data readout completes, the key data read request will be cleared (DO will be set high), and the IC performs another key scan. Note that since DO is an open-drain output, a pull-up resistor (between 1 and 10KΩ) is required. PT6332 V1.0 - 16 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 Key Input 1 Key Input 2 Key scan 38 400 T[s] 38 400 T[s] 38 400 T[s] CE Se rial da ta tran sfe r Se rial da ta tran sfe r Ke y ad dre ss (8FH) Se rial da ta tran sfe r Ke y ad dre ss Ke y ad dre ss DI DO Ke y da ta r ead Ke y da ta r ead re que st Ke y da ta r ead Ke y da ta r ead re que st Ke y da ta r ead Ke y da ta r ead re que st T= 1 [s] fosc IN SLEEP MODE • The pins KS1 to KS5 are set to high or low according to the values of S0 and S1 in the control data. (see the description of the control data elsewhere in this document) • If a key connected to one of the KS1 to KS5 lines that was set high is pressed, the clock generator (oscillator circuit) is started and a key scan is performed, and the keys are kept scanning until all keys are released. The controller can recognize simultaneous multiple key presses by checking the key data for multiple bits being set. • If a key is pressed for over 38400T [s] (where T=1/fosc), the IC outputs a key data read request to the controller by setting DO low. The controller acknowledges this state and reads the key data. However, note that DO will go high when CE is set high during the serial data transfer. • After the controller key data readout completes, the key data read request will be cleared (DO will be set high), and the IC performs another key scan. However, sleep mode will not be cleared. Note that since DO is an open-drain output, a pull-up resistor (between 1 and 10KΩ) is required. • Example of a key scan operation in sleep mode. Example: Sleep mode with S1=0, S1=1 (only KS5 is set high) (L) KS 1 If a n y o n e o f t h e s e k e ys i s p r e ss e d , th e o s ci l l a to r o n th e O S C p i n is s ta r t e d a n d th e ke y s a r e s ca n n e d . (L) KS 2 (L) KS 3 (L) KS 4 (H ) KS5 ∗ KI 1 KI 2 KI 3 KI 4 KI 5 PT6332 V1.0 - 17 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 Note: *: These diodes are required to reliably recognize multiple key presses on the KS5 line when the IC is set to sleep mode with only KS5 set to high as in the example above. That is, they prevent incorrect recognition of key pressed due to sneak currents arising from simultaneous presses of keys on the KS1 through KS4 lines. Key Input (KS6 line) Key scan 61 5T[s] 61 5T[s] CE Se rial da ta tran sfer Se rial da ta tran sfer Ke y ad dre ss (43 H) Se rial da ta tran sfer Ke y ad dre ss DI DO Ke y da ta r ead Ke y da ta r ead re que st PT6332 V1.0 - 18 - Ke y da ta r ead Ke y da ta r ead re que st T= 1 fosc February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 MULTIPLE KEY PRESSES The PT6332, even without diodes in the key scan lines, can scan for any combination of dual key presses, any combination of triple key presses on any of the KI1 to KI5 key scan input pin lines, or any combination of multiple key presses on any of the KS1 to KS5 key scan output lines. However, keys that are not pressed may be seen as having been pressed for any other multiple key press combination. Accordingly, applications must insert diodes at each key. Also, to reject any triple and higher multiple key presses, if three or more data readout are 1 ignore the data by the software or in other ways. NOTES ON THE /BLK PIN AND DISPLAY CONTROL Since the states of the IC internal data (D1 to D168, and the control data) are undefined when power is first applied, applications should turn off the display (i.e. set SG1 to SG56 and GR1 to GR3 low) by setting the /BLK pin low at the same time as power is applied. Applications should transfer all 264 bits of the serial data while /BLK is held low, and only then set /BLK high. This will prevent random meaningless display at power on. (see figure 6) toff1 toff2 ton V DD V FL /B LK V IL tc CE V IL Di sp l a y a n d co n tr o l d a ta tr a n sfe r In ter nal d ata D1 to D5 6 C ontr ol d ata Un d e fi n e d De fi n e d Un d e fi n e d In ter nal d ata D5 7 to D 112 Un d e fi n e d De fi n e d Un d e fi n e d In ter nal d ata D 113 to D1 68 Un d e fi n e d De fi n e d Un d e fi n e d ton > 0 toff1 > 0 toff2 > 0 ( toff1 > to ff2 ) tc ⋅⋅ ⋅⋅ ⋅ ⋅⋅ ⋅⋅ ⋅1 0 µ s mi n. Figure 6 PT6332 V1.0 - 19 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 NOTE ON THE POWER ON SEQUENCE Applications must observe the following sequence when turning the power on or off. • At power on: First turn on the logic system power (VDD), and then turn on the driver power (VFL). • At power off: First turn off the driver power (VFL), and then turn off the logic system power (VDD). V 2V PT6332 V1.0 t - 20 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 OUTPUT WAVEFOORMS (SG1 TO SG56) 1/3 DUTY V FL G R1 V SS V FL G R2 V SS V FL G R3 V SS S G 1 to SG 56 w av efor m wh en the s eg men t c or re spo ndi ng to G R1 is on V FL S G 1 to SG 56 w av efor m wh en the s eg men t c or re spo ndi ng to G R2 is on V FL S G 1 to SG 56 w av efor m wh en the s eg men t c or re spo ndi ng to G R3 is on V FL S G 1 to SG 56 w av efor m wh en the s eg men ts c or re spo ndi ng to G R1 an d G R2 ar e on V FL S G 1 to SG 56 w av efor m wh en the s eg men ts c or re spo ndi ng to G R1 an d G R3 ar e on S G 1 to SG 56 w av efor m wh en the s eg men ts c or re spo ndi ng to G R2 an d G R3 ar e on S G 1 to SG 56 w av efor m wh en the s eg men ts c or re spo ndi ng to G R1 , G R2 a nd G R3 ar e on V SS V SS V SS V SS V FL V SS V FL V SS V FL V SS S G 1 to SG 56 w av efor m wh en the s eg men ts c or re spo ndi ng to G R1 , G R2 a nd G R3 ar e off PT6332 V1.0 - 21 - V FL V SS February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 OUTPUT WAVEFOORMS (SG1 TO SG57) 1/2 DUTY V FL G R1 V SS V FL G R2 V SS S G 1 to SG 57 w av efor m wh en the s eg men t c or re spo ndi ng to G R1 is on V FL S G 1 to SG 57 w av efor m wh en the s eg men t c or re spo ndi ng to G R2 is on V FL S G 1 to SG 57 w av efor m wh en the s eg men ts c or re spo ndi ng to G R1 , G R2 a re o n V SS V SS V FL V SS S G 1 to SG 57 w av efor m wh en the s eg men ts c or re spo ndi ng to G R1 , G R2 a re o ff PT6332 V1.0 - 22 - V FL V SS February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 RELATIONSHIP BETWEEN THE SEGMENT AND DIGIT OUTPUTS G R1 G R2 t3 S G 1 to SG 7 2 E xa mpl e 2 S G 1 to SG 7 2 E xa mpl e 3 S G 1 to SG 7 2 VFL V SS t3 G R3 E xa mpl e 1 VFL V SS t3 t3 t3 t2 t4 t2 t2 t1 t4 t1 t4 t1 t3 t2 t4 t2 t2 t1 t4 t4 t1 t1 VFL V SS VFL V SS VFL V SS VFL V SS Figure 7 • Figure 7 shows the case where the display data is set up so that the segment outputs SG1 to SG56 output the VSS level with the same timing as the GR1 and GR3 digit outputs, and output the VFL level with the same timing as the GR2 digit output. Here, the segments corresponding to GR2 will be turned on. The relationship between t3 and the oscillator frequency fosc in this case is t3=2048/fosc. • The SG1 to SG56 segment output waveforms in example 1 correspond to a dimmer data (DM0 to DM9) set to 3FEH. The relationship between t1 and the oscillator frequency fosc is t1=2/fosc. Note that t1 and t2 in example 1 are identical times. • The SG1 to SG56 segment output waveforms in example 2 correspond to a dimmer data (DM0 to DM9) set to a smaller value. Although t1 does not change, t2 becomes longer. Here, if the dimmer data (DM0 to DM9) is set to 1FFH and the oscillator frequency fosc is 2.4MHz, then t2 can be calculated as follows. t 2 = t 3 − t1 × (1FFH + 1) 1024 fosc = 0.43[ms ] = • If the dimmer data (DM0 to DM9) is set to an even smaller value, t2 will become even longer as shown in example 3. Note that t1 does not change in this case as well. PT6332 V1.0 - 23 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 BLOCK STATES DURING THE RESET PERIOD (when /BLK is low) G ri d D ri ve r SG2 SG1 S G 56/P 1 S G 55/P 2 S G 54/P 3 S G 53/P 4 G R1 G R2 G R3 /SG 57 • Divider and timing generator These circuits are reset and their base clock is stopped. • Dimmer timing generator The circuit is reset and its operation is stopped. • Digit and segment dividers These circuits are reset and the display is turned off (SG1 to SG56 and GR1 to GR3 are set low). • Key scan The circuit is reset, its internal circuits are set to the initial state, and key scanning is disabled. • Key buffer The circuit is reset and all data is set to 0. • Clock generator The state (normal or sleep mode) of this block (the clock oscillator circuit) is determined after the sleep control data (S0 to S1) is transferred. • CCB interface, shift register, control register, latch, and multiplexer The circuits are not reset so that serial data can be input during the reset period. S egm ent Dr iv er 57 /B LK M PX VFL 17 1 V DD La tch V SS 1 D im me r Tim in g G e ner ato r V SS 2 Con tro l R egi ste r 57 16 S hift Reg is ter Tim in g G e ner ato r K ey B uffer Di vi der K I5 K I4 K I3 K I2 K I1 K S5 K S4 K S3 K S2 K S1 K ey S ca n CE CL DI DO Clo ck G e ner ato r DT O S CI C om ma nd Inte rfa ce Block than are reset PT6332 V1.0 - 24 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 OUTPUT PIN STATES DURING THE RESET PERIOD (when /BLK is low) Output Pin SG1 to SG56 GR1 to GR3 KS1 to KS4 KS5 DO State during Reset L L X *1 H H *2 Notes: 1. The state of this pin is undefined after power has been applied until the sleep control data (S0 to S1) are transferred. 2. Since this pin is an open-drain output, a pull-up resistor (between 1 and 10KΩ) is required. It remains high during the reset period even if the controller attempts to read the key data. NOTE ON THE SEGMENT AND DIGIT WAVEFORMS Di git wa ve for m S egm ent w av efor m 1 S egm ent w av efor m 2 Figure 8 The digit waveform is somewhat deformed due to the VFD panel itself and the circuit wiring. Furthermore, if a segment waveform such as segment waveform 1 in which no dimming is applied is used, the display will glow dimly. Therefore, applications must take this waveform deformation into account and apply adequate dimming such as that shown in segment waveform 2 so that this phenomenon does not occur. NOTE ON CONTROLLER TRACSFER OF DISPLAY DATA Since the display data is transferred in three operations as shown in figures 1 & 2, we strongly recommend that applications transfer all the data within a 30ms period to assure display quality. PT6332 V1.0 - 25 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 CONTROLLER KEY DATA READOUT PROCEDURE WHEN THE CONTROLLER USES A TIMER TO READ OUT THE KEY DATA • Flowchart CE=L NO DO=L YES Key data read processing • Timing Chart Key on Key on Key Input Key S can t6 t5 CE t5 t8 DI t7 t5 t8 Ke y d ata rea d t8 t7 t7 DO Ke y d ata r ea d r equ est t9 Co ntr olle r d ete r mina tion ( key on ) t5 t6 t7 t8 t9 Co ntrolle r d ete rmina tion (key on ) t9 Co ntr olle r d ete r mina tion ( key off ) t9 Co ntr olle r d ete rmina tion (key on ) Co ntrolle r d ete rmina tion (key off ) - Key scan execution time (38400T [s]) when the key data for two key scan operations matches. - Key scan execution time (76800T [s]) when the key data for the first two key scan operations does not match. - Key address (8FH) transfer time - Key data readout time PT6332 V1.0 - 26 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 • Operation When the controller use timer processing for key on/off determination and key data readout, it must set CE low and check the state of DO at least once every t9 period. If DO is low, the controller must recognize that a key has been pressed and read out the key data. The period t9 must obey the following inequality: t9 > t7 + t8 + t6 Note: If the controller reads out key data when DO is high, both the key data (KD1 to KD25) and the sleep acknowledge data will be invalid data. PT6332 V1.0 - 27 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 WHEN THE CONTROLLER USES INTERRUPT PROCESSING TO READ OUT THE KEY DATA • Flowchart CE= L DO=L NO YE S K ey data read processing Wait period (st Least t10) CE= L NO DO=H YE S K ey off PT6332 V1.0 - 28 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC • Timing Chart Key Input PT6332 Key on Key on Key S can t5 t5 t6 t5 CE t8 DI t8 t8 t8 Ke y a ddr ess t7 t7 Ke y d ata rea d t7 t7 DO Ke y d ata rea d requ est Co ntro ller de ter m inat ion ( key on ) t5 t6 t7 t8 t10 Co ntr o ller de ter m inat ion (key off ) t10 Co ntr o ller de ter m inat ion (key on ) Co ntr o ller de ter m inat ion (key on ) t10 Co ntr o ller de ter m inat ion (key on ) t10 Co ntr o ller de ter m inat ion (key off ) - Key scan execution time (38400T [s]) when the key data for two key scan operations matches. - Key scan execution time (76800T [s]) when the key data for the first two key scan operations does not match. - Key address (8FH) transfer time 1 T= [ s] fosc - Key data readout time • Operation When the controller use interrupt processing for key on/off determination and key data readout, it must check the state of DO when CE is low, and perform a key data readout if DO is low. The next time the controller checks the on/off states of the keys, it must make that determination at a time t10 after the last readout on the state of DO when CE is low, and then read out the key data. The time t10 must obey the following inequality: t10 > t6 Note: 1. If the controller reads out key data when DO is high, both the key data (KD1 to KD25) and the sleep acknowledge data will be invalid data. PT6332 V1.0 - 29 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 ABSOLUTE MAXIMUM RATINGS (VSS=0V, Ta=25℃) Parameter Maximum Supply Voltage Input Voltage Symbol VDD max VFL max VIN1 VIN2 VOUT1 Output Voltage VOUT2 VOUT3 IOUT1 Output Current Allowable Power Dissipation Operating Temperature Storage Temperature PT6332 V1.0 IOUT2 IOUT3 Pd max Topr Tstg Condition VDD VFL DI, CL, CE, /BLK OSCI, KI1 to KI5 SG1 to SG52, SG53/P4 to SG56/P1, GR1, GR2, GR3/SG57 KS1 to KS5 DO SG1 to SG52, SG53/P4 to SG56/P1 GR1, GR2, GR3/SG57 KS1 to KS5 Ta=85℃ - - 30 - Rating -0.3 ~ +6.5 -0.3 ~ +20 -0.3 ~ VDD+0.3 -0.3 to VDD+0.3 Unit V V V V -0.3 to VFL+0.3 V -0.3 to VDD+0.3 -0.3 ~ VDD+0.3 V V 6 µA 60 1 400 -40 to +85 -65 to +150 mA mA mW ℃ ℃ February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 ALLOWABLE OPERATING RANGES (Ta=25℃, VDD=3.3 to 5V, VFL=18V, VSS=0V) Parameter Symbol Condition Min VDD VDD 3 Supply Voltage VFL 8 VFL VIH1 DI, CL, CE, /BLK 0.8 VDD Input High-Level Voltage KI1 to KI5 0.6 VDD VIH2 DI, CL, CE, /BLK, 0 Low-Level Input Voltage VIL KI1 to KI5 Guaranteed Oscillator Range fosc OSCI 0.9 Recommended External VDD=5V ROSC OSCI Resistance VDD=3.3V Recommended External COSC OSCI 15 Capacitance 5V 160 Clock Low-Level Pulse Width CL: Figure 9 t∅L 3.3V 240 5V 160 Clock High-Level Pulse Width CL: Figure 9 t∅H 3.3V 240 5V 160 Data Setup Time tds DI, CL: Figure 9 3.3V 240 5V 160 Data Hold Time tdh DI, CL: Figure 9 3.3V 240 5V 160 CE Wait Time tcp CE, CL: Figure 9 3.3V 240 5V 160 CE Setup Time tcs CE, CL: Figure 9 3.3V 240 5V 160 CE Hold Time tch CE, CL: Figure 9 3.3V 240 DO, RPU=4.7KΩ, 5V DO Output Delay Time tdc CL=10pf*: Figure 9 3.3V DO, RPU=4.7KΩ, 5V DO Rise Time tdr CL=10pf*: Figure 9 3.3V 5V 10 /BLK Switching Time tC /BLK, CE: Figure 6 3.3V 14 PT6332 V1.0 - 31 - Typ 5.0 12 - Max 5.5 18 5.5 VDD Unit V V V V 0.2 VDD V 2.4 12 7.5 3.7 - MHz 33 100 pF - 1.5 1.6 1.5 1.6 - KΩ ns ns ns ns ns ns ns µs µs µs February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 ELECTRICAL CHARACTERISTICS (Ta=25℃, VDD=3.3 to 5V, VFL=18V, VSS=0V) Parameter High Level Input Current Low Level Input Current Input Floating Voltage Pull-down Resistance Output Off Leakage Current Symbol Unit - 5 µA IIL DI, CL, CE, /BLK, VIN=0V -5 - - µA VIF KI1~KI5 - - 0.05VDD V RPD KI1~KI5: VDD=5.0V 50 100 250 KΩ IOFFH DO: VO=5.0V - - 5 µA VFL-0.6 - - V VFL-1.3 VDD-1.2 VDD-1.2 VDD-0.5 VDD-0.5 VDD-0.2 VDD-0.2 V - - 0.5 V 0.2 0.2 - 0.5 0.5 0.1 0.1 2.4 1.7 0.1VDD 1.5 1.2 0.5 0.4 - - - 100 - - 5 - - 10 VOH2 VOL2 VOL3 Oscillator Frequency fOSC Hysteresis Voltage VH IDD1 IDD2 PT6332 V1.0 Max. - VOL1 Current Drain Typ. DI, CL, CE, /BLK: VIN=5.0V VOH3 Low Level Output Voltage Min. IIH VOH1 High Level Output Voltage Conditions SG1~SG52, SG53/P4~SG56/P1: IO=-2mA GR1, GR2, GR3/SG57: IO=-50mA 5V KS1~KS5: IO=-500µA 3.3V SG1~SG52, SG53/P4~SG56/P1, GR1, GR2, GR3/SG57: IO=50µA 5V KS1~KS5: IO=25µA 3.3V 5V DO: IO=1mA 3.3V ROSC=12KΩ, COSC=33pF 5V 3.3V ROSC=7.5KΩ, COSC=33pF DI, CL, CE, /BLK, KI1~KI5 C0~C2=0 Sleep mode, Normal mode Figure 1~4 C0~C2=1 Test mode Output open: fOSC=2.4MHz - 32 - V V V MHZ V µA mA February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 When stopped with CL at the low level V IH 1 CE CL DI V IL tφ H V IH1 50 % V IL tφ L tcp tcs V IH1 tch V IL tds tdh DO D0 D1 tdc tdr When stopped with CL at the HIGH level V IH 1 CE V IH1 C L 50 % V IL DI tφH V IL tφL tcp tcs tch V IH1 V IL tds td h D0 DO D1 tdc tdr Figure 9 PT6332 V1.0 - 33 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 APPLICATION CIRCUIT 47 46 45 44 43 42 41 SG15 SG16 SG17 SG18 SG19 SG20 SG23 38 64 KS3 SG24 37 65 KS4 SG25 36 66 KS5 SG26 35 67 KI1 SG27 34 68 KI2 SG28 33 69 KI3 SG29 32 70 KI4 SG30 31 71 KI5 SG31 30 72 DT SG32 29 73 /BLK SG33 28 74 DO SG34 27 75 CE SG35 26 76 CL SG36 25 77 DI SG37 24 78 VDD SG38 23 79 OSCI SG39 22 80 VSS2 SG40 21 SG41 SG42 SG43 SG44 SG45 SG46 SG47 SG48 SG49 SG50 SG51 SG52 SG53/P4 SG54/P3 SG55/P2 PT6332 VFD Panel 48 52 SG14 53 SG9 49 54 SG8 SG13 55 SG7 SG12 56 SG6 51 57 SG5 50 58 SG4 SG11 59 SG3 SG10 60 SG1 KS2 SG56/P1 12K 39 63 +18V 33p 40 SG22 VFL 5V/3.3V SG21 KS1 GR3/SG57 * VSS1 GR2 VDD 61 62 GR1 MCU SG2 Key matrix with up to 25 keys Note: *- Since DO is an open-drain output, a pull-up resistor is required. Select a value in the range 1 to 10KΩ that is most appropriate for the capacitance of the external lines so that the waveform is not distorted. PT6332 V1.0 - 34 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 ORDER INFORMATION Valid Part Number PT6332-LQ PT6332 V1.0 Package Type 80 Pin, LQFP - 35 - Top Code PT6332-LQ February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 PACKAGE INFORMATION 80 PINS, LQFP (BODY SIZE: 12MMx12MM, PITCH: 0.50MM, THK: 1.40MM) D D1 A A2 A1 -B- -A- L1 E E1 -D- e c b θ1 C SEATING PLANE θ ccc C θ2 R1 R2 -H- GAUGE PLANE 0.25mm S L θ3 PT6332 V1.0 - 36 - February, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw VFD Driver/Controller IC PT6332 Symbol A A1 Min. 0.05 Nom. - Max. 1.60 0.15 A2 b D 1.35 0.17 1.40 0.22 14.00 BSC. 1.45 0.27 D1 e 12.00 BSC. 0.50 BSC. E E1 14.00 BSC. 12.00 BSC. S R1 0.20 0.08 - - R2 L L1 0.08 0.45 0.60 1.00 REF. 0.20 0.75 C 0.09 - 0.20 θ 0° θ1 0° 3.5° - 7° - θ2 11° 12° 13° θ3 ccc 11° 12° 0.08 13° Notes: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. The top package body may be smaller than the bottom package size as much as 0.15mm. 3. Datum A-B and D to be determined at the datum plane H. 4. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25mm per side. d1 and E1 are maximum plastic body size dimensions including mold mismatch. 5. Controlling Dimensions: Millimeters 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4mm and 0.5mm pitch package. 7. A1 is defined as the distance from the seating plane to the lowest point on the package body. 8. Refer to JEDEC MS-026 Variation BDD. JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY CORPORAITON. PT6332 V1.0 - 37 - February, 2006