PT6552 ½ Duty LCD Driver with On-Chip Key Input Function DESCRIPTION The PT6552 is ½ duty dynamic LCD display driver. In addition to being able to directly Drive LCD panels with up to 90 segments, it can also control up to 4 general purpose output ports. This product also includes a key scan circuit that allows it to accept input from keypads with up to 30 keys. This allows the end product front panel wiring to be simplified. APPLICATIONS • • • • • • • • • Cellular phone Data bank, organizer Electronic dictionary/translator P.D.A. P.O.S. Information appliance Caller ID Pager Electronic equipment with LCD display FEATURES • Up to 4 general purpose output ports • Up to 90 segments outputs • Up to 30 key inputs (Key scan is only performed when a key is pressed) • ½ duty - ½ bias (up to 90 segments) • Serial data control sleep mode and the all segments off function • Serial data controlled segment output port/general-purpose output port usage • Serial data I/O supports CCB format communication with the system controller • High generality since display data is displayed directly without decoder intervention • Reset pin that can establish the initial state • Available in 64 pin QFP and 64 pin LQFP package BLOCK DIAGRAM Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan PT6552 APPLICATION CIRCUIT Note: * Since DO is an open-drain output, a pull-up resistor is required. Select a value (between 1k and 10KΩ) that is appropriate for the capacitance of the external wiring so that the waveforms are not distorted. V1.3 2 July 2010 PT6552 ORDER INFORMATION Valid Part Number PT6552 PT6552LQ Package Type 64 Pin, QFP 64 Pin, LQFP Top Code PT6552 PT6552LQ PIN CONFIGURATION V1.3 3 July 2010 PT6552 PIN CONFIGURATIONS Pin Name I/O SG1/P1 to SG4/P4 SG5 to SG43 O COM1 COM2 O KS1/SG44, KS2/SG45, KS3 to KS6 O KI1 to KI5 I OSC I/O VSS - /RES I VDD - DO CE O I CLK I DI I V1.3 Function Segment outputs: Used to output the display data that is transmitted over the serial data input. Pins SG1/P1 to SG4/P2 can be used as general-purpose outputs according to control data specification. Common driver outputs. The frame frequency fo is (fosc/512)Hz Key scan outputs. When a key matrix is formed, normally a diode will be attached to the key scan timing line to prevent shorts. However, since the output transistor impedance is an unbalanced CMOS output, it will not be damaged if shorted. Pins KS1/SG44 and KS2/SG45 can be used as segment outputs according to control data specification. Key scan inputs: Pin with a built-in pull-down resistor. Oscillator connection: Oscillator circuit can be formed by connecting the pin to a resistor and a capacitor Power supply ground connected. Must be connected to GND. Reset input that re-initializes the LSI internal states. During a reset, the display segments are turned off forcibly regardless of the internal display data. All internal key data is reset to low and the key scan operation is disabled. However, serial data can input during a reset. Power supply connection. A supply voltage of between 4.5 and 6.0V must be provided. Serial data interface: CE: Chip enable Connected to the controller. CLK: Synchronization Since DO is an open-drain clock output, it required a pull-up DI: Transfer data resistor. DO: Output data 4 Active Handing when unused Pin No. - Open 1 to 4 5 to 43 - Open 44 45 - Open 46 47 48 to 51 H GND 52 to 56 - VDD 57 - - 58 L GND 59 - - 60 H Open 61 62 GND 63 - 64 July 2010 PT6552 FUNCTION DESCRIPTION SERIAL DATA INPUT WHEN STOPPED WITH CLK AT THE LOW LEVEL WHEN STOPPED WITH CLK AT THE HIGH LEVEL CCB address: 42H D1 to D90: Display data S0, S1: Sleep control data K0, K1: Key scan output/segment output selection data P0, P1: Segment output port/general-purpose output port selection data SC: Segment on/off control data V1.3 5 July 2010 PT6552 CONTROL SERIAL DATA FUNCTION 1. S0, S1: SLEEP CONTROL DATA This control data switches the LSI between normal mode and sleep mode. It also sets the key scan output standby states for pinsKS1 to KS6. Control Data Key scan standby mode output pin states Segment outputs Mode Oscillator Common outputs S0 S1 KS1 KS2 KS3 KS4 KS5 KS6 0 0 Normal Oscillator Operation H H H H H H 0 1 Sleep Stopped L L L L L L H 1 0 Sleep Stopped L L L L L H H 1 1 Sleep Stopped L H H H H H H 2. K0, K1: KEY SCAN OUTPUT/SEGMENT OUTPUT SELECTION DATA This control data switches the KS1/SG44 and KS2/SG45 output pins between the key scan output and segment output function. Control data Output pin states Maximum number of key inputs K0 K1 KS1/SG44 KS2/SG45 0 0 KS1 KS2 30 0 1 SG44 KS2 25 1 X SG44 SG45 20 X: don’t care 3. P0, P1: SEGMENT OUTPUT PORT/GENERAL-PURPOSE OUTPUT PORT SELECTION DATA This control data switches the SG1/P1 to SG4/P4 output pins between the segment output port and the general-purpose output port function. Control data Output pin states P0 P1 SG1/P1 SG2/P2 SG3/P3 SG4/P4 0 0 SG1 SG2 SG3 SG4 0 1 P1 P2 SG3 SG4 1 0 P1 P2 P3 SG4 1 1 P1 P2 P3 P4 The table below lists the correspondence between the display data and the output pins when the general-purpose output port function is selected. Output pin Corresponding display data SG1/P1 D1 SG2/P2 D3 SG3/P3 D5 SG4/P4 D7 For example, if the output pin SG4/P4 is set for use as a general-purpose output port, the output pin SG4/P4 will output a high level when the display data D7 is 1. 4. SC: SEGMENT ON/OFF CONTROL DATA This control data controls the segment on/off states. SC 0 1 Display states On Off V1.3 6 July 2010 PT6552 DISPLAY DATA L SERIAL DATA FUNCTION Output Pin SG1/P1 SG2/P2 SG3/P3 SG4/P4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 SG13 SG14 SG15 SG16 SG17 SG18 SG19 SG20 SG21 SG22 SG23 SG24 SG25 SG26 SG27 SG28 SG29 SG30 SG31 SG32 SG33 SG34 SG35 SG36 SG37 SG38 SG39 SG40 SG41 SG42 SG43 KS1/SG44 KS2/SG45 COM1 D1 D3 D5 D7 D9 D11 D13 D15 D17 D19 D21 D23 D25 D27 D29 D31 D33 D35 D37 D39 D41 D43 D45 D47 D49 D51 D53 D55 D57 D59 D61 D63 D65 D67 D69 D71 D73 D75 D77 D79 D81 D83 D85 D87 D89 COM2 D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30 D32 D34 D36 D38 D40 D42 D44 D46 D48 D50 D52 D54 D56 D58 D60 D62 D64 D66 D68 D70 D72 D74 D76 D78 D80 D82 D84 D86 D88 D90 For example, the output states of output pin SG11 are listed in the table below. Display data D21 D22 0 0 0 1 1 0 1 1 V1.3 Output pin state SG11 Segment off for both COM1 and COM2 Segment on for COM2 Segment on for COM1 Segment on for both COM1 and COM2 7 July 2010 PT6552 SERIAL DATA OUTPUT WHEN STOPPED WITH CLK AT THE LOW LEVEL WHEN STOPPED WITH CLK AT THE HIGH LEVEL CCB address: 43H KD1 to KD30: Key data SA: Sleep acknowledge data Note: If key data is read when DO is high, the key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. V1.3 8 July 2010 PT6552 OUTPUT DATA KD1 TO KD30: KEY DATA When a key matrix with up to 30 keys is formed using the KS1 to KS6 output pins and the KI1 to KI5 input pins, the key data corresponding to given key will be 1 if that key is pressed. The table below lists that correspondence. Item KS1/SG44 KS2/SG45 KS3 KS4 KS5 KS6 KI1 KD1 KD6 KD11 KD16 KD21 KD26 KI2 KD2 KD7 KD12 KD17 KD22 KD27 KI3 KD3 KD8 KD13 KD18 KD23 KD26 KI4 KD4 KD9 KD14 KD19 KD24 KD29 KI5 KD5 KD10 KD15 KD20 KD25 KD30 When the output pins KS1/SG44 and KS2/SG45 are selected for segment output by the control data K0 and K1, the key data items KD1 to KD10 will be 0. SA: SLEEP ACKNOWLEDGE DATA This output data is set according to the state when the key was pressed. If the LSI was in sleep mode, SA will be 1, and if the LSI was in normal mode, SA will be 0. SLEEP MODE When S0 or S1 in the control data is set to 1, the oscillator at the OSC pin will stop (it will restart if a key is pressed) and the segment and common outputs will all go to the low level. This reduces the LSI power dissipation. However, the SG1/P1 to SG4/P4 output pins can be used as general-purpose output ports even in sleep mode if selected for such use by the P0 and P1 control data bits KEY SCAN OPERATING KEY SCAN TIMING The key scan period is 375T[s]. The key scan is performed twice to reliably determine the key on/off states, and the LSI detects key data agreement. When the key data agrees, the LSI determines that a key has been pressed, and outputs a key read request (by setting DO low) 800T[s] after the key scan started. If a key is pressed again without the key data agreeing, a key scan is performed 1=once more. Thus key on/off operations shorter than 800T[s] cannot be detected. Note: *1: The high or low states of these signals in sleep mode are determined by the S0 and S1 control data bits. V1.3 9 July 2010 PT6552 KEY SCAN DURING NORMAL MODE The pins KS1 to KS6 are set high. A key scan starts if any key is pressed, and the scan continues until all keys have been released. Multiple key pressed can be recognized be determining if multiple key data bits have been set. When a key has been pressed for 800T[s] (when T=1/fosc) or longer, a key data read request (DO is set to low) is output to the controller. The controller acknowledges this request and reads the key data; however, DO will go high when CE is high during a serial data transfer. After the controller has finished reading the key data, the LSI clears the key data read request (by setting DO high) and performs another key scan. Note that since DO is an open drain output, a pull-up resistor of between 1K and 10KΩ is required. KEY SCAN DURING SLEEP MODE The pins KS1 to KS6 are set high or low according to the S0 and S1 control data bits. (see the description of the control data function for details)If a key for a line corresponding to one of the pins KS1 to KS6 which is high is pressed, the oscillator at the OSC pin starts and a key scan is performed. The key scan continues until all keys have been released. Multiple key presses can be recognized by determining if multiple key data bits have been set. When a key has been pressed for 800T[s] (where T=1/fosc) or longer, a key data read request (D0 is set to low) is output to the controller. The controller acknowledges this request and reads the key data; however, DO will go high when CE is high during a serial data transfer. After the controller has finished reading the key data, the LSI clears the key data read request (by setting DO high) and performs another key scan. Note that since DO is an open drain output, a pull-up resistor of between 1k and 10KΩ is required. Key scan example in sleep mode. Example: Here S0 = 0 and S1 = 1 (This is a sleep in which only KS6 is high) Note: *1=These diodes are required to reliably recognize events in which three or more of the keys on the KS6 line are pressed at the same time. V1.3 10 July 2010 PT6552 MULTIPLE KEY PRESSES Without the insertion of additional diodes, the PT6552 supports key scan for double key presses in general, triple key presses of keys on the lines for input pins KI1 to KI5, and multiple key pressed of keys on the lines for the output pins KS1 to KS6. However, if multiple key presses in excess of these limits occur, the PT6552 may recognize keys that were not pressed as having been pressed. Therefore, series diodes must be connected to each key. ½ DUTY – ½ BIAS LCD DRIVE SCHEME V1.3 11 July 2010 PT6552 NTERNAL BLOCK STATES DURING THE RESET PERIOD (WHEN /RES IS LOW) CLOCK GENERATOR Reset is applied and the basic clock stops. However, the state of the OSC pin (the normal or sleep state) is determined after the control data S0 and S1 has been sent. COMMON DRIVER, SEGMENT DRIVER & LATCH Reset is applied and the display is turned off. However, display data can be input to the LATCH. KEY SCAN Reset is applied and at the same time as the internal states are set to their initial states, the key scan operation is disabled. KEY BUFFER Reset is applied and all the key data is set to the low level. CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER To allow serial data transfers, reset is not applied to these circuits. V1.3 12 July 2010 PT6552 OUTPUT PIN STATES DURING THE RESET PERIOD (WHEN /RES IS LOW) Output Pin SG1/P1 to SG4/P4 SG5 to SG43 COM1, COM2 KS1/SG44, KS2/SG45 KS3 to KS5 KS6 DO State During Reset L *1 L L L *1 X *2 H H *3 X: don’t care Notes: *1: These output pins are forcibly set to the segment output mode and held low. *2: Immediately following power on, these output pins are undefined until the control data S0 and S1 has been sent. *3: Since this output pin is an open-drain output, a pull-up resistor of between 1k and 10KΩ is required. This pin is held high during the reset period even if key data is read. NOTE ON CONTROLLER DISPLAY DATA TRANSFER The PT6552 transfers the display data (D1 to D90) in two operations. To assure visual display quality, all the display data should be sent within a 30ms or shorter period. V1.3 13 July 2010 PT6552 NOTE ON CONTROLLER KEY DATA READ TECHNIQUES When determining key on/off and reading key data, the controller must confirm the state of D0 output when CE is low for each period t7. When DO is low, the controller recognizes that a key has been pressed and reads the key data. During this operation t7 must obey the following condition: t7 > t5 + t6 + t4 If key data is read when DO is high, the key data (KD1 to KD30) and the sleep acknowledge data (SA) will be invalid. 1. CONTROLLER KEY DATA READING UNDER TIMER CONTROL FLOWCHART TIMING CHART T=1/fosc t3: Key scan execution time (800T [s]) when the key scan data for two key scans agrees. t4: Key scan execution time (1600T [s]) when the key scan data for two key scans does not agree and a key scan is executed again. t5: Key address (43H) transfer time. t6: Key data read time. V1.3 14 July 2010 PT6552 2. CONTROLLER KEY DATA READING UNDER INTERRUPT CONTROL When determining key on/of and reading key data, the controller must confirm the state of DO output when CE is low. When DO is low, the controller recognizes that a key has been pressed and reads the key data. After the time t8, the next key on/off determination and reading key data must be confirmed by the state of DO output when CE is low. During this operation t8 must obey the following condition: t8 > t4. If key data is read when DO is high, the key data (KD1 to KD30) and the sleep acknowledge data (SA) be invalid. FLOWCHART TIMING CHART T=1/fosc t3: Key scan execution time (800T [s]) when the key scan data for two key scans agrees. t4: Key scan execution time (1600T [s]) when the key scan data for two key scans does not agree and a key scan is executed again. t5: Key address (43H) transfer time. t6: Key data read time. V1.3 15 July 2010 PT6552 /RES AND THE DISPLAY CONTROLLER Since the LSI internal data (D1 to D90 and the control data) is undefined when power is first applied, the output pins SG1/P1 to SG4/P4, SG5 to SG43, COM1, COM2, KS1/SG44 and KS2/SG45 should be held low by setting the /RES pin low at the same time as power is applied. Then, meaningless displays at power on can be prevented by transferring data from the controller and setting /RES high when that transfer has completes. t1: Determined by the value of C and R t2: 10μs min Figure 1 V1.3 16 July 2010 PT6552 ABSOLUTE MAXIMUM RATINGS (VSS=0V, Ta=25℃) Parameter Maximum supply voltage Input voltage Symbol VDD max VIN Output voltage Output current Allowable power dissipation Operating temperature Storage temperature Condition VDD OSC, CE, CLK, DI, /RES, KI1 to KI5 OSC, DO, SG1 to SG45, COM1, COM2, KS1 to KS6, P1 to P4 SG1 to SG45 COM1, COM2, KS1 to KS6 P1 to P4 Ta=85℃ VOUT IOUT1 IOUT2 IOUT3 Pd max Topr Tstg Rating -0.3 ~ +7.0 -0.3 to VDD+0.3 Unit V V -0.3 to VDD+0.3 V 100 1 5 200 -40 to +85 -65 to +150 μA mA mA mW ℃ ℃ ALLOWABLE OPERATING RANGES (Ta=-40 to +85℃, VSS=0V) Parameter Supply voltage Input high-level voltage Input low-level voltage Recommended external resistance Recommended external capacitance Guaranteed oscillator range Data setup time Data hold time CE wait time CE setup time CE hold time High-level clock pulse width Low-level clock pulse width Rise time Fall time Symbol VDD VIH1 VIH2 ROSC Condition VDD CE, CLK, DI, /RES KI1 to KI5 CE, CLK, DI, /RES, KI1 to KI5 OSC COSC OSC fosc tds tdh tcp tcs tch t∅H t∅L tr tf OSC CLK, DI: Figure 2 CLK, DI: Figure 2 CE, CLK: Figure 2 CE, CLK: Figure 2 CE, CLK: Figure 2 CLK: Figure 2 CLK: Figure 2 CE, CLK, DI: Figure 2 CE, CLK, DI: Figure 2 DO, RPU=47KΩ, CL=10pF*: Figure 2 DO, RPU=47KΩ, CL=10pF*: Figure 2 Figure 1 VIL DO output delay time tdc DO rise time tdr /RES switching time t2 V1.3 17 Min. 4.5 0.8VDD 0.6VDD Typ. 0 25 160 160 160 160 160 160 160 Max. 6.0 VDD VDD Unit V V V 0.2VDD V 62 KΩ 680 pF 50 100 KHz ns ns ns ns ns ns ns ns ns 1.5 μs 1.5 μs 160 160 10 μs July 2010 PT6552 ELECTRICAL CHARACTERISTICS IN THE ALLOWABLE OPERATING RANGES Parameter Symbol Hysteresis VH Input high-level current IIH Input low-level current IIL Input floating voltage Pull-down resistance Output off leakage current Output high-level voltage Output low-level voltage VIF RPD IOFFH VOH1 VOH2 VOH3 VOH4 VOL1 VOL2 VOL3 VOL4 VOL5 VMID1 Output middle-level voltage VMID2 Current drain V1.3 IDD1 IDD2 Condition CE, CLK, CI, /RES, KI1 to KI5 CE, CLK, DI, /RES: VI=VDD CE, CLK, DI, /RES: VI=0V KI1 to KI5 KI1 to KI5:VDD=5.0V DO:VO=6.0V KS1 to KS6:IO=-1mA P1 to P4:IO=-1mA SG1 to SG45: IO=-10μA COM1, COM2: IO=-100μA KS1 to KS6:IO=50μA P1 to P4:IO=1mA SG1 to SG45:IO=10μA COM1, COM2: IO=-100μA DO:IO=1mA COM1, COM2: VDD=6.0V, IO=±100μA COM1, COM2: VDD=4.5V, IO=±100μA Sleep Mode, Ta=25℃ VDD=6.0V, Output open, Ta=25℃, fosc=50KHz 18 Min Typ Max 0.1VDD Unit V 5.0 -5.0 μA μA 0.1 3.0 1.0 1.0 0.6 0.5 V KΩ μA V V V V V V V V V 2.4 3.0 3.6 V 1.65 2.25 2.85 V 5 μA 2.5 mA 50 100 VDD-1.0 VDD-1.0 VDD-1.0 VDD-0.6 0.4 1.0 1.4 0.05VDD 250 6.0 July 2010 PT6552 WHEN STOPPED WITH CL AT THE LOW LEVEL WHEN STOPPED WITH CL AT THE HIGH LEVEL Figure 2 V1.3 19 July 2010 PT6552 PACKAGE INFORMATION 64 PINS, QFP Symbol A A1 A2 b c D D1 E E1 e L L1 Min. 0.00 1.90 0.29 0.11 θ 0° 0.65 Nom. 0.35 17.20 BSC 14.00 BSC 17.20 BSC 14.00 BSC 0.80 BSC 1.60 REF Max. 3.15 0.25 2.90 0.41 0.23 - 8° 1.05 Notes: 1. Refer to JEDEC MC-022BE 2. Unit: mm V1.3 20 July 2010 PT6552 64 PINS, LQFP Symbol A A1 A2 b c D D1 E E1 e L L1 Min. 0.05 1.35 0.17 0.09 Nom. Max. 1.60 0.15 1.40 1.45 0.22 0.27 0.20 12.00 BSC 10.00 BSC 12.00 BSC 10.00 BSC 0.50 BSC 0.45 0.60 0.75 1.00 REF θ 0° 3.5° 7° Notes: 1. All dimensions are in millimeter. 2. Refer to JEDEC MS-026BCD V1.3 21 July 2010 PT6552 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V1.3 22 July 2010