PTC PT6522

PT6522
LCD Display Driver
DESCRIPTION
The PT6522 is a general purpose LCD display driver
which can be used for frequency display applications
in microprocessor-controlled radio receivers and other
display applications.
APPLICATIONS
•
•
•
•
•
•
Electronic dictionary/calculator
P.O.S. terminal
Call ID device
Pager
Mini component system
Electronic equipment with LCD display
FEATURES
• 53 segment outputs
• Two drive types are possible: static (1/1) duty (53
segments) and 1/2 duty (104 segments)
• INH pin for turning off all display output
• RC oscillation circuit
• Power supply voltage: 3.0 to 6.5V
• Available in 64-pin QFP or LQFP package
BLOCK DIAGRAM
Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT6522
APPLICATION CIRCUIT 1
Note: 39KΩ ≥ R ≥ 10KΩ
APPLICATION CIRCUIT 2
Note:
When power (VDD) is first applied, the internal display data is undefined and a meaningless pattern will result if the display is turned on in this state. To
avoid the display should be turned off by setting /INH low and turned on only after display data has been sent from the controller.
V1.6
2
August 2010
PT6522
ORDERING INFORMATION
Valid Part Number
PT6522-Q
PT6522LQ
Package Type
64 pins, QFP
64 pins, LQFP
Top Code
PT6522-Q
PT6522LQ
PIN CONFIGURATION
PIN DESCRIPTION
Pin Name
SG1 to SG53
OSC
VSS, VDD
/INH
VLCD
CE, CLK, DI
COM1, COM2
NC
V1.6
Description
Segment output pins
Oscillator connection
Power supply
Display off control input
/INH=low (VSS)=Display off (SG1 to SG53, COM1, COM2=low)
/INH=high (VDD)=Display on
Note that serial data transfers are allowed when display output is turned off using this
pin.
LCD bias voltage setting
Serial data transfer inputs
Common output pins (For static (1/1) drive only COM1 is used, COM2 must be left
open)
No connection
3
Pin No.
1~23, 25~53
55
59, 56
57
58
60, 61, 62
64, 63
24
August 2010
PT6522
INPUT/OUPUT CONFIGURATIONS
The schematic diagrams of the input and output circuits of the logic section are shown below:
INPUT PIN: CLK, CE, DI, /INH
OUTPUT PIN: COM1 TO COM2, SG1 TO SG53
V1.6
4
August 2010
PT6522
FUNCTION DESCRIPTION
DATA TRANSFER FORMAT
1. Static (1/1) duty
2. 1/2 duty (if there are no more that 52 display segments, only 64 bits need to be transferred. The transfer format is the
same as the static duty case. It is not possible to alter the D54 to D106 data without specifying the D1 to D53 data.)
Address: A2H
DP: Drive type selection bit
DP=0: 1/1 duty
DP=1: 1/2 duty
D1 to D106: Display data
Dn (for n=1 to 106)=0: Segment off
Dn (for n=1 to 106)=1: Segment on
x: don't care
DATA TRANSFER EXAMPLES
1. Static duty
2. 1/2 duty with 52 or fewer segments
3. 1/2 duty with more than 52 segments
Note: the following transfer format is not allowed in 1/2 duty with 52 or fewer segments.
V1.6
5
August 2010
PT6522
SERIAL DATA
1. STATIC DUTY (64 BITS)
2. 1/2 DUTY (128 BITS)
V1.6
6
August 2010
PT6522
OUTPUT WAVEFORMS
1. STATIC DUTY
2. 1/2 DUTY
V1.6
7
August 2010
PT6522
ABSOLUTE MAXIMUM RATINGS
(Unless otherwise specified, Ta=25℃, VSS=0V)
Parameter
Symbol
VDDmax
Maximum supply voltage
VLCD
VIN1
Input voltage
VIN2
Output voltage
VOUT
IOUT1
Output current
IOUT2
Allowable power dissipation
Pd max
Operating temperature
Topr
Storage temperature
Tstg
Conditions
VDD
VLCD
CE, CLK, DI, /INH
OSC: output off
OSC: output off
SG1 to SG53
COM1, COM2
Ta=85℃
-
Ratings
-0.3 to +7.0
-0.3 to VDD +0.3
-0.3 to +7.0
-0.3 to VDD +0.3
-0.3 to VDD +0.3
100
1.0
100
-40 to +85
-65 to +150
Unit
V
V
V
V
V
μA
mA
mW
℃
℃
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, Ta=25℃, VSS=0V)
Parameter
Symbol
Conditions
High-level input current
IIH
CE, CLK, DI, /INH: VDD
Low-level input current
IIL
CE, CLK, DI, /INH: VI=0V
High-level output
VOH1
SG1 to SG53: IO=-10μA
voltage
Low-level output voltage
VOL1
SG1 to SG53: IO=10μA
High-level output
VOH2
COM1, COM2: IO=-100μA
voltage
Low-level output voltage
VOL2
COM1, COM2: IO=100μA
VMID1 COM1, COM2: VLCD=6.5V, IO=±100μA
Mid-level voltage
VMID2 COM1, COM2: VLCD=3.0V, IO=±100μA
Oscillator frequency
FOSC
OSC: R=51KΩ, C=680pF
Hysteresis width
VH
CE, CLK, DI: VDD=5V
IDD
VDD=5V, Output=open
Supply current
ILCD
VLCD
Min.
-5
Typ.
-
Max.
5
-
Unit
μA
μA
VLCD - 1.0
-
-
V
-
-
1.0
V
VLCD - 0.6
-
-
V
2.65
0.9
40
0.3
-
3.25
1.5
50
-
0.6
3.85
2.1
60
0.5
2
V
V
V
KHz
V
mA
mA
ALLOWABLE OPERATING RANGES
(Unless otherwise specified, Ta=25℃, VSS=0V)
Parameter
Symbol
VDD
Supply voltage
VLCD
High-level input voltage
VIH1
Low-level input voltage
VIL1
High-level input voltage
VIH2
Low-level input voltage
VIL2
Recommended external resistance
ROSC
Recommended external capacitance
COSC
Guaranteed oscillation range
FOSC
Clock low-level pulse width (See figure)
toL
Clock high-level pulse width (See figure)
toH
Data setup time (See figure)
tds
Data hold time (See figure)
tdh
CE wait time (See figure)
tcp
CE setup time (See figure)
tcs
CE hold time (See figure)
tch
V1.6
Conditions
VDD
VLCD
/INH
/INH
CE, CLK, DI
CE, CLK, DI
OSC
OSC
OSC
CLK
CLK
CLK, DI
CLK, DI
CE, CLK
CE, CLK
CE, CLK
8
Min.
3.0
3.0
0.7 VDD
0
0.8 VDD
0
25
250
250
250
250
250
250
250
Typ.
51
680
50
-
Max.
6.5
VDD
6.5
0.3 VDD
6.5
0.2 VDD
100
-
Unit
V
V
V
V
V
V
KΩ
pF
KHz
ns
ns
ns
ns
ns
ns
ns
August 2010
PT6522
1. CLK IS TERMINATED AT “LOW” LEVEL
2. CLK IS TERMINATED AT “HIGH” LEVEL
Figure
V1.6
9
August 2010
PT6522
TRANSFER (EXTERNAL INPUT) DATA/OUTPUT PIN
CORRESPONDENCE
Note: Only COM1 is used in static (1/1 duty) drive.
DP
Output Pin
SG1
SG2
D1
D2
SG3
D3


SG26
D26
SG27
D27
SG28
D28


SG43
D43
SG44
SG45
SG46
SG47
SG48
SG49
SG50
SG51
SG52
SG53
V1.6
0
1/1 duty
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
1
1/2 duty
D1
D2
D3
D4
D5
D6
COM1








D51
D52
D54
D55
D56
D57



D86
D87
D88
D89
D90
D91
D92
D93
D94
D95
D96
D97
D98
D99
D100
D101
D102
D103
D104
D105
Always on
Always on

10
COM2




























August 2010
PT6522
PACKAGE INFORMATION
64 PINS, QFP PACKAGE
(BODY SIZE: 14mm x 14mm, PITCH: 0.80mm)
Symbol
A
A1
A2
b
c
D
D1
E
E1
e
L
L1
Min.
0.00
1.90
0.29
0.11
θ
0°
0.65
Nom.
0.35
17.20 BSC
14.00 BSC
17.20 BSC
14.00 BSC
0.80 BSC
1.60 REF
Max.
3.15
0.25
2.90
0.41
0.23
-
8°
1.05
Notes:
1. Refer to JEDEC MC-022BE
2. All dimensions are in millimeter.
V1.6
11
August 2010
PT6522
64 PINS, LQFP PACKAGE
(BODY SIZE: 10mm x 10mm, THK BODY: 1.40mm)
Symbol
A
A1
A2
b
c
D
D1
E
E1
e
L
L1
Min.
0.05
1.35
0.17
0.09
θ
0°
0.45
Nom.
1.40
0.22
12.00 BSC
10.00 BSC
12.00 BSC
10.00 BSC
0.50 BSC
0.60
1.00 REF
Max.
1.60
0.15
1.45
0.27
0.20
3.5°
7°
0.75
Notes:
1. All dimensions are in millimeter.
2. Refer to JEDEC MS-026BCB
V1.6
12
August 2010
PT6522
IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and to discontinue any product without notice at any time.
PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No
circuit patent licenses are implied.
Princeton Technology Corp.
2F, 233-1, Baociao Road,
Sindian, Taipei 23145, Taiwan
Tel: 886-2-66296288
Fax: 886-2-29174598
http://www.princeton.com.tw
V1.6
13
August 2010