PCS5I9351 November 2006 rev 0.3 2.5V or 3.3V, 200MHz, 9-Output Zero Delay Buffer Features The PCS5I9351 features LVPECL and LVCMOS reference • Output frequency range: 25MHz to 200MHz clock inputs and provides 9 outputs partitioned in 4 banks • Input frequency range: 25MHz to 200MHz • 2.5V or 3.3V operation • Split 2.5V/3.3V outputs • ± 2.5% max Output duty cycle variation compatible output can drive 50Ω series or parallel • Nine Clock outputs: Drive up to 18 clock lines terminated transmission lines. For series terminated • Two reference clock inputs: LVPECL or LVCMOS transmission lines, each output can drive one or two traces • 150-pS max output-output skew giving the device an effective fanout of 1:18. • Phase-locked loop (PLL) bypass mode The PLL is ensured stable given that the VCO is configured • ‘SpreadTrak’ to run between 200MHz to 500MHz. This allows a wide • Output enable/disable range of output frequencies from 25MHz to 200MHz. For • Pin-compatible with MPC9351 and CY29351. normal operation, the external feedback input, FB_IN, is • Industrial temperature range: -40°C to +85°C • 32-pin 1.0mm TQFP & LQFP Packages. 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see Table.2. These dividers allow output to input ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each LVCMOS connected to one of the outputs. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see the Table 1. When PLL_EN is LOW, PLL is bypassed and the reference Functional Description The PCS5I9351 is a low of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by clock directly feeds the output dividers. This mode is fully voltage high performance 200MHz PLL-based zero delay buffer designed for high static and the minimum input clock frequency specification does not apply. speed clock distribution applications. PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. PCS5I9351 November 2006 rev 0.3 Block Diagram SELA PLL_EN REF_SEL TCLK PECL_CLK Phase Detector VCO 200-500MHz ÷2/ ÷4 QA ÷4/ ÷8 QB ÷4/ ÷8 QC0 QC1 LPF FB_IN SELB SELC ÷4/ ÷8 OE# QD0 QD1 QD2 SELD VSS VDDQB QB QA VSS TCLK Pin Configuration PLL_EN REF_SEL QD3 QD4 32 31 30 29 28 27 26 25 AVDD 1 24 FB_IN 2 23 QC0 VDDQC SELA 3 22 QC1 SELB 4 21 VSS SELC 5 20 QD0 SELD 6 19 VDDQD AVSS 7 18 QD1 PECL_CLK 8 17 VSS PCS5I9351 QD2 VDDQD QD3 VSS QD4 VDD OE# PECL_CLK# 9 10 11 12 13 14 15 16 2.5V or 3.3V, 200MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 2 of 13 PCS5I9351 November 2006 rev 0.3 Pin Configuration1 Pin # Pin Name I/O Type 8 PECL_CLK I, PU Analog I, PU/PD Analog LVPECL reference clock input. Weak pull-up to VDD/2. I, PD LVCMOS LVCMOS/LVTTL reference clock input QA O LVCMOS Clock output bank A QB O LVCMOS Clock output bank B QC(1:0) O LVCMOS Clock output bank C QD(4:0) O LVCMOS Clock output bank D 9 PECL_CLK# 30 TCLK 28 26 22, 24 12, 14, 16, 18, 20 Description LVPECL reference clock input. 2 FB_IN I, PD LVCMOS 10 OE# I, PD LVCMOS Feedback clock input. Connect to an output for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. Output enable/disable input. See Table 2. 31 PLL_EN I, PU LVCMOS PLL enable/disable input. See Table 2. 32 REF_SEL I, PD LVCMOS Reference select input. See Table 2. 3, 4, 5, 6 27 23 15, 19 SEL(A:D) VDDQB VDDQC VDDQD I, PD Supply Supply Supply LVCMOS VDD VDD VDD Frequency select input, Bank (A:D). See Table 2. 2.5V or 3.3V Power supply for bank B output clock2,3 2.5V or 3.3V Power supply for bank C output clocks2,3 2.5V or 3.3V Power supply for bank D output clocks2,3 1 AVDD Supply VDD 2.5V or 3.3V Power supply for PLL2,3 11 VDD Supply VDD 7 13, 17, 21, 25, 29 AVSS Supply Ground 2.5V or 3.3V Power supply for core, inputs, and bank A 2,3 output clock Analog ground VSS Supply Ground Common ground Note: 1 PU = Internal pull-up, PD = Internal pull-down. 2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output power supply pins. 2.5V or 3.3V, 200MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 3 of 13 PCS5I9351 November 2006 rev 0.3 Table 1: Frequency Table Feedback Output Divider VCO Input Frequency Range (AVDD = 3.3V) Input Frequency Range (AVDD = 2.5V) ÷2 Input Clock * 2 100MHz to 200MHz 100MHz to 190MHz ÷4 Input Clock * 4 50MHz to 125MHz 50MHz to 95MHz ÷8 Input Clock * 8 25MHz to 62.5MHz 25MHz to 47.5MHz Table 2: Function Table Control Default 0 1 REF_SEL 0 TCLK PLL_EN 1 PCLK Bypass mode, PLL disabled. The input clock connects to the output dividers OE# 0 Outputs enabled SELA 0 ÷2 (Bank A) Outputs disabled (three-state), VCO running at its minimum frequency ÷ 4 (Bank A) SELB 0 ÷4 (Bank B) ÷ 8 (Bank B) SELC 0 ÷4 (Bank C) ÷ 8 (Bank C) SELD 0 ÷4 (Bank D) ÷ 8 (Bank D) PLL enabled. The VCO output connects to the output dividers Absolute Maximum Ratings Parameter Description Condition VDD DC Supply Voltage VDD DC Operating Voltage Functional VIN DC Input Voltage DC Output Voltage VOUT VTT Min Max Unit -0.3 5.5 V 2.375 3.465 V Relative to VSS -0.3 VDD+ 0.3 V Relative to VSS -0.3 VDD+ 0.3 V VDD ÷2 V 150 mVp-p Output termination Voltage LU Latch Up Immunity Functional RPS Power Supply Ripple Ripple Frequency < 100kHz TS Temperature, Storage Non-functional -65 +150 °C TA Temperature, Operating Ambient Functional -40 +85 °C TJ Temperature, Junction Functional ØJC Dissipation, Junction to Case Functional ØJA Dissipation, Junction to Ambient Functional ESDH FIT ESD Protection (Human Body Model) Failure in Time 200 mA +150 °C/W 105 °C/W 2000 Manufacturing test °C 42 Volts 10 ppm Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2.5V or 3.3V, 200MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 4 of 13 PCS5I9351 November 2006 rev 0.3 DC Electrical Specifications (VDD = 2.5V ± 5%, TA = -40°C to +85°C) Parameter Description Condition VIL Input Voltage, Low LVCMOS VIH Input Voltage, High Peak-Peak Input Voltage LVCMOS LVPECL Common Mode Range1 LVPECL VPP VCMR VOL VOH 2 Output Voltage, Low 2 IOL= 15mA Min Typ Max Unit 0.7 V 1.7 250 VDD+0.3 1000 V mV 1.0 VDD- 0.6 - V 0.6 V Output Voltage, High IOH= –15mA IIL Input Current, Low3 VIL= VSS -100 µA IIH Input Current, High3 VIL= VDD 100 µA IDDA PLL Supply Current AVDD only 10 mA IDDQ Quiescent Supply Current All VDD pins except AVDD 7 mA IDD Dynamic Supply Current CIN Input Pin Capacitance ZOUT 1.8 V 5 Outputs loaded @ 100 MHz 180 Outputs loaded @ 200 MHz 210 mA 4 Output Impedance 14 18 pF 22 Ω Note: 1 VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input swing is within the VPP (DC) specification. 2.Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series terminated transmission lines. 3.Inputs have pull-up or pull-down resistors that affect the input current. DC Electrical Specifications (VDD = 3.3V ± 5%, TA = -40°C to +85°C) Parameter Description Condition VIL Input Voltage, Low LVCMOS VIH Input Voltage, High Peak-Peak Input Voltage LVCMOS LVPECL Common Mode Range1 LVPECL VPP VCMR IOH= –24 mA IIL Input Current, Low3 VIL= VSS IIH Input Current, High3 VIL= VDD IDDA PLL Supply Current AVDD only IDDQ Quiescent Supply Current All VDD pins except AVDD Input Pin Capacitance ZOUT Output Impedance V 2.0 250 VDD+0.3 1000 V mV 1.0 VDD– 0.6 V 0.30 Output Voltage, High2 Unit 0.8 0.55 VOH CIN Max IOL= 12 mA Output Voltage, Low2 Dynamic Supply Current Typ IOL= 24 mA VOL IDD Min 2.4 V –100 5 Outputs loaded @ 100 MHz 270 Outputs loaded @ 200 MHz 300 15 µA 100 µA 10 mA 7 mA mA 4 12 V pF 18 Ω Note: 1 VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input swing is within the VPP (DC) specification. 2.Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series terminated transmission lines. 3.Inputs have pull-up or pull-down resistors that affect the input current. 2.5V or 3.3V, 200MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 5 of 13 PCS5I9351 November 2006 rev 0.3 AC Electrical Specifications (VDD = 2.5V ± 5%, TA = -40°C to +85°C) 1 Parameter fVCO fin frefDC VPP Description Condition VCO Frequency Input Frequency Min Typ Max Unit MHz 200 380 ÷2 Feedback 100 190 ÷4 Feedback 50 95 ÷8 Feedback 25 47.5 Bypass mode (PLL_EN = 0) 0 200 25 75 % Input Duty Cycle MHz Peak-Peak Input Voltage LVPECL 500 1000 mV Common Mode Range2 LVPECL 1.2 VDD- 0.6 V tr, tf TCLK Input Rise/FallTime 0.7V to 1.7V 1.0 nS fMAX Maximum Output Frequency VCMR ÷2 Output 100 190 ÷4 Output 50 95 ÷8 Output 25 47.5 fMAX < 100MHz 47.5 52.5 fMAX > 100MHz 45 55 0.1 1.0 DC Output Duty Cycle tr, tf Output Rise/Fall times 0.6V to 1.8V t(φ) Propagation Delay (static phase offset) TCLK to FB_IN -100 100 PCLK to FB_IN -100 100 tsk(O) MHz % nS pS Output-to-Output Skew 150 pS tPLZ, HZ Output Disable Time 10 nS tPZL, ZH Output Enable Time 10 nS BW PLL Closed Loop Bandwidth (–3dB) tJIT(CC) Cycle-to-Cycle Jitter tJIT(PER) Period Jitter tJIT(φ) I/O Phase Jitter tLOCK Maximum PLL Lock Time ÷2 Feedback 2.2 ÷4 Feedback 0.85 ÷8 Feedback 0.6 MHz Same frequency 150 Multiple frequencies 250 Same frequency 100 Multiple frequencies 175 175 pS pS pS 1 mS Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ). 2.5V or 3.3V, 200MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 6 of 13 PCS5I9351 November 2006 rev 0.3 AC Electrical Specifications (VDD = 3.3V ± 5%, TA = -40°C to +85°C)1 Parameter fVCO fin Description Condition VCO Frequency Input Frequency Min Typ Max Unit MHz 200 500 ÷2 Feedback 100 200 ÷4 Feedback 50 125 ÷8 Feedback Bypass mode (PLL_EN = 0) 25 62.5 0 200 MHz frefDC Input Duty Cycle 25 75 % VPP Peak-Peak Input Voltage LVPECL 500 1000 mV Common Mode Range2 LVPECL 1.2 VDD- 0.9 V 1.0 nS ÷2 Output 100 200 ÷4 Output 50 125 ÷8 Output 25 62.5 fMAX < 100MHz 47.5 52.5 fMAX > 100MHz 45 55 0.1 1.0 VCMR tr, tf fMAX TCLK Input Rise/FallTime Maximum Output Frequency 0.8V to 2.0V DC Output Duty Cycle tr, tf Output Rise/Fall times 0.8V to 2.4V t(φ) Propagation Delay (static phase offset) TCLK to FB_IN, same VDD -100 100 PCLK to FB_IN, same VDD -100 100 Output-to-Output Skew Banks at same voltage 150 Banks at different voltages tsk(O) MHz % nS pS pS tsk(B) Bank-to-Bank Skew 350 pS tPLZ, HZ Output Disable Time 10 nS tPZL, ZH Output Enable Time 10 nS BW PLL Closed Loop Bandwidth (–3dB) tJIT(CC) Cycle-to-Cycle Jitter tJIT(PER) Period Jitter tJIT(φ) I/O Phase Jitter tLOCK Maximum PLL Lock Time ÷2 Feedback 2.2 ÷4 Feedback 0.85 ÷8 Feedback 0.6 MHz Same frequency 150 Multiple frequencies 250 Same frequency 100 Multiple frequencies 150 I/O same VDD 175 pS pS pS 1 mS Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ). 2.5V or 3.3V, 200MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 7 of 13 PCS5I9351 November 2006 rev 0.3 Zo = 50 ohm Zo = 50 ohm Pulse Generator Z = 50 ohm RT = 50 ohm RT = 50 ohm VTT VTT Figure 1. LVCMOS_CLK AC Test Reference for VDD = 3.3V / 2.5V Zo = 50 ohm Zo = 50 ohm Differential Pulse Generator Z = 50 ohm Zo = 50 ohm RT = 50 ohm RT = 50 ohm VTT VTT Figure 2. PECL_CLK AC Test Reference for VDD = 3.3V / 2.5V PECL_CLK VPP PECL_CLK VCMR VDD VDD ÷2 FB_IN t(Ø) GND Figure 3. LVPECL Propagation Delay (t(f)). Static phase offset 2.5V or 3.3V, 200MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 8 of 13 PCS5I9351 November 2006 rev 0.3 VDD LVCMOS_CCLK VDD ÷2 GND VDD FB_IN VDD ÷2 GND t(Ø) Figure 4. LVCMOS Propagation delay t(Ø), static phase offset VDD VDD ÷2 GND tP T0 DC= (tP ÷T0 Χ 100%) Figure 5. Output Duty Cycle (DC) VDD VDD ÷2 GND VDD VDD ÷2 tSK(O) GND Figure 6. Output–to–Output Skew tSK(O) 2.5V or 3.3V, 200MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 9 of 13 PCS5I9351 November 2006 rev 0.3 Package Diagram 32-lead TQFP SECTION A-A Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.0472 … 1.2 A1 0.0020 0.0059 0.05 0.15 A2 0.0374 0.0413 0.95 1.05 D 0.3465 0.3622 8.8 9.2 D1 0.2717 0.2795 6.9 7.1 E 0.3465 0.3622 8.8 9.2 E1 0.2717 0.2795 6.9 7.1 L 0.0177 0.0295 0.45 0.75 L1 0.03937 REF 1.00 REF T 0.0035 0.0079 0.09 0.2 T1 0.0038 0.0062 0.097 0.157 b 0.0118 0.0177 0.30 0.45 b1 0.0118 0.0157 0.30 0.40 R0 0.0031 0.0079 0.08 0.2 a 0° 7° 0° 7° e 0.031 BASE 0.8 BASE 2.5V or 3.3V, 200MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 13 PCS5I9351 November 2006 rev 0.3 32-lead LQFP SECTION A-A Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.0630 … 1.6 A1 0.0020 0.0059 0.05 0.15 A2 0.0531 0.0571 1.35 1.45 D 0.3465 0.3622 8.8 9.2 D1 0.2717 0.2795 6.9 7.1 E 0.3465 0.3622 8.8 9.2 E1 0.2717 0.2795 6.9 7.1 L 0.0177 0.0295 0.45 0.75 L1 0.03937 REF 1.00 REF T 0.0035 0.0079 0.09 0.2 T1 0.0038 0.0062 0.097 0.157 b 0.0118 0.0177 0.30 0.45 b1 0.0118 0.0157 0.30 0.40 R0 0.0031 0.0079 0.08 0.20 e a 0.031 BASE 0° 7° 0.8 BASE 0° 7° 2.5V or 3.3V, 200MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 13 PCS5I9351 November 2006 rev 0.3 Ordering Information Part Number Marking Package Type Temperature PCS5I9351G-32-ET PCS5I9351G 32-pin TQFP, Green Industrial PCS5I9351G-32-LT PCS5I9351G 32-pin LQFP –Tape and Reel, Green Industrial Device Ordering Information P C S 5 I 9 3 5 1 G - 3 2 - L T R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 2.5V or 3.3V, 200MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 13 PCS5I9351 November 2006 rev 0.3 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS5I9351 Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. 2.5V or 3.3V, 200MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 13 of 13