ASM5I9352 July 2005 rev 0.2 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer Features The ASM5I9352 features an LVCMOS reference clock input and provides 11 outputs partitioned in 3 banks of 5, 4, Output frequency range: 25MHz to 200MHz Output frequency range: 16.67MHz to 200MHz Input frequency range: 16.67MHz to 200MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs 1:3. Each LVCMOS compatible output can drive 50Ω series ± 2% max Output duty cycle variation or parallel terminated transmission lines. For series 11 Clock outputs: Drive up to 22 clock lines terminated transmission lines, each output can drive one or LVCMOS reference clock input two traces giving the device an effective fanout of 1:22. 125-pS max output-output skew PLL bypass mode Spread Aware to run between 200 MHz to 500 MHz. This allows a wide Output enable/disable range of output frequencies from 16.67 MHz to 200 MHz. Pin compatible with MPC9352 and MPC952 For normal operation, the external feedback input, FB_IN, Industrial temperature range: –40°C to +85°C is connected to one of the outputs. The internal VCO is 32-Pin 1.0mm TQFP & LQFP Packages running at multiples of the input reference clock set by the and 2 outputs. Bank A divides the VCO output by 4 or 6 while Bank B divides by 4 and 2 and Bank C divides by 2 and 4 per SEL(A:C) settings, see Table 2. These dividers allow output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and The PLL is ensured stable given that the VCO is configured TM feedback divider, see Table 1. Functional Description The ASM5I9352 is a low voltage high performance 200MHz PLL-based zero delay buffer designed for high speed clock distribution applications. When PLL_EN# is HIGH, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. ASM5I9352 July 2005 rev 0.2 Block Diagram PLL_EN# REFCLK FB_IN VCO 200-500MHz Phase Detector +4/ +6 +2 QA0 QA1 LPF QA2 VCO_SEL QA3 QA4 SELA +4/ +2 QB0 QB1 QB2 QB3 SELB +2/ +4 SELC MR/OE# QC0 QC1 VDDQB QB2 QB3 VSS VSS QC0 QC1 VDDQC Pin Configuration 32 31 30 29 28 27 26 25 VCO_SEL 1 24 VSS SELC 2 23 QB1 SELB 3 22 QB0 SELA 4 21 VDDQB ASM5I9352 20 VDDQA 6 19 QA4 AVSS 7 18 QA3 FB_IN 8 17 VSS VDDQA QA2 QA1 VSS QA0 10 11 12 13 14 15 16 VDD 9 AVDD 5 PLL_EN# MR/OE# REFCLK 2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 2 of 12 ASM5I9352 July 2005 rev 0.2 Pin Configuration1 Pin 6 12, 14, 15, 18, 19 22, 23, 26, 27 30, 31 Name I/O Type Description REFCLK I, PD LVCMOS Reference clock input. QA(0:4) O LVCMOS Clock output bank A. QB(0:3) O LVCMOS Clock output bank B. QC(0,1) O LVCMOS Clock output bank C. I, PD LVCMOS Feedback clock input. Connect to an output for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. 8 FB_IN 1 VCO_SEL I, PD LVCMOS VCO divider select input. See Table 2. 5 MR/OE# I, PD LVCMOS Master reset/output enable/disable input. See Table 2. 9 PLL_EN# I, PD LVCMOS PLL enable/disable input. See Table 2. 2, 3, 4 16, 20 SEL(A:C) VDDQA I, PD Supply LVCMOS VDD Frequency select input, Bank (A:C). See Table 2. 2.5V or 3.3V power supply for bank A output clocks2,3. 21, 25 VDDQB Supply VDD 2.5V or 3.3V power supply for bank B output clocks.2,3 32 10 VDDQC AVDD Supply Supply VDD VDD 2.5V or 3.3V power supply for bank C output clocks. 2,3 2.5V or 3.3V power supply for PLL. 2,3 11 VDD Supply VDD 2.5V or 3.3V power supply for core and inputs. 2,3 7 AVSS Supply Ground Analog ground. 13, 17, 24, 28, 29 VSS Supply Ground Common ground. Note: 1. PD = Internal pull-down. 2.A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3.AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output supply pins. 2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 3 of 12 ASM5I9352 July 2005 rev 0.2 Table 1: Frequency Table VCO_SEL Feedback Output Divider VCO Input Frequency Range (AVDD = 3.3V) Input Frequency Range (AVDD = 2.5V) 0 ÷2 Input Clock * 2 100 MHz to 200 MHz 100 MHz to 200 MHz 0 ÷4 Input Clock * 4 50 MHz to 125 MHz 50 MHz to 100 MHz 0 ÷6 Input Clock * 6 33.33 MHz to 83.33 MHz 33.33 MHz to 66.67 MHz 1 ÷2 Input Clock * 4 50 MHz to 125 MHz 50 MHz to 100 MHz 1 ÷4 Input Clock * 8 25 MHz to 62.5 MHz 25 MHz to 50 MHz 1 ÷6 Input Clock * 12 16.67 MHz to 41.67 MHz 16.67 MHz to 33.33 MHz Table 2: Function Table Control Default 0 1 VCO_SEL 0 VCO VCO ÷ 2 PLL_EN# 0 PLL enabled. The VCO output connects to the output dividers Bypass mode, PLL disabled. The input clock connects to the output dividers MR/OE# 0 Outputs enabled Outputs disabled (three-state), VCO running at its minimum frequency SELA 0 QA = VCO÷4 QA = VCO÷6 SELB 0 QB = VCO ÷4 QB = VCO÷2 SELC 0 QC = VCO÷2 QC = VCO÷4 Absolute Maximum Ratings Parameter Description Condition Min Max Unit VDD DC Supply Voltage –0.3 5.5 V VDD DC Operating Voltage Functional 2.375 3.465 V VIN DC Input Voltage Relative to VSS –0.3 VDD+ 0.3 V VOUT DC Output Voltage Relative to VSS –0.3 VDD+ 0.3 V VTT Output termination Voltage VDD ÷2 V LU Latch Up Immunity RPS Power Supply Ripple Ripple Frequency < 100 kHz 150 mVp-p TS Temperature, Storage Non Functional –65 +150 °C TA Temperature, Operating Ambient Functional –40 +85 °C TJ Temperature, Junction Functional 155 °C ØJC Dissipation, Junction to Case Functional 42 °C/W ØJA Dissipation, Junction to Ambient Functional 105 °C/W ESDH ESD Protection (Human Body Model) FIT Failure in Time Functional 200 mA 2000 Manufacturing test Volts 10 ppm Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 4 of 12 ASM5I9352 July 2005 rev 0.2 DC Electrical Specifications (VDD = 2.5V ± 5%, TA = -40°C to +85°C) Parameter Description VIL Input Voltage, Low VIH Input Voltage, High Condition Min Typ LVCMOS LVCMOS 1 1.7 Max Unit 0.7 V VDD+ 0.3 V VOL Output Voltage, Low IOL= 15 mA VOH Output Voltage, High1 IOH= –15 mA 0.6 V IIL Input Current, Low VIL= VSS –10 µA IIH Input Current, High2 VIL= VDD 100 µA IDDA PLL Supply Current AVDD only 5 10 mA IDDQ Quiescent Supply Current All VDD pins except AVDD 3 5 mA IDD Dynamic Supply Current CIN Input Pin Capacitance ZOUT Output Impedance 1.8 V 170 mA 4 pF 17 – 20 Ω Note:1.Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 Ω series terminated transmission lines. 2.Inputs have pull-down resistors that affect the input current. DC Electrical Specifications (VDD = 3.3V ± 5%, TA = -40°C to +85°C) Parameter Description Condition VIL Input Voltage, Low LVCMOS VIH Input Voltage, High LVCMOS VOL Output Voltage, Low1 VOH Output Voltage, High1 IOH= –24 mA IIL Input Current, Low VIL= VSS 2 Min Typ 2.0 Max Unit 0.8 V VDD + 0.3 V IOL= 24 mA 0.55 IOL= 12 mA 0.30 2.4 V V –10 µA IIH Input Current, High VIL= VDD 100 µA IDDA PLL Supply Current AVDD only 5 10 mA IDDQ Quiescent Supply Current All VDD pins except AVDD 3 5 mA IDD Dynamic Supply Current CIN Input Pin Capacitance ZOUT Output Impedance 240 mA 4 pF 14 – 17 Ω Note:1.Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 Ω series terminated transmission lines. 2.Inputs have pull-down resistors that affect the input current. 2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 5 of 12 ASM5I9352 July 2005 rev 0.2 AC Electrical Specifications (VDD = 2.5V ± 5%, TA = -40°C to +85°C) 1 Parameter Description Condition fVCO fin VCO Frequency Input Frequency Input Duty Cycle tr, tf TCLK Input Rise/FallTime fMAX Maximum Output Frequency Typ Max Unit MHz 200 400 ÷2 Feedback 100 200 ÷4 Feedback 50 100 ÷6 Feedback 33.33 66.67 ÷8 Feedback 25 50 16.67 33.33 0 200 25 75 % 1.0 nS ÷2 Output 100 200 ÷4 Output 50 100 ÷6 Output 33.33 66.67 ÷12 Feedback Bypass mode (PLL_EN# = 1) frefDC Min 0.7V to 1.7V ÷8 Output 25 50 16.67 33.33 fMAX< 100 MHz 47 53 fMAX > 100 MHz 44 56 0.1 1.0 nS -100 100 pS pS Output Duty Cycle tr, tf Output Rise/Fall times 0.6V to 1.8V t(φ) Propagation Delay (static phase offset) TCLK to FB_IN, same VDD, does not include jitter tsk(O) Output-to-Output Skew Skew within Bank 125 Banks at same voltage, same frequency 175 Banks at same voltage, different frequency 225 Bank-to-Bank Skew MHz ÷12 Output DC tsk(B) MHz % pS tPLZ, HZ Output Disable Time 8 nS tPZL, ZH Output Enable Time 10 nS PLL Closed Loop Bandwidth (3dB) BW tJIT(CC) Cycle-to-Cycle Jitter tJIT(PER) Period Jitter tJIT(φ) I/O Phase Jitter tLOCK Maximum PLL Lock Time ÷2 Feedback 2 ÷4 Feedback 1 - 1.5 ÷6 Feedback 0.6 ÷8 Feedback 0.75 ÷12 Feedback 0.5 MHz Same frequency 100 Multiple frequencies 300 Same frequency 100 Multiple frequencies 150 VCO < 300 MHz 150 VCO > 300 MHz 100 pS pS pS 1 mS . Note:1 AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested. 2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 6 of 12 ASM5I9352 July 2005 rev 0.2 AC Electrical Specifications (VDD = 3.3V ± 5%, TA = -40°C to +85°C)1 Parameter fVCO fin Description Condition Max Unit 200 500 MHz ÷2 Feedback 100 200 ÷4 Feedback 50 125 ÷6 Feedback 33.33 83.33 ÷8 Feedback 25 62.5 ÷12 Feedback 16.67 41.67 0 200 VCO Frequency Input Frequency Bypass mode (PLL_EN# = 1) frefDC Input Duty Cycle tr, tf TCLK Input Rise/FallTime Typ 25 0.8V to 2.0V ÷2 Output fMAX Min Maximum Output Frequency 100 75 % 1.0 nS 200 ÷4 Output 50 125 ÷6 Output 33.33 83.33 25 62.5 ÷12 Output 16.67 41.67 fMAX< 100 MHz 48 52 fMAX > 100 MHz 44 56 0.1 1.0 nS –100 200 pS pS Output Duty Cycle tr, tf Output Rise/Fall times 0.55V to 2.4V t(φ) Propagation Delay (static phase offset) TCLK to FB_IN, same VDD, does not include jitter tsk(O) Output-to-Output Skew Skew within each Bank 125 Banks at same voltage, same frequency 175 Banks at same voltage, different frequency 235 Banks at different voltage 425 Bank-to-Bank Skew MHz ÷8 Output DC tsk(B) MHz % pS tPLZ, HZ Output Disable Time 8 nS tPZL, ZH Output Enable Time 10 nS PLL Closed Loop Bandwidth (-3dB) BW tJIT(CC) Cycle-to-Cycle Jitter tJIT(PER) Period Jitter tJIT(φ) I/O Phase Jitter tLOCK Maximum PLL Lock Time ÷2 Feedback 2 ÷4 Feedback 1 – 1.5 ÷6 Feedback 0.6 ÷8 Feedback 0.75 ÷12 Feedback 0.5 MHz Same frequency 100 Multiple frequencies 275 Same frequency 100 Multiple frequencies 150 VCO < 300 MHz 150 VCO > 300 MHz 100 pS pS pS 1 mS . Note:1 AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested. 2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 7 of 12 ASM5I9352 July 2005 rev 0.2 Zo = 50 ohm Zo = 50 ohm Pulse Generator Z = 50 ohm RT = 50 ohm RT = 50 ohm VTT VTT Figure 1. AC Test Reference for VDD = 3.3V / 2.5V VDD LVCMOS_CLK VDD/2 GND VDD FB_IN VDD/2 t(φ) GND Figure 2. LVCMOS Propagation Delay t(φ), Static Phase Offset VDD LVCMOS_CLK VDD/2 GND tP T0 DC = tP / T0 x 100% Figure 3. Output Duty Cycle (DC) VDD VDD/2 GND VDD VDD/2 tSK(0) GND Figure 4. Output-to-Output Skew , tsk(O) 2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 8 of 12 ASM5I9352 July 2005 rev 0.2 Package Diagram 32-lead TQFP Package SECTION A-A Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.0472 … 1.2 A1 0.0020 0.0059 0.05 0.15 A2 0.0374 0.0413 0.95 1.05 D 0.3465 0.3622 8.8 9.2 D1 0.2717 0.2795 6.9 7.1 E 0.3465 0.3622 8.8 9.2 E1 0.2717 0.2795 6.9 7.1 L 0.0177 0.0295 0.45 0.75 L1 0.03937 REF 1.00 REF T 0.0035 0.0079 0.09 0.2 T1 0.0038 0.0062 0.097 0.157 b 0.0118 0.0177 0.30 0.45 b1 0.0118 0.0157 0.30 0.40 R0 0.0031 0.0079 0.08 0.2 a 0° 7° 0° 7° e 0.031 BASE 0.8 BASE 2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 9 of 12 ASM5I9352 July 2005 rev 0.2 32-lead LQFP Package SECTION A-A Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.0630 … 1.6 A1 0.0020 0.0059 0.05 0.15 A2 0.0531 0.0571 1.35 1.45 D 0.3465 0.3622 8.8 9.2 D1 0.2717 0.2795 6.9 7.1 E 0.3465 0.3622 8.8 9.2 E1 0.2717 0.2795 6.9 7.1 L 0.0177 0.0295 0.45 0.75 L1 0.03937 REF 1.00 REF T 0.0035 0.0079 0.09 0.2 T1 0.0038 0.0062 0.097 0.157 b 0.0118 0.0177 0.30 0.45 b1 0.0118 0.0157 0.30 0.40 R0 0.0031 0.0079 0.08 0.20 e a 0.031 BASE 0° 7° 0.8 BASE 0° 7° 2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 12 ASM5I9352 July 2005 rev 0.2 Ordering Information Part Number Marking Package Type Temperature ASM5I9352-32-ET ASM5I9352 32-pin TQFP Industrial ASM5I9352-32-LT ASM5I9352 32-pin LQFP –Tape and Reel Industrial ASM5I9352G-32-ET ASM5I9352G 32-pin TQFP, Green Industrial ASM5I9352G-32-LT ASM5I9352G 32-pin LQFP –Tape and Reel, Green Industrial Device Ordering Information A S M 5 I 9 3 5 2 F - 3 2 - L T R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 12 ASM5I9352 July 2005 rev 0.2 Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM5I9352 Document Version: 0.2 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2003 Alliance Semiconductor Corporation. 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Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. 2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 12