ALSC ASM5I9350G-32-LT

ASM5I9350
July 2005
rev 0.2
3.3V 1:10 LVCMOS PLL Clock Generator
Features
The ASM5I9350 features Xtal and LVCMOS reference
clock inputs and provides nine outputs partitioned in four
ƒ
Output frequency range: 25 MHz to 200 MHz
ƒ
Input frequency range: 6.25 MHz to 31.25 MHz
ƒ
2.5V or 3.3V operation
ƒ
Split 2.5V/3.3V outputs
ƒ
± 2.5% max Output duty cycle variation
LVCMOS compatible output can drive 50Ω series or
ƒ
Nine Clock outputs: Drive up to 18 clock lines
parallel
ƒ
Two reference clock inputs: Xtal or LVCMOS
terminated transmission lines, each output can drive one or
ƒ
150pS max output-output skew
two traces giving the device an effective fanout of 1:18.
ƒ
Phase-locked loop (PLL) bypass mode
The PLL is ensured stable given that the VCO is configured
ƒ
‘SpreadTrak’
to run between 200MHz to 500MHz. This allows a wide
ƒ
Output enable/disable
range of output frequencies from 25MHz to 200MHz. The
ƒ
Pin-compatible with MPC9350 and CY29350.
internal VCO is running at multiples of the input reference
ƒ
Industrial temperature range: –40°C to +85°C
ƒ
32-pin 1.0mm TQFP & LQFP Packages
banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO
output by 2 or 4 while the other banks divide by 4 or 8 per
SEL(A:D) settings, see Table 2. These dividers allow
output to input ratios of 16:1, 8:1, 4:1, and 2:1. Each
terminated
transmission
lines.
For
series
clock set by the feedback divider, see Table 1.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
Functional Description
The
ASM5I9350
is
a
does not apply.
low-voltage
high-performance
200MHz PLL-based clock driver designed for high speed
clock distribution applications.
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
ASM5I9350
July 2005
rev 0.2
Block Diagram
SELA
PLL_EN
REF_SEL
TCLK
XIN
XOUT
VCO
200-500MHz
Phase
Detector
osc
+2/
+4
QA
+4/
+8
QB
+4/
+8
QC0
QC1
LPF
+16/+32
FB_SEL
SELB
SELC
+4/
+8
SELD
QD0
QD1
QD2
QD3
QD4
VSS
QB
VDDQB
QA
TCLK
VSS
REF_SEL
Pin Configuration
PLL_EN
OE#
32 31 30 29 28 27 26 25
AVDD
1
24
QC0
FB_SEL
2
23
VDDQC
SELA
3
22
QC1
SELB
4
21
VSS
SELC
5
20
QD0
SELD
6
19
VDDQD
AVSS
7
18
QD1
17
VSS
XOUT
ASM5I9350
8
QD2
VDDQD
QD3
VSS
QD4
OE#
VDD
XIN
9 10 11 12 13 14 15 16
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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ASM5I9350
July 2005
rev 0.2
Pin Discription1
Pin #
Pin Name
I/O
Type
Description
8
XOUT
O
Analog
Oscillator Output. Connect to a crystal.
9
XIN
I
Analog
Oscillator Input. Connect to a crystal.
30
TCLK
I, PD
LVCMOS
LVCMOS/LVTTL reference clock input
28
QA
O
LVCMOS
Clock output bank A
26
QB
O
LVCMOS
Clock output bank B
22, 24
12, 14, 16,
18, 20
2
QC(1:0)
O
LVCMOS
Clock output bank C
QD(4:0)
O
LVCMOS
Clock output bank D
FB_SEL
I, PD
LVCMOS
Internal Feedback Select Input. See Table 1.
10
OE#
I, PD
LVCMOS
Output enable/disable input. See Table 2.
31
PLL_EN
I, PU
LVCMOS
PLL enable/disable input. See Table 2.
32
REF_SEL
I, PD
LVCMOS
Reference select input. See Table 2.
3, 4, 5, 6
27
23
15, 19
SEL(A:D)
VDDQB
VDDQC
VDDQD
I, PD
Supply
Supply
Supply
LVCMOS
VDD
VDD
VDD
Frequency select input, Bank (A:D). See Table 2.
2.5V or 3.3V Power supply for bank B output clock2,3
2.5V or 3.3V Power supply for bank C output clocks2,3
2.5V or 3.3V Power supply for bank D output clocks2,3
1
AVDD
Supply
VDD
2.5V or 3.3V Power supply for PLL2,3
11
VDD
Supply
VDD
2.5V or 3.3V Power supply for core, inputs, and bank A
2,3
output clock
7
13, 17, 21,
25, 29
AVSS
Supply
Ground
Analog ground
VSS
Supply
Ground
Common ground
Note: 1. PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins
their high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output
power supply pins.
Table 1: Frequency Table
FB_SEL
Feedback Divider
VCO
Input Frequency
Range (AVDD = 3.3V)
Input Frequency
Range (AVDD = 2.5V)
0
÷32
Input Clock * 32
6.25 MHz to 15.625 MHz
6.25 MHz to 11.875 MHz
1
÷16
Input Clock * 16
12.5 MHz to 31.25 MHz
12.5 MHz to 23.75 MHz
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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ASM5I9350
July 2005
rev 0.2
Table 2: Function Table
Control
Default
0
1
REF_SEL
0
TCLK
PLL_EN
1
PLL enabled. The VCO output connects to
the output dividers
OE#
0
Xtal
Bypass mode, PLL disabled. The
input clock connects to the output
dividers
Outputs enabled
FB_SEL
0
Feedback divider ÷32
Feedback divider ÷16
SELA
0
÷2 (Bank A)
÷ 4 (Bank A)
SELB
0
÷4 (Bank B)
÷ 8 (Bank B)
SELC
0
÷4 (Bank C)
÷ 8 (Bank C)
SELD
0
÷4 (Bank D)
÷ 8 (Bank D)
Outputs disabled (three-state)
Absolute Maximum Ratings
Parameter
Description
Condition
Min
Max
Unit
VDD
DC Supply Voltage
–0.3
5.5
V
VDD
DC Operating Voltage
Functional
2.375
3.465
V
VIN
DC Input Voltage
Relative to VSS
–0.3
VDD+ 0.3
V
VOUT
DC Output Voltage
Relative to VSS
–0.3
VDD+ 0.3
V
VTT
Output termination Voltage
VDD ÷2
V
150
mVp-p
LU
Latch Up Immunity
Functional
RPS
Power Supply Ripple
Ripple Frequency < 100 kHz
200
mA
TS
Temperature, Storage
Non-functional
–65
+150
°C
TA
Temperature, Operating Ambient
Functional
–40
+85
°C
TJ
Temperature, Junction
Functional
+150
°C
ØJC
Dissipation, Junction to Case
Functional
42
°C/W
ØJA
Dissipation, Junction to Ambient
Functional
105
°C/W
ESDH
ESD Protection (Human Body Model)
FIT
Failure in Time
2000
Manufacturing test
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
Volts
10
ppm
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ASM5I9350
July 2005
rev 0.2
DC Electrical Specifications (VCC = 2.5V ± 5%, TA = -40°C to +85°C)
Parameter
Description
Condition
Min
Typ
Max
Unit
VIL
Input Voltage, Low
LVCMOS
-
-
0.7
V
VIH
Input Voltage, High
LVCMOS
1.7
-
VDD+0.3
V
VOL
Output Voltage, Low1
IOL= 15mA
-
-
0.6
V
VOH
Output Voltage, High1
IOH= –15mA
1.8
-
-
V
2
IIL
Input Current, Low
VIL= VSS
-
-
-100
µA
IIH
Input Current, High2
VIL= VDD
-
-
100
µA
IDDA
PLL Supply Current
AVDD only
-
5
10
mA
IDDQ
Quiescent Supply Current
All VDD pins except AVDD
-
-
7
mA
Outputs loaded @ 100 MHz
-
180
-
Outputs loaded @ 200 MHz
-
210
-
-
4
-
pF
14
18
22
Ω
IDD
Dynamic Supply Current
CIN
Input Pin Capacitance
ZOUT
Output Impedance
mA
Note: 1. Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series terminated
transmission lines.
2. Inputs have pull-up or pull-down resistors that affect the input current.
DC Electrical Specifications (VCC = 3.3V ± 5%, TA = -40°C to +85°C)
Parameter
Description
VIL
Input Voltage, Low
VIH
Input Voltage, High
Condition
1
Min
Typ
Max
Unit
LVCMOS
-
-
0.8
V
LVCMOS
V
2.0
-
VDD+0.3
IOL= 24 mA
-
-
0.55
IOL= 12 mA
-
-
0.30
VOL
Output Voltage, Low
VOH
Output Voltage, High1
IOH= –24 mA
IIL
Input Current, Low2
VIL= VSS
IIH
Input Current, High2
VIL= VDD
IDDA
PLL Supply Current
AVDD only
IDDQ
Quiescent Supply Current
IDD
Dynamic Supply Current
CIN
Input Pin Capacitance
ZOUT
Output Impedance
V
2.4
-
-
V
-
-
–100
µA
-
-
100
µA
-
5
10
mA
mA
All VDD pins except AVDD
-
-
7
Outputs loaded @ 100 MHz
-
270
-
Outputs loaded @ 200 MHz
-
300
-
-
4
-
pF
12
15
18
Ω
mA
Note: 1. Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series terminated
transmission lines.
2. Inputs have pull-up or pull-down resistors that affect the input current.
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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ASM5I9350
July 2005
rev 0.2
AC Electrical Specifications (VCC = 2.5V ± 5%, TA = -40°C to +85°C)1
Parameter
fVCO
fin
Description
Condition
Min
Typ
Max
Unit
200
-
380
MHz
÷16 Feedback
12.5
-
23.75
÷32 Feedback
Bypass mode
(PLL_EN = 0)
6.25
-
11.87
0
-
200
VCO Frequency
Input Frequency
MHz
fXTAL
Crystal Oscillator Frequency
10
-
23.75
MHz
frefDC
Input Duty Cycle
25
-
75
%
tr, tf
TCLK Input Rise/FallTime
-
-
1.0
nS
÷2 Output
100
-
190
fMAX
Maximum Output Frequency
÷4 Output
50
-
95
÷8 Output
25
-
47.5
0.7V to 1.7V
MHz
fMAX< 100 MHz
47.5
-
52.5
fMAX > 100 MHz
45
-
55
0.6V to 1.8V
0.1
-
1.0
Output-to-Output Skew
-
-
150
pS
Output Disable Time
-
-
10
nS
tPZL, ZH
Output Enable Time
-
-
10
nS
BW
PLL Closed Loop Bandwidth (-3dB)
÷16 Feedback
-
0.7 - 0.9
-
÷32 Feedback
-
0.6 - 0.8
-
tJIT(CC)
Cycle-to-Cycle Jitter
Same frequency
-
-
150
Multiple frequencies
-
-
250
tJIT(PER)
Period Jitter
Same frequency
-
-
100
Multiple frequencies
-
-
175
tLOCK
Maximum PLL Lock Time
-
-
1
DC
Output Duty Cycle
tr, tf
Output Rise/Fall times
tsk(O)
tPLZ, HZ
%
nS
MHz
pS
pS
mS
Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested.
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
6 of 12
ASM5I9350
July 2005
rev 0.2
AC Electrical Specifications (VCC = 3.3V ± 5%, TA = -40°C to +85°C)1
Parameter
fVCO
fin
Description
Condition
VCO Frequency
Input Frequency
Min
Typ
Max
Unit
MHz
200
-
500
÷16 Feedback
12.5
-
31.25
÷32 Feedback
Bypass mode
(PLL_EN = 0)
6.25
-
15.625
0
-
200
MHz
fXTAL
Crystal Oscillator Frequency
10
-
25
MHz
frefDC
Input Duty Cycle
25
-
75
%
tr, tf
TCLK Input Rise/FallTime
nS
fMAX
Maximum Output Frequency
DC
Output Duty Cycle
tr, tf
Output Rise/Fall times
-
-
1.0
÷2 Output
0.8V to 2.0V
100
-
200
÷4 Output
50
-
125
÷8 Output
25
-
62.5
fMAX < 100 MHz
47.5
-
52.5
fMAX > 100 MHz
45
-
55
0.8V to 2.4V
0.1
-
1.0
nS
MHz
%
tsk(O)
Output-to-Output Skew
Banks at same voltage
-
-
150
pS
tsk(B)
Bank-to-Bank Skew
Banks at different voltages
-
-
350
pS
tPLZ, HZ
Output Disable Time
-
-
10
nS
tPZL, ZH
Output Enable Time
-
-
10
nS
BW
PLL Closed Loop Bandwidth (–3dB)
÷16 Feedback
-
0.7 – 0.9
-
÷32 Feedback
-
0.6 – 0.8
-
tJIT(CC)
Cycle-to-Cycle Jitter
Same frequency
-
-
150
Multiple frequencies
-
-
250
tJIT(PER)
Period Jitter
Same frequency
-
-
100
Multiple frequencies
-
-
150
tLOCK
Maximum PLL Lock Time
-
-
1
MHz
pS
pS
mS
Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested.
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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ASM5I9350
July 2005
rev 0.2
Zo = 50 ohm
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 1. AC Test Reference for VDD = 3.3V / 2.5V
VDD
LVCMOS_CLK
VDD/2
GND
tP
DC =
tP
× 100%
To
T0
Figure 2. Output Duty Cycle (DC)
VDD
VDD/2
GND
VDD
VDD/2
tSK(0)
GND
Figure 3. Output-to-Output Skew , tsk(O)
Table 3. Suggested Oscillator Crystal Parameters
Characteristic
Frequency Tolerance
Frequency Temperature
Stability
Aging
Load Capacitance
Effective Series Resistance
Symbol
Conditions
TC
Min
Typ
Max
Units
-
-
±100
ppm
TS
(TA–10 +60C)
-
-
±00
ppm
TA
First three years @ 25°C
-
-
5
ppm/yr
CL
Crystal’s rated load
RESR
-
20
-
pF
-
40
80
Ω
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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ASM5I9350
July 2005
rev 0.2
Package Diagram
32-lead TQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
….
0.0472
…
1.2
A1
0.0020
0.0059
0.05
0.15
A2
0.0374
0.0413
0.95
1.05
D
0.3465
0.3622
8.8
9.2
D1
0.2717
0.2795
6.9
7.1
E
0.3465
0.3622
8.8
9.2
E1
0.2717
0.2795
6.9
7.1
L
0.0177
0.0295
0.45
0.75
L1
0.03937 REF
1.00 REF
T
0.0035
0.0079
0.09
0.2
T1
0.0038
0.0062
0.097
0.157
b
0.0118
0.0177
0.30
0.45
b1
0.0118
0.0157
0.30
0.40
R0
0.0031
0.0079
0.08
0.2
a
0°
7°
0°
7°
e
0.031 BASE
0.8 BASE
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
9 of 12
ASM5I9350
July 2005
rev 0.2
32-lead LQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
….
0.0630
…
1.6
A1
0.0020
0.0059
0.05
0.15
A2
0.0531
0.0571
1.35
1.45
D
0.3465
0.3622
8.8
9.2
D1
0.2717
0.2795
6.9
7.1
E
0.3465
0.3622
8.8
9.2
E1
0.2717
0.2795
6.9
7.1
L
0.0177
0.0295
0.45
0.75
L1
0.03937 REF
1.00 REF
T
0.0035
0.0079
0.09
0.2
T1
0.0038
0.0062
0.097
0.157
b
0.0118
0.0177
0.30
0.45
b1
0.0118
0.0157
0.30
0.40
R0
0.0031
0.0079
0.08
0.20
e
a
0.031 BASE
0°
7°
0.8 BASE
0°
7°
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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ASM5I9350
July 2005
rev 0.2
Ordering Information
Part Number
Marking
Package Type
Temperature
ASM5I9350-32-ET
ASM5I9350
32-pin TQFP
Industrial
ASM5I9350-32-LT
ASM5I9350
32-pin LQFP –Tape and Reel
Industrial
ASM5I9350G-32-ET
ASM5I9350G
32-pin TQFP, Green
Industrial
ASM5I9350G-32-LT
ASM5I9350G
32-pin LQFP –Tape and Reel, Green
Industrial
Device Ordering Information
A S M
5 I 9 3 5 0
F - 3 2 - L T
R = Tape & reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
11 of 12
ASM5I9350
July 2005
rev 0.2
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM5I9350
Document Version: 0.2
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance).
All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of
products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any
other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant
injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer
assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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