PYRAMID P4C168

P4C168, P4C169, P4C170
ULTRA HIGH SPEED 4K x 4
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
Fully TTL Compatible, Common I/O Ports
High Speed (Equal Access and Cycle Times)
– 12/15/20/25/35ns (Commercial)
– 20/25/35/45/55/70ns (P4C168 Military)
Three Options
– P4C168 Low Power Standby Mode
– P4C169 Fast Chip Select Control
– P4C170 Fast Chip Select, Output Enable
Controls
Low Power Operation (Commercial)
– 715 mW Active
– 193 mW Standby (TTL Input) P4C168
– 83 mW Standby (CMOS Input) P4C168
Standard Pinout (JEDEC Approved)
– P4C168: 20-pin DIP, SOJ, LCC, SOIC,
CERPACK, and Flat Pack
– P4C169: 20-pin DIP and SOIC
– P4C170: 22-pin DIP
Single 5V±10% Power Supply
DESCRIPTION
The P4C168, P4C169 and P4C170 are a family of
16,384-bit ultra high-speed static RAMs organized as 4K
x 4. All three devices have common input/output ports.The
P4C168 enters the standby mode when the chip enable
(CE) control goes HIGH; with CMOS input levels, power
consumption is only 83mW in this mode. Both the P4C169
and the P4C170 offer a fast chip select access time that
is only 67% of the address access time. In addition, the
P4C170 includes an output enable (OE) control to eliminate data bus contention. The RAMs operate from a
single 5V ± 10% tolerance power supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption to a low 715
mW active, 193 mW standby.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
The P4C168 and P4C169 are available in 20-pin (P4C170
in 22-pin) 300 mil DIP packages providing excellent
board level densities. The P4C168 is also available in 20pin 300 mil SOIC, SOJ, CERPACK, and Flat Pack
packages.
The P4C169 is also available in a 20-pin 300 mil SOIC
package.
P4C168
P4C169
DIP (P2, C6, D2)
DIP (P2)
SOIC (S2)
SOIC (S2)
SOJ (J2)
CERPACK (F2)
SOLDER SEAL FLAT PACK (FS-2)
P4C170
DIP (P3)
Document # SRAM107 REV A
1
Revised October 2005
P4C168, P4C169, P4C170
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
VCC
Power Supply Pin with
Respect to GND
– 0.5 to +7
V
VTERM
Terminal Voltage with
Respect to GND
(up to 7.0V)
– 0.5 to
VCC +0.5
V
TA
Operating Temperature
–55 to +125
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Value
Unit
TBIAS
Temperature Under
Bias
– 55 to +125
°C
TSTG
Storage Temperature
– 65 to +150
°C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
50
mA
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
Grade(2)
Ambient Temp
Gnd
VCC
Commercial
0°C to 70°C
0V
5.0V ± 10%
–55°C to +125°C
0V
5.0V ± 10%
Military
Symbol
Symbol
Parameter
Conditions Typ. Unit
CIN
Input Capacitance
VIN = 0V
5
pF
COUT
Output Capacitance VOUT= 0V
7
pF
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
P4C168/169/170
Test Conditions
Min
Max
Unit
VIH
Input High Voltage
2.2
VCC +0.5
V
VIL
Input Low Voltage
–0.5(3)
0.8
V
VHC
CMOS Input High Voltage
VCC –0.2
VCC +0.5
V
VLC
CMOS Input Low Voltage
–0.5(3)
0.2
V
VCD
Input Clamp Diode Voltage
VCC = Min., IIN = –18 mA
–1.2
V
VOL
Output Low Voltage
(TTL Load)
IOL = +8 mA, VCC = Min.
0.4
V
VOLC
Output Low Voltage
(CMOS Load)
IOLC = +100 µA, VCC = Min.
0.2
V
VOH
Output High Voltage
(TTL Load)
IOH = –4 mA, VCC = Min.
VOHC
Output High Voltage
(CMOS Load)
IOHC = –100 µA, VCC = Min.
ILI
Input Leakage Current
VCC = Max., VIN = GND to VCC
ILO
Output Leakage Current
VCC = Max., CS = VIH,
VOUT = GND to VCC
ICC
Dynamic Operating
Current
Standby Power Supply
Current (TTL Input Levels)
P4C168 only
Standby Power
Supply Current
(CMOS Input Levels)
P4C168 only
ISB
ISB1
Document # SRAM107 REV A
2.4
V
VCC –0.2
V
–10
–5
–10
–5
+10
+5
+10
+5
µA
VCC = Max., f = Max., Outputs Open
___
130
mA
CE ≥ VIH, VCC = Max., f = Max.,
Outputs Open
___
35
mA
CE ≥ VHC, VCC = Max., f = 0,
Outputs Open
VIN ≤ VLC or VIN ≥ VHC
___
15
mA
Mil.
Comm’l
Mil.
Comm’l
µA
Page 2 of 15
P4C168, P4C169, P4C170
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym
Parameter
-12
-15
-20
-25
-35
Min Max Min Max Min Max Min Max Min Max
Unit
tRC
Read Cycle Time
tAA
Address Access Time
12
15
20
25
35
ns
Chip Enable Access Time
12
15
20
25
35
ns
Chip Select Access Time
8
9
12
15
20
ns
tAC §
tAC
‡
tOH
tLZ
‡
tHZ †
tOE
†
tOLZ †
tOHZ
†
12
15
20
25
35
ns
Output Hold from Address Change
2
2
2
2
2
ns
Chip Enable to Output in Low Z
2
2
2
2
2
ns
Chip Disable to Output in High Z
7
8
9
10
15
ns
Output Enable to Data Valid
8
10
12
15
15
ns
Output Enable to Output in Low Z
0
Output Disable to Output in High Z
0
6
0
7
0
0
9
11
ns
15
ns
tRCS
Read Command Setup Time
0
0
0
0
0
ns
tRCH
Read Command Hold Time
0
0
0
0
0
ns
tPU §
Chip Enable to Power Up Time
0
0
0
0
0
ns
tPD
§
Chip Disable to Power Down Time
12
15
20
25
35
ns
AC CHARACTERISTICS—READ CYCLE (CONTINUED)
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym
Parameter
-45
-55
-70
Min Max Min Max Min Max
Unit
t RC
Read Cycle Time
t AA
Address Access Time
45
55
70
ns
t AC §
Chip Enable Access Time
45
55
70
ns
t OH
Output Hold from Address Change
2
2
2
ns
t LZ ‡
Chip Enable to Output in Low Z
2
2
2
ns
t HZ
†
45
Chip Disable to Output in High Z
55
25
70
25
ns
30
ns
t RCS
Read Command Setup Time
0
0
0
ns
t RCH
Read Command Hold Time
0
0
0
ns
t PU §
Chip Enable to Power Up Time
0
0
0
ns
t PD
§
Chip Disable to Power Down Time
45
55
70
ns
§ P4C168 only
† P4C170 only
‡ Chip Select/Deselect for P4C169 and P4C170
Document # SRAM107 REV A
Page 3 of 15
P4C168, P4C169, P4C170
TIMING WAVEFORM OF READ CYCLE NO. 1 (ADDRESS CONTROLLED)(5,6)
Notes:
5. WE is HIGH for READ cycle.
6. CE/CS and OE are LOW for READ cycle.
CE
CS CONTROLLED)(5,7)
TIMING WAVEFORM OF READ CYCLE NO. 2 (CE
CE/CS
OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 3—P4C170 ONLY (OE
Notes:
7. ADDRESS must be valid prior to, or coincident with CE/CS transition
low. For Fast CS, tAA must still be met.
8. Transition is measured ±200mV from steady state voltage prior to
change, with loading as specified in Figure 1.
Document # SRAM107 REV A
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Page 4 of 15
P4C168, P4C169, P4C170
AC ELECTRICAL CHARACTERISTICS - WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym
Parameter
-12
-15
-20
-25
-35
Min Max Min Max Min Max Min Max Min Max
Unit
tWC
Write Cycle Time
12
15
18
20
30
ns
tcw
Chip Enable Time to End of Write
12
15
18
20
30
ns
tAW
Address Valid to End of Write
12
15
18
20
30
ns
tAS
Address Set-up Time
0
0
0
0
0
ns
tWP
Write Pulse Width
12
15
18
20
30
ns
tAH
Address Hold Time
0
0
0
0
0
ns
tDW
Data Valid to End of Write
7
8
10
10
15
ns
tDH
Data Hold Time
0
0
0
0
0
ns
tWZ
Write Enable to Output in High Z
tOW
Output Active from End of Write
4
0
5
0
6
0
7
0
13
0
ns
ns
AC ELECTRICAL CHARACTERISTICS - WRITE CYCLE (CONTINUED)
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym
Parameter
-45
-55
-70
Min Max Min Max Min Max
Unit
tWC
Write Cycle Time
45
55
70
ns
tcw
Chip Enable Time to End of Write
40
50
60
ns
tAW
Address Valid to End of Write
40
50
60
ns
tAS
Address Set-up Time
0
0
0
ns
tWP
Write Pulse Width
40
50
60
ns
tAH
Address Hold Time
0
0
0
ns
tDW
Data Valid to End of Write
20
20
25
ns
tDH
Data Hold Time
3
3
3
ns
tWZ
Write Enable to Output in High Z
tOW
Output Active from End of Write
Document # SRAM107 REV A
20
0
25
0
30
0
ns
ns
Page 5 of 15
P4C168, P4C169, P4C170
WE CONTROLLED)(10)
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE
Notes:
10. CE/CS and WE must be LOW for WRITE cycle.
11. If CE/CS goes HIGH simultaneously with WE HIGH, the output
remains in a high impedance state.
12. Write Cycle Time is measured from the last valid address to the first
transitioning address.
CE
CS CONTROLLED)(10)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE
CE/CS
TRUTH TABLES
P4C168 (P4C169)
P4C170
CE
WE
OE
Output
Deselect
H
X
X
High Z
DOUT
Read
L
H
L
DOUT
High Z
Output Inhibit
L
H
H
High Z
Write
L
L
X
High Z
Mode
CE (CS
CS
CS)
WE
Output
Standby (Deselect)
H
X
High Z
Read
L
H
Write
L
L
Document # SRAM107 REV A
Mode
Page 6 of 15
P4C168, P4C169, P4C170
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
Figure 2. Thevenin Equivalent
Figure 1. Output Load
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C168, P4C169 AND P4C170
care must be taken when testing these devices; an inadequate setup
can cause a normal functioning part to be rejected as faulty. Long highinductance leads that cause supply bounce must be avoided by bringing
the VCC and ground planes directly up to the contactor fingers. A high
frequency capacitor of 0.01 µF is also required between VCC and ground.
To avoid signal reflections, proper termination must be used; for
example, a 50Ω test environment should be terminated into a 50Ω load
with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω
resistor must be used in series with DOUT to match 166Ω (Thevenin
Resistance).
LCC PIN CONFIGURATION
LCC (L9)
Document # SRAM107 REV A
Page 7 of 15
P4C168, P4C169, P4C170
ORDERING INFORMATION
SELECTION GUIDE
The P4C168, P4C169 and P4C170 are available in the following temperature, speed and package options.
Temperature
Range
Commercial
Temperature
Package
Speed
12
15
20
25
35
Plastic DIP
-12PC
-15PC
-20PC
-25PC
N/A
Plastic SOIC†
-12SC
-15SC
-20SC
-25SC
N/A
Plastic SOJ††
-12JC
-15JC
-20JC
-25JC
N/A
N/A
-15LM
-20LM
-25LM
-35LM
LCC
Military
Temperature
CERDIP
N/A
-15DM
-20DM
-25DM
-35DM
Side Brazed DIP
N/A
-15CM
-20CM
-25CM
-35CM
(P4C168 only)
CERPACK
N/A
-15FM
-20FM
-25FM
-35FM
Solder Seal Flat Pack
N/A
-15FSM
-20FSM
-25FSM
-35FSM
LCC
N/A
-15LMB
-20LMB
-25LMB
-35LMB
Military
Processed*
CERDIP
N/A
-15DMB
-20DMB
-25DMB
-35DMB
Side Brazed DIP
N/A
-15CMB
-20CMB
-25CMB
-35CMB
(P4C168 only)
CERPACK
N/A
-15FMB
-20FMB
-25FMB
-35FMB
Solder Seal Flat Pack
N/A
-15FSMB
-20FSMB
-25FSMB
-35FSMB
† P4C168 and P4C169 only.
†† P4C168
* Military temperature range with MIL-STD-883, Class B processing.
N/A = Not available
Document # SRAM107 REV A
Page 8 of 15
P4C168, P4C169, P4C170
SELECTION GUIDE (CONTINUED)
Temperature
Range
Package
Speed
45
55
70
LCC
-45LM
-55LM
-70LM
Military
Temperature
CERDIP
-45DM
-55DM
-70DM
Side Brazed DIP
-45CM
-55CM
-70CM
(P4C168 only)
CERPACK
-45FM
-55FM
-70FM
Solder Seal Flat Pack
-45FSM
-55FSM
-70FSM
LCC
-45LMB
-55LMB
-70LMB
Military
Processed*
CERDIP
-45DMB
-55DMB
-70DMB
Side Brazed DIP
-45CMB
-55CMB
-70CMB
(P4C168 only)
CERPACK
-45FMB
-55FMB
-70FMB
-55FSMB
-55FSMB
-70FSMB
Solder Seal Flat Pack
* Military temperature range with MIL-STD-883, Class B processing.
Document # SRAM107 REV A
Page 9 of 15
P4C168, P4C169, P4C170
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
S2
Pkg #
# Pins
Symbol
A
b
c
D
E
e
k
L
Q
S
S1
C6
SIDE BRAZED DUAL IN-LINE PACKAGE
20 (300 mil)
Min
Max
0.200
0.014
0.026
0.045
0.065
0.008
0.018
1.060
0.220
0.310
0.300 BSC
0.100 BSC
0.125
0.200
0.015
0.070
0.005
0.005
-
F2
CERPACK CERAMIC FLAT PACKAGE
20
Min
Max
0.060
0.090
0.015
0.022
0.004
0.009
0.530
0.305
0.355
0.050 BSC
0.005
0.018
0.250
0.370
0.026
0.045
0.085
0.005
-
Document # SRAM107 REV A
Page 10 of 15
P4C168, P4C169, P4C170
Pkg #
# Pins
Symbol
A
b
b1
c
c1
D
E
E1
E2
E3
e
k
L
Q
S1
M
N
Pkg #
# Pins
Symbol
A
A1
b
C
D
e
E
E1
E2
Q
FS-2
SOLDER SEAL FLAT PACKAGE
20
Min
Max
0.045
0.115
0.015
0.022
0.015
0.019
0.004
0.009
0.004
0.006
0.540
0.245
0.300
0.330
0.130
0.030
0.050 BSC
0.008
0.015
0.250
0.370
0.026
0.045
0.000
0.0015
20
J2
SOJ SMALL OUTLINE IC PACKAGE
20 (300 mil)
Min
Max
0.120
0.140
0.080
0.014
0.020
0.008
0.013
0.496
0.512
0.050 BSC
0.335
0.347
0.292
0.300
0.267 BSC
0.025
-
Document # SRAM107 REV A
Page 11 of 15
P4C168, P4C169, P4C170
Pkg #
# Pins
Symbol
A
A1
B1
D
D1
D2
D3
E
E1
E2
E3
e
h
j
L
L1
L2
ND
NE
Pkg #
# Pins
Symbol
A
A1
b
b2
C
D
E1
E
e
eB
L
α
L9
RECTANGULAR LEADLESS CHIP CARRIER
20
Min
Max
0.060
0.075
0.050
0.066
0.022
0.028
0.280
0.305
0.150 BSC
0.075 BSC
0.305
0.420
0.440
0.250 BSC
0.125 BSC
0.440
0.050 BSC
0.020 REF
0.010 REF
0.045
0.055
0.045
0.055
0.075
0.098
4
6
P2
PLASTIC DUAL IN-LINE PACKAGE (P4C168, P4C169)
20 (300 mil)
Min
Max
0.210
0.015
0.014
0.022
0.045
0.070
0.008
0.014
0.980
1.060
0.240
0.280
0.300
0.325
0.100 BSC
0.430
0.115
0.150
0°
15°
Document # SRAM107 REV A
Page 12 of 15
P4C168, P4C169, P4C170
Pkg #
# Pins
Symbol
A
A1
b
b2
C
D
E1
E
e
eB
L
α
Pkg #
# Pins
Symbol
A
A1
b2
C
D
e
E
H
h
L
α
P3
PLASTIC DUAL IN-LINE PACKAGE (P4C170)
22 (300 Mil)
Min
Max
0.210
0.015
0.014
0.022
0.045
0.070
0.008
0.014
1.145
1.165
0.240
0.280
0.300
0.325
0.100 BSC
0.430
0.115
0.150
0°
15°
S2
SOIC/SOP SMALL OUTLINE IC PACKAGE
20 (300 mil)
Min
Max
0.093
0.104
0.004
0.012
0.013
0.020
0.009
0.012
0.496
0.511
0.050 BSC
0.291
0.299
0.394
0.419
0.010
0.029
0.016
0.050
0°
8°
Document # SRAM107 REV A
Page 13 of 15
P4C168, P4C169, P4C170
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
α
D2
CERDIP DUAL IN-LINE PACKAGE
20 (300 mil)
Min
Max
0.200
0.014
0.026
0.045
0.065
0.008
0.018
1.060
0.220
0.310
0.300 BSC
0.100 BSC
0.125
0.200
0.015
0.070
0.005
0°
15°
Document # SRAM107 REV A
Page 14 of 15
P4C168, P4C169, P4C170
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM107
P4C168, P4C169, P4C170 ULTRA HIGH SPEED 4K x 4 STATIC CMOS RAMS
REV.
ISSUE
DATE
ORIG. OF
CHANGE
OR
1997
DAB
New Data Sheet
A
Oct-05
JDB
Change logo to Pyramid
Document # SRAM107 REV A
DESCRIPTION OF CHANGE
Page 15 of 15