PYRAMID P3C1011-25TI

P3C1011
HIGH SPEED 128K x 16 (2 MEG)
STATIC CMOS RAM
FEATURES
2.0V Data Retention
Easy Memory Expansion Using CE and OE
Inputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast tOE
Automatic Power Down when deselected
Packages
—44-Pin SOJ, TSOP II
High Speed (Equal Access and Cycle Times)
— 10/12/15/20 ns (Commercial)
— 12/15/20 ns (Industrial)
— 20/25/35 (Military)
Low Power
— 360 mW (max.)
Single 3.3V ± 0.3V Power Supply
DESCRIPTION
The P3C1011 is a 131,072 words by 16 bits high-speed
CMOS static RAM. The CMOS memory requires no
clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM operates from a single 3.3V ± 0.3V tolerance power
supply.
accomplished by device selection (CE and output enabling (OE) while write enable (WE) remains HIGH. By
presenting the address under these conditions, the data
in the addressed memory location is presented on the
data input/output pins. The input/output pins stay in the
HIGH Z state when either CE or OE is HIGH or WE is
LOW.
Access times as fast as 10 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The P3C1011
is a member of a family of PACE RAM™ products offering fast access times.
For both reading and writing, the Byte Enable control lines
(BLE for I/O0-7 and BHE for I/O8-15) allow for the selection
of only 8 of the 16 I/O lines if desired. When a Byte
Enable control line is HIGH, the corresponding I/Os are
active.
The P3C1011 device provides asynchronous operation
with matching access and cycle times. Memory locations are specified on address pins A0 to A17. Reading is
Package options for the P3C1011 include 44-pin SOJ and
TSOP packages.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
1519B
SOJ
TSOP II
Document # SRAM131 REV OR
Revised March 2006
1
P3C1011
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
Power Supply Pin with
Respect to GND
–0.5 to +4.6
V
V TERM
Terminal Voltage with
Respect to GND
–0.5 to
VCC +0.5
V
TA
Operating Temperature
–55 to +125
°C
V CC
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade(2)
Industrial
Commercial
Military
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under
Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
20
mA
CAPACITANCES(4)
VCC = 3.3V, TA = 25°C, f = 1.0MHz
Ambient
Temperature
VSS
VCC
Symbol
Parameter
–40°C to +85°C
0V
3.3V ± 0.3V
CIN
Input Capacitance
0°C to +70°C
0V
3.3V ± 0.3V
COUT
-55°C to +125°C
0V
3.3V ± 0.3V
I/O Capacitance
Conditions Typ. Unit
VIN = 0V
8
pF
VOUT = 0V
8
pF
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
Symbol
Parameter
Test Conditions
P3C1011
Unit
Min
Max
VCC +0.3 V
2.0
VIH
Input High Voltage
VIL
Input Low Voltage
VOL
Output Low Voltage
(TTL Load)
IOL = +8 mA, VCC = Min.
VOH
Output High Voltage
(TTL Load)
IOH = –4 mA, VCC = Min.
2.4
VCC = Max.
-1
+1
µA
-1
+1
µA
___
40
mA
___
10
mA
ILI
Input Leakage Current
–0.3(3)
Output Leakage Current
V
0.4
V
V
VIN = GND to VCC
VCC = Max.,
ILO
0.8
CE = VIH,
VOUT = GND to VCC
CE ≥ VIH
ISB
Standby Power Supply
VCC= Max,
Current (TTL Input Levels) f = Max., Outputs Open
VIN ≥ VIH or VIN ≤ VIL
CE ≥ VCC - 0.2V
ISB1
Standby Power Supply
Current
(CMOS Input Levels)
VCC= Max,
f = 0, Outputs Open
VIN ≥ VCC - 0.3V or
VIN ≤ 0.3V
Document # SRAM131 REV OR
Page 2 of 10
P3C1011
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
ICC
Parameter
Temperature
Range
Commercial
Dynamic Operating Current* Industrial
Military
–10
90
–12
–15
85
N/A
N/A
Unit
80
–20
75
–25
70
–35
65
95
90
85
80
75
mA
N/A
N/A
100
95
90
mA
mA
*VCC = 3.6V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 3.3V ± 0.3V, All Temperature Ranges)(2)
Sym.
-12
-10
Parameter
-15
-25
-20
-35
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
t RC
Read Cycle Time
tAA
Address Access Time
10
12
15
20
25
35
ns
tAC
Chip Enable Access Time
10
12
15
20
25
35
ns
t OH
Output Hold from Address Change
3
3
3
3
3
3
ns
tLZ
Chip Enable to Output in Low Z
3
3
3
3
3
3
ns
t HZ
Chip Disable to Output in High Z
5
6
7
8
10
12
ns
tOE
Output Enable Low to Data Valid
5
6
7
8
10
12
ns
tOLZ
Output Enable Low to Low Z
t OHZ
Output Enable High to High Z
tPU
Chip Enable to Power Up Time
tPD
Chip Disable to Power Down Time
10
12
15
20
25
35
ns
tBE
Byte Enable to Data Valid
5
6
7
8
10
12
ns
tLZBE
Byte Enable to Low Z
tHZBE
Byte Disable to High Z
Document # SRAM131 REV OR
12
10
0
15
0
5
0
6
0
0
0
0
6
7
0
10
ns
ns
0
0
8
12
10
0
0
0
ns
0
0
8
7
ns
35
25
0
0
0
6
20
ns
12
ns
Page 3 of 10
P3C1011
TIMING WAVEFORM OF READ CYCLE NO. 1
OE CONTROLLED)(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 2 (OE
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL not more negative than –2.0V and
VIH ≤ VCC + 0.5V, are permissible for pulse widths up to 20 ns.
Document # SRAM131 REV OR
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE transition LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Page 4 of 10
P3C1011
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 3.3V ± 0.3V, All Temperature Ranges)(2)
Sym.
Parameter
-12
-10
-15
-20
-25
-35
Min Max Min Max Min Max Min Max Min Max Min Max
Unit
tWC
Write Cycle Time
10
12
15
20
25
35
ns
tCW
Chip Enable Time to End of
Write
7
8
10
10
12
15
ns
tAW
Address Valid to End of Write
7
8
10
10
12
15
ns
tAS
0
0
0
0
0
0
ns
tWP
Address Set-up Time to Write
Start
Write Pulse Width
7
8
10
10
12
15
ns
tAH
Address Hold Time
0
0
0
0
0
0
ns
tDW
Data Valid to End of Write
5
6
7
8
10
12
ns
t DH
Data Hold Time
0
0
0
0
0
0
ns
tWZ
Write Enable to Output in High Z
tOW
Output Active from End of Write
3
3
3
3
3
3
ns
tLZWE
WE High to Low Z
3
3
3
3
3
3
ns
tBW
Byte Enable to End of Write
7
8
10
10
12
15
ns
5
6
7
8
12
10
ns
CE CONTROLLED)
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (CE
Document # SRAM131 REV OR
Page 5 of 10
P3C1011
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (BLE
BLE OR BHE CONTROLLED)
WE CONTROLLED, OE LOW)
TIMING WAVEFORM OF WRITE CYCLE NO. 3 (WE
Document # SRAM131 REV OR
Page 6 of 10
P3C1011
AC TEST CONDITIONS
Input Pulse Levels
VSS to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P3C1041, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads
that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
frequency capacitor is also required between VCC and ground. To avoid
signal reflections, proper termination must be used; for example, a 50Ω
test environment should be terminated into a 50Ω load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116Ω resistor must
be used in series with DOUT to match 166Ω (Thevenin Resistance).
TRUTH TABLE
Mode
CE
O E W E BLE BHE
I/O0 - I/O7
I/O8 - I/O15
Power
Power-down
Read All Bits
H
L
X
L
X
H
X
L
X
L
High Z
DOUT
High Z
DOUT
Standby
Active
Read Lower Bits Only
L
L
H
L
H
DOUT
High Z
Active
Read Upper Bits Only
L
L
H
H
L
High Z
DOUT
Active
Write All Bits
L
X
L
L
L
DIN
DIN
Active
Write Lower Bits Only
L
X
L
L
H
DIN
High Z
Active
Write Upper Bits Only
L
X
L
H
L
High Z
DIN
Active
Selected, Outputs Disabled
L
H
H
X
X
High Z
High Z
Active
Document # SRAM131 REV OR
Page 7 of 10
P3C1011
ORDERING INFORMATION
Document # SRAM131 REV OR
Page 8 of 10
P3C1011
Pkg #
# Pins
Symbol
A
A1
b
C
D
e
E
E1
E2
Q
Pkg #
# Pins
Symbol
A
A2
b
D
E
e
HD
J8
SOJ SMALL OUTLINE IC PACKAGE
44 (400 mil)
Min
Max
0.128
0.148
0.082
0.013
0.023
0.007
0.013
1.120
1.130
0.050 BSC
0.435
0.445
0.395
0.405
0.370 BSC
0.025
-
T2
TSOP II THIN SMALL OUTLINE PACKAGE
44
Min
Max
0.039
0.047
0.033
0.045
0.012
0.016
0.396
0.404
0.721
0.729
0.0315 BSC
0.462
0.470
Document # SRAM131 REV OR
Page 9 of 10
P3C1011
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM131
P3C1011 HIGH SPEED 128K x 16 (4 MEG) STATIC CMOS RAM
REV.
ISSUE
DATE
ORIG. OF
CHANGE
OR
Mar-06
JDB
Document # SRAM131 REV OR
DESCRIPTION OF CHANGE
New Data Sheet
Page 10 of 10