RT9262/A Preliminary High Efficiency, Low Supply Current, Step-up DC/DC Converter General Description Features The RT9262/A is a compact, high efficient, step-up DC/DC converter with an adaptive current mode PWM control loop, providing a stable and high efficient operation over a wide range of load currents. It operates in both continuous and discontinuous current modes in stable waveforms without external compensation. z The low start-up input voltage below 1V makes RT9262/A suitable for 1 to 4 battery cell applications providing up to 400mA output current. The 550KHz high switching rate minimized the size of external components. Besides, the 17µA low quiescent current together with high efficiency maintains long battery lifetime. z z z z z z z z z 1.0V Low Start-up Input Voltage High Supply Capability to Deliver 3.3V 100mA with 1V Input Voltage 17µA Quiescent (Switch-off) Supply Current 90% Efficiency 550KHz Fixed Switching Rate Providing Flexibility for Using Internal and External Power Switches Built-in 300mA LDO, also for the Zero-OutputCurrent Shutdown Mode (RT9262) Boost DC-DC Integrating LDO for Up-Down Regulation (RT9262) Built-in 0.86V Voltage Detector (RT9262A) 8-Pin SOP Package Applications The 1.8V to 5V output voltage is set with 2 external resistors. Both internal 2A switch and driver for driving external power devices (NMOS or NPN) are provided. A 300mA LDO is included in RT9262 to provide a secondary low noise output as well as an output current stop in the shutdown mode. Similarly, a 1.8V to 5V LDO output voltage can be set with 2 external resistors. For RT9262A, a low battery detector with 0.86V detection voltage is included. RT9262/A are provided in SOP-8 packages. z z z z z z PDA Portable Instrument Wireless Equipment DSC LCD Back Bias Circuit RF-Tags Pin Configurations Part Number RT9262CS (Plastic SOP-8) Ordering Information RT9262A Package type S : SOP-8 Operating temperature range C: Commercial standard A : Include low battery detector Default : Include LDO DS9262/A-04 August 2002 RT9262ACS (Plastic SOP-8) Pin Configurations TOP VIEW GND 1 8 CE EXT 2 7 LX LFB 3 6 VDD LDOO 4 5 FB TOP VIEW GND 1 8 CE EXT 2 7 LX LBO 3 6 VDD LBI 4 5 FB www.richtek.com 1 RT9262/A Preliminary Marking Information Part Number Marking RT9262CS RT9262CS RT9262ACS RT9262ACS Typical Application Circuit VIN 100µF 100pF VDD RT9262 CE R4 1.3M 3.3V VOUT1 D1 LX 1nF LFB + C3 10µF L DO O L1 4.7µH GND FB R3 680K R2 980K + 2.5V VOUT2 EXT R1 1.6M C2 1µF C1 100µF Fig. 1 RT9262 Typical Application for Portable Instruments below 400mA VIN 100µF 100pF VDD RT9262A LB O R4 R3 L BI EXT L1 4.7µH 3.3V VOUT1 D1 LX GND FB R2 980K C2 1µF + CE Low Battery Warning Output (Open Collector) R1 1.6M C1 100µF Fig. 2 RT9262A Typical Application for Portable Instruments below 400mA www.richtek.com 2 DS9262/A-04 August 2002 RT9262/A Preliminary VIN 100µF VDD RT9262 CE EXT L DO O 3.3V VOUT LFB L1 4.7µH R1 1.6M D1 LX GND FB + C3 10µF R2 980K C2 1µF + Chip Enable Input 100pF C1 100µF Fig. 3 Application Circuit with Zero-Output-Current Shutdown Mode Control VIN 100µF R1 100pF 1.6M VDD RT9262 LDOO 2.5V VOUT2 + C3 10µF R4 1.3M 1nF LFB LX Q1 NMOS EXT GND 3.3V VOUT1 D1 FB R3 680K R2 980K C2 1µF + CE L1 4.7µH C1 100µF Fig. 4 0.4A ~ 2A Output Current Application L1 5V VIN 10µH CE 2.5V VOUT2 R4 1.3M RT9262 L DO O 1nF LFB EXT Q1 NMOS LX GND R1 2.2M FB + 0.1µF R3 680K Rm 0.05 ~0.1Ω 15V VOUT1 R2 200K C2 1µF + VDD 100µF C3 10µF D1 C1 100µF Fig. 5 High Voltage Application (Rm should be added when IL > 100mA) DS9262/A-04 August 2002 www.richtek.com 3 RT9262/A Preliminary Pin Description Pin No. RT9262 RT9262A Pin Name Pin Function 1 1 GND Ground 2 2 EXT Output pin for driving external NMOS or NPN When driving an NPN, a resistor should be added for limiting base current. 3 -- LFB Feedback pin of the built-in LDO (Internal Vref = 0.86V) 4 -- LDOO Voltage output pin of the built-in LDO -- 3 LBO Drain output pin of the NMOS of the built-in low voltage detector This pin will be internally pulled low when the voltage at LBI pin drops to below 0.86V. -- 4 LBI Input pin of the built-in low voltage detector Trip point = 0.86V 5 5 FB Feedback input pin Internal reference voltage for the error amplifier is 1.25V. 6 6 VDD Input positive power pin of RT9262/A 7 7 LX Pin for switching 8 8 CE Chip enable RT9262/A gets into shutdown mode when CE pin set to low. Absolute Maximum Ratings Supply Voltage z LX Pin Switch Voltage z LDO Output Voltage z Other I/O Pin Voltages z LX Pin Switch Current z EXT Pin Driver Current z LBO Current z Power Dissipation, PD @ TA = 25°C SOP-8 • Package Thermal Resistance SOP-8, θJA z Operating Junction Temperature z Storage Temperature Range z www.richtek.com 4 -0.3V to 7V -0.3V to (VDD + 0.8V) -0.3V to (VDD + 0.3V) -0.3V to (VDD + 0.3V) 2.5A 30mA 30mA 0.625W 160°C/W 150°C -65°C ~ +150°C DS9262/A-04 August 2002 RT9262/A Preliminary Electrical Characteristics (VIN = 1.5V, VDD set to 3.3V, Load Current = 0, TA = 25°C, unless otherwise specified) Parameter Symbol Start-UP Voltage VST Test Conditions IL = 1mA Min Typ Max Units -- 0.98 1.05 V * V Operating VDD Range VDD Start-up to IDD1 > 250µA 0.8 -- 6.5 No Load Current I (VIN) INO LOAD VIN = 1.5V, VOUT = 3.3V -- 47 -- µA Switch-off Current I (VDD) ISWITCH OFF VIN = 6V -- 17 -- µA Shutdown Current I (VIN) IOFF CE Pin = 0V, VIN = 4.5V -- 0.1 1 µA Feedback Reference Voltage VREF Close Loop, VDD = 3.3V 1.225 1.25 1.275 V VREF Close Loop, VDD = 3.3V 0.843 0.86 0.877 V VDD = 3.3V 0.843 0.86 0.877 V Feedback Reference Voltage for LDO RT9262 LBI Pin Trip Point RT9262A Switching Rate FS VDD = 3.3V -- 550 -- KHz Maximum Duty DMAX VDD = 3.3V -- 92 -- % VDD = 3.3V -- 0.25 -- Ω VDD = 3.3V -- 2 -- A EXT ON Resistance to VDD VDD = 3.3V -- 40 -- Ω EXT ON Resistance to GND VDD = 3.3V -- 30 -- Ω LX ON Resistance Current Limit Setting ILIMIT Line Regulation ∆VLINE VIN = 1.5 ~ 2.5V, IL = 1mA -- 10 -- mV/V Load Regulation ∆VLOAD VIN = 2.5V, IL = 1 ~ 100mA -- 0.25 -- mV/mA VDD = 3.3V -- 1 1.5 Ω VDD = 3.3V, IL = 100mA -- 70 -- mV VDD = 3.3V -- 40 -- Ω VDD = 3.3V 0.2 0.8 1.4 V LDO PMOS ON Resistance RT9262 LDO Drop Out Voltage RT9262 LBO ON Resistance RT9262A VDROP CE Pin Trip Level Temperature Stability for FB, LFB, LBI TS Guaranteed by Design -- 50 -- ppm/°C Thermal Shutdown TSD Guaranteed by Design -- 165 -- °C Thermal Shutdown Hysterises ∆TSD Guaranteed by Design -- 10 -- °C * Note: The CE pin shall be tied to VDD pin and inhibit to act the ON/OFF state whenever the VDD pin voltage may reach to 5.5V or above. DS9262/A-04 August 2002 www.richtek.com 5 RT9262/A Preliminary Function Block Diagram VDD Q2 PMOS RT9262 _ 0.86V EXT + VDD LDOO LFB LX FB _ + VDD 1.25V Loop Control Circuit R2 VDD LBI LBO R1 Q3 Over Temp. NMOS Detector CE Q1 NMOS Shut Down GND RT9262A _ Q2 NMOS + EXT 0.86V LX + VDD 1.25V _ FB Loop Control Circuit R1 R2 CE www.richtek.com 6 Q3 Over Temp. NMOS Detector Q1 NMOS Shut Down GND DS9262/A-04 August 2002 RT9262/A Preliminary Typical Operating Charateristics Efficiency Efficiency VOUT= 5.0V; TA = 25°C VOUT = 3.3V ; TA = 25°C No Load Current No Load Current 140 90 TA = 25°C VOUT = 3.3V 80 TA = 25°C VOUT = 5.0V 120 70 100 IDD ( µ A) IDD ( µ A) 60 50 40 80 60 30 40 20 20 10 Refer to Application Circuit Fig.1 and Fig.2 0 Refer to Application Circuit Fig.1 and Fig.2 0 1 1.2 1.5 2 2.5 3 1 1.2 1.5 Input Voltage (V) 2 2.5 3 4 Input Voltage (V) Start Up Voltage Start Up Voltage 1.4 1.25 TA = 25°C 1.3 VOUT = 3.3V 1.20 TA = 25°C VOUT= 5.0V Input Voltage (V) Input Voltage (V) 1.15 1.2 1.1 1.0 1.10 1.05 1.00 0.95 0.90 0.9 0.85 Refer to Application Circuit Fig.1 and Fig.2 Refer to Application Circuit Fig.1 and Fig.2 0.8 0 20 40 60 80 ILOAD (mA) ILOAD (mA) in constant resistance load DS9262/A-04 August 2002 100 0.80 0 25 50 75 100 ILOAD (mA) ILOAD (mA) in constant resistance load www.richtek.com 7 RT9262/A Preliminary Application Note Output Voltage Setting Referring to application circuits Fig.1 to Fig.5, the output voltage of the switching regulator (VOUT1) can be set with Eq.1. The LDO output voltage (VOUT2 of RT9262) can be set with Eq.2. R1 VOUT1 = (1 + ) × 1.25 V Eq.1 R2 VOUT 2 = (1 + R4 ) × 0.86 V R3 Eq.2 And trip point of the low battery detector is 0.86V at LBI pin of RT9262A. Feedback Loop Design Referring to application circuits Fig.1 to Fig.5, The selection of R1, R2, R3, and R4 based on the tradeoff between quiescent current consumption and interference immunity is stated below: • Follow Eq.1 and Eq.2. • Higher R reduces the quiescent current (Path current = 1.25V/R2, and 0.86V/R3), however resistors beyond 5MΩ are not recommended. • Lower R gives better noise immunity, and is less sensitive to interference, layout parasitics, FB/LFB node leakage, and improper probing to FB/LFB pins. • A proper value of feed forward capacitor parallel with R1 (or R4) on Fig.1 to Fig.5 can improve the noise immunity of the feedback loops, especially in an improper layout. An empirical suggestion is around 100pF ~ 1nF for feedback resistors of MΩ, and 10nF ~ 0.1µF for feedback resistors of tens to hundreds KΩ. For applications without standby or suspend modes, lower values of R1 to R4 are preferred. For applications concerning the current consumption in standby or suspend modes, the higher values of R1 to R4 are needed. Such “high impedance feedback loops” are sensitive to any interference, which require careful layout and avoid any interference, e.g. probing to FB/LFB pins. www.richtek.com 8 PRECAUTION 1: Improper probing to FB or LFB pin will cause fluctuation at VOUT1 and VOUT2. It may damage RT9262/A and system chips because VOUT1 may drastically rise to an over-rated level due to unexpected interference or parasitics being added to FB pin. PRECAUTION 2: Disconnecting R1 or short circuit across R2 may also cause similar IC damage as described in precaution 1. PRECAUTION 3: When large R values were used in feedback loops, any leakage in FB/LFB node may also cause VOUT1 and VOUT2 voltage fluctuation, and IC damage. To be especially highlight here is when the air moisture frozen and re-melt on the circuit board may cause several µA leakage between IC or component pins. So, when large R values are used in feedback loops, post coating, or some other moisture-preventing processes are recommended. VOUT1 Prober Parasitics R1 FB Pin _ R2 Q + Layout Guide • A full GND plane without gap break. • VOUT1 to GND noise bypass – Short and wide connection for C2 to Pin1 and Pin6. • VIN to GND noise bypass – Add a 100µF capacitor close to L1 inductor, when VIN is not an idea voltage source. • Minimized FB/LFB node copper area and keep far away from noise sources. • Minimized parasitic capacitance connecting to LX and EXT nodes, which may cause additional switching loss. • The following diagram is an example of 2-layer board layout for application circuits Fig.1 to Fig.4. DS9262/A-04 August 2002 Preliminary RT9262/A First Layer RT9262/A Second Layer (Full GND Plane) DS9262/A-04 August 2002 www.richtek.com 9 RT9262/A Preliminary Package Information H A M J B F C D I Dimensions In Millimeters Symbol Dimensions In Inches Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.178 0.254 0.007 0.010 I 0.102 0.254 0.004 0.010 J 5.791 6.198 0.228 0.244 M 0.406 1.270 0.016 0.050 8–Lead SOP Plastic Package www.richtek.com 10 DS9262/A-04 August 2002 Preliminary DS9262/A-04 August 2002 RT9262/A www.richtek.com 11 RT9262/A Preliminary RICHTEK TECHNOLOGY CORP. RICHTEK TECHNOLOGY CORP. Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)89191466 Fax: (8862)89191465 Email: [email protected] www.richtek.com 12 DS9262/A-04 August 2002