Revised March 2005
74ABT573
Octal D-Type Latch with 3-STATE Outputs
General Description
Features
The ABT573 is an octal latch with buffered common Latch
Enable (LE) and buffered common Output Enable (OE)
inputs.
■ Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
This device is functionally identical to the ABT373 but has
broadside pinouts.
■ Functionally identical to ABT373
■ Useful as input or output port for microprocessors
■ 3-STATE outputs for bus interfacing
■ Output sink capability of 64 mA, source capability of
32 mA
■ Guaranteed output skew
■ Guaranteed multiple output switching specifications
■ Output switching specified for both 50 pF and 250 pF
loads
■ Guaranteed simultaneous switching, noise level and
dynamic threshold performance
■ Guaranteed latchup protection
■ High impedance glitch-free bus loading during entire
power up and power down
■ Nondestructive hot insertion capability
Ordering Code:
Order Number
Package
Package Description
Number
74ABT573CSC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ABT573CSCX_NL
(Note 1)
M20B
Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT573CSJ
74ABT573CMSA
MSA20
74ABT573CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ABT573CMTCX_NL
(Note 1)
MTC20
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ABT573CPC
N20A
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS011548
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74ABT573 Octal D-Type Latch with 3-STATE Outputs
January 1993
74ABT573
Connection Diagram
Functional Description
The ABT573 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the Dn inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Function Table
Pin Descriptions
Inputs
Pin Names
D0–D7
Data Inputs
LE
Latch Enable Input (Active HIGH)
OE
O0–O7
Outputs
Descriptions
3-STATE Output Enable Input (Active LOW)
3-STATE Latch Outputs
OE
LE
D
O
L
H
H
H
L
H
L
L
L
L
X
O0
H
X
X
Z
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
O0 Value stored from previous clock cycle
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Recommended Operating
Conditions
65qC to 150qC
55qC to 125qC
55qC to 150qC
0.5V to 7.0V
0.5V to 7.0V
30 mA to 5.0 mA
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 3)
Input Current (Note 3)
40qC to 85qC
4.5V to 5.5V
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate ('V/'t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Voltage Applied to Any Output
in the Disabled or
0.5V to 5.5V
0.5V to VCC
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Twice the rated IOL (mA)
500 mA
DC Latchup Source Current
Over Voltage Latchup (I/O)
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
10V
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Units
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
1.2
V
VOH
Output HIGH Voltage
2.0
2.5
2.0
VOL
Output LOW Voltage
IIH
Input HIGH Current
0.55
1
1
IBVI
Input HIGH Current
7
Breakdown Test
IIL
VCC
V
1
Input LOW Current
1
Conditions
Recognized HIGH Signal
Recognized LOW Signal
Min
V
Min
V
Min
PA
Max
PA
Max
PA
Max
V
0.0
IIN
18 mA
IOH
3 mA
IOH
32 mA
IOL
64 mA
VIN
2.7V (Note 5)
VIN
VCC
VIN
7.0V
VIN
0.5V (Note 5)
VIN
0.0V
IID
1.9 PA
VID
Input Leakage Test
IOZH
Output Leakage Current
10
PA
0 5.5V VOUT
2.7V; OE
2.0V
IOZL
Output Leakage Current
10
PA
0 5.5V VOUT
0.5V; OE
2.0V
IOS
Output Short-Circuit Current
275
mA
Max
VOUT
0.0V
4.75
All Other Pins Grounded
100
ICEX
Output HIGH Leakage Current
50
PA
Max
VOUT
VCC
IZZ
Bus Drainage Test
100
PA
0.0
VOUT
5.5V; All Others GND
ICCH
Power Supply Current
50
PA
Max
All Outputs HIGH
ICCL
Power Supply Current
30
mA
Max
All Outputs LOW
ICCZ
Power Supply Current
50
PA
Max
OE
VCC
All Others at VCC or GND
ICCT
Additional ICC/Input
Outputs Enabled
2.5
mA
Outputs 3-STATE
2.5
mA
Outputs 3-STATE
2.5
mA
VI
Max
VCC 2.1V
Enable Input VI
Data Input VI
VCC 2.1V
VCC 2.1V
All Others at VCC or GND
ICCD
Dynamic ICC
No Load
mA/
(Note 5)
0.12
MHz
Max
Outputs Open
OE
GND, LE
V CC (Note 4)
One Bit Toggling, 50% Duty Cycle
Note 4: For 8 bits toggling, ICCD 0.8 mA/MHz.
Note 5: Guaranteed but not tested.
3
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74ABT573
Absolute Maximum Ratings(Note 2)
74ABT573
DC Electrical Characteristics
Symbol
Parameter
Min
Conditions
Typ
Max
Units
VCC
0.7
1.0
V
5.0
TA
25qC (Note 6)
CL
50 pF, RL
VOLP
Quiet Output Maximum Dynamic VOL
VOLV
Quiet Output Minimum Dynamic VOL
1.5
1.2
V
5.0
TA
25qC (Note 6)
VOHV
Minimum HIGH Level Dynamic Output Voltage
2.5
3.0
V
5.0
TA
25qC (Note 7)
VIHD
Minimum HIGH Level Dynamic Input Voltage
2.2
1.8
V
5.0
TA
25qC (Note 8)
VILD
Maximum LOW Level Dynamic Input Voltage
V
5.0
TA
25qC (Note 8)
1.0
0.7
500:
Note 6: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 7: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 8: Max number of data inputs (n) switching. n 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ).
Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Package)
TA
Symbol
Parameter
25qC
VCC
5.0V
CL
50 pF
40qC to 85qC
TA
VCC
4.5V to 5.5V
CL
Min
Typ
Max
Min
Max
tPLH
Propagation Delay
1.9
2.7
4.5
1.9
4.5
tPHL
Dn to On
1.9
2.8
4.5
1.9
4.5
tPLH
Propagation Delay
2.0
3.1
5.0
2.0
5.0
tPHL
LE to On
2.0
3.0
5.0
2.0
5.0
tPZH
Output Enable Time
1.5
3.1
5.3
1.5
5.3
1.5
3.1
5.3
1.5
5.3
tPZL
Units
50 pF
tPHZ
Output Disable Time
2.0
3.6
5.4
2.0
5.4
tPLZ
Time
2.0
3.4
5.4
2.0
5.4
ns
ns
ns
ns
AC Operating Requirements
(SOIC and SSOP Package)
TA
Symbol
Parameter
Min
25qC
VCC
5.0V
CL
50 pF
Typ
VCC
Max
Min
Max Toggle Frequency
tS(H)
Set Time, HIGH
1.5
1.5
tS(L)
or LOW Dn to LE
1.5
1.5
100
tH(H)
Hold Time, HIGH
1.0
1.0
or LOW Dn to LE
1.0
1.0
tW(H)
Pulse Width,
3.0
3.0
4
Units
50 pF
Max
MHz
tH(L)
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4.5V to 5.5V
CL
fTOGGLE
LE HIGH
40qC to 85qC
TA
ns
ns
ns
74ABT573
Extended AC Electrical Characteristics
(SOIC Package)
40qC to 85qC
TA
VCC
Symbol
CL
Parameter
40qC to 85qC
TA
4.5V to 5.5V
VCC
50 pF
CL
8 Outputs Switching
40qC to 85qC
TA
4.5V to 5.5V
VCC
250 pF
4.5V to 5.5V
CL
(Note 10)
250 pF
(Note 9)
(Note 11)
Min
Max
Min
Max
Min
Max
tPLH
Propagation Delay
1.5
5.2
2.0
6.8
2.0
9.0
tPHL
Dn to On
1.5
5.2
2.0
6.8
2.0
9.0
tPLH
Propagation Delay
1.5
5.5
2.0
7.5
2.0
9.5
tPHL
LE to On
1.5
5.5
2.0
7.5
2.0
9.5
tPZH
Output Enable Time
1.5
6.2
2.0
8.0
2.0
10.5
1.5
6.2
2.0
8.0
2.0
10.5
1.0
5.5
1.0
5.5
tPZL
Output Disable Time
tPHZ
tPLZ
Units
8 Outputs Switching
(Note 12)
ns
ns
ns
(Note 12)
ns
Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.).
Note 10: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only.
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 12: The 3-STATE delay times are dominated by the RC network (500:, 250 pF) on the output and has been excluded from the datasheet.
Skew
(Note 13)
(SOIC Package)
40qC to 85qC
TA
VCC
Symbol
Parameter
CL
40qC to 85qC
TA
4.5V to 5.5V
VCC
50 pF
4.5V to 5.5V
CL
250 pF
Units
8 Outputs Switching
8 Outputs Switching
(Note 13)
(Note 14)
Max
Max
tOSHL (Note 15)
Pin to Pin Skew, HL Transitions
1.0
1.5
ns
tOSLH (Note 15)
Pin to Pin Skew, LH Transitions
1.0
1.5
ns
tPS (Note 16)
Duty Cycle, LH–HL Skew
1.4
3.5
ns
tOST (Note 15)
Pin to Pin Skew, LH/HL Transitions
1.5
3.9
ns
tPV (Note 17)
Device to Device Skew LH/HL Transitions
2.0
4.0
ns
Note 13: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.)
Note 14: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 15: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). This specification is guaranteed but not tested.
Note 16: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 17: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not
tested.
Capacitance
Conditions
Symbol
Parameter
CIN
Input Capacitance
COUT (Note 18)
Output Capacitance
Note 18: COUT is measured at frequency f
Typ
Units
5
pF
VCC
0V
9
pF
VCC
5.0V
(TA
25qC)
1 MHz per MIL-STD-883B, Method 3012.
5
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74ABT573
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Test Load
FIGURE 2. Test Input Signal Levels
Amplitude
Rep. Rate
tW
tr
tf
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
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74ABT573
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
7
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74ABT573
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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8
74ABT573
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
9
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74ABT573
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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10
74ABT573 Octal D-Type Latch with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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