TI SN74AUC16501GQLR

SN74AUC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES418 – DECEMBER 2002 – REVISED JUNE 2005
FEATURES
•
•
•
•
•
•
•
•
•
DGG OR DGV PACKAGE
(TOP VIEW)
Member of the Texas Instruments Widebus™
Family
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 2 ns at 1.8 V
Low Power Consumption, 10 µA at 1.8 V
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
DESCRIPTION/ORDERING INFORMATION
This 18-bit universal bus transceiver is operational at
0.8-V to 2.7-V VCC, but is designed specifically for
1.65-V to 1.95-V VCC operation.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and CLKBA)
inputs. For A-to-B data flow, the device operates in
the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held at
a high or low logic level. If LEAB is low, the A data is
stored in the latch/flip-flop on the low-to-high
transition of CLKAB. When OEAB is high, the outputs
are active. When OEAB is low, the outputs are in the
high-impedance state.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
GND
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
GND
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TSSOP – DGG
Tape and reel
SN74AUC16501DGGR
AUC16501
TVSOP – DGV
Tape and reel
SN74AUC16501DGVR
MH501
VFBGA – GQL
Tape and reel
SN74AUC16501GQLR
MH501
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2005, Texas Instruments Incorporated
SN74AUC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES418 – DECEMBER 2002 – REVISED JUNE 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor, and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
GQL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
TERMINAL ASSIGNMENTS
2
1
2
3
4
5
6
A
A1
LEAB
OEAB
GND
CLKAB
B1
B
A3
A2
GND
GND
B2
B3
C
A5
A4
VCC
VCC
B4
B5
D
A7
A6
GND
GND
B6
B7
E
A9
A8
B8
B9
F
A10
A11
B11
B10
G
A12
A13
GND
GND
B13
B12
H
A14
A15
VCC
VCC
B15
B14
J
A16
A17
GND
GND
B17
B16
K
A18
OEBA
LEBA
GND
CLKBA
B18
SN74AUC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES418 – DECEMBER 2002 – REVISED JUNE 2005
FUNCTION TABLE
(1)
INPUTS
(1)
(2)
(3)
OEAB
LEAB
CLKAB
A
OUTPUT
B
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
↑
L
L
H
L
↑
H
H
H
L
H
X
B0 (2)
H
L
L
X
B0 (3)
A-to-B data flow is shown; B-to-A flow is similar, but uses OEBA,
LEBA, and CLKBA.
Output level before the indicated steady-state input conditions were
established, provided that CLKAB was high before LEAB went low
Output level before the indicated steady-state input conditions were
established
LOGIC DIAGRAM (POSITIVE LOGIC)
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
3
1D
C1
CLK
54
B1
1D
C1
CLK
To 17 Other Channels
Pin numbers shown are for the DGG and DGV packages.
3
SN74AUC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES418 – DECEMBER 2002 – REVISED JUNE 2005
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
3.6
V
VI
Input voltage range (2)
–0.5
3.6
V
–0.5
3.6
V
–0.5
VCC + 0.5
state (2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
±100
mA
Continuous current through VCC or GND
θJA
Package thermal impedance (3)
Tstg
(1)
(2)
(3)
DGG package
64
DGV package
48
GQL package
42
Storage temperature range
–65
V
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
VCC
Supply voltage
VCC = 0.8 V
VIH
High-level input voltage
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
MIN
MAX
0.8
2.7
Low-level input voltage
0.65 × VCC
0
VCC = 1.1 V to 1.95 V
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
4
V
1.7
0.35 × VCC
VCC = 2.3 V to 2.7 V
VI
V
VCC
VCC = 0.8 V
VIL
UNIT
V
0.7
0
3.6
Active state
0
VCC
3-state
0
3.6
VCC = 0.8 V
–0.7
VCC = 1.1 V
–3
VCC = 1.4 V
–5
VCC = 1.65 V
–8
VCC = 2.3 V
–9
VCC = 0.8 V
0.7
VCC = 1.1 V
3
VCC = 1.4 V
5
VCC = 1.65 V
8
VCC = 2.3 V
9
–40
V
V
mA
mA
20
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74AUC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES418 – DECEMBER 2002 – REVISED JUNE 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
VOL
II
TEST CONDITIONS
MIN TYP (1) MAX
VCC
IOH = –100 µA
0.8 V to 2.7 V
IOH = –0.7 mA
0.8 V
IOH = –3 mA
1.1 V
0.8
IOH = –5 mA
1.4 V
1
IOH = –8 mA
1.65 V
1.2
IOH = –9 mA
2.3 V
1.8
IOL = 100 µA
0.8 V to 2.7 V
IOL = 0.7 mA
0.8 V
IOL = 3 mA
1.1 V
0.3
IOL = 5 mA
1.4 V
0.4
IOL = 8 mA
1.65 V
0.45
IOL = 9 mA
2.3 V
0.6
Control inputs VI = VCC or GND
UNIT
VCC – 0.1
0.55
V
0.2
0.25
V
0.8 V to 2.7 V
±5
µA
0
±10
µA
2.7 V
±10
µA
20
µA
4.5
pF
Ioff
VI or VO = 2.7 V
IOZ (2)
VO = VCC or GND
ICC
VI = VCC or GND,
Ci
VI = VCC or GND
2.5 V
3.5
Cio
VO = VCC or GND
2.5 V
6
7.5
pF
(1)
(2)
IO = 0
0.8 V to 2.7 V
All typical values are at TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 0.8 V
TYP
fclock
Clock frequency
tw
Pulse
duration
tsu
Setup
time
Hold time
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN MAX
MIN MAX
MIN MAX
MIN MAX
150
250
300
350
85
LE high
5.8
4
1.7
1.5
1.5
CLK high or low
5.8
4
1.7
1.5
1.5
Data before CLK↑
0.2
0.6
0.6
0.6
0.6
CLK high
0.1
0.4
0.4
0.3
0.3
CLK low
0.1
0.4
0.4
0.3
0.3
0.3
1.2
1.1
0.9
0.9
1.3
1.5
1.3
1.2
1.2
Data before LE↓
Data after CLK↑
th
VCC = 1.2 V
± 0.1 V
Data after LE↓
CLK high
or low
UNIT
MHz
ns
ns
ns
5
SN74AUC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES418 – DECEMBER 2002 – REVISED JUNE 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
tpd
A or B
B or A
8.5
0.9
4
1
tpd
LE
9.8
1.6
6.3
tpd
CLK
9.2
1.5
9.7
1.6
15
PARAMETER
fmax
ten
tdis
ten
tdis
TYP
MIN
A or B
OEAB
B
OEBA
A
MIN
MAX
350
MHz
2.8
0.3
2
2.8
0.1
2.3
ns
1
4.1
0.9
2.5
3.8
0.7
3
ns
3.8
0.7
3.1
0.9
2.2
3.3
0.6
2.7
ns
3
1.1
3.2
1
1.8
3.4
0.8
2.8
ns
3.6
5.3
0.9
5.7
1.7
2.4
3.2
1
3.1
ns
11
1.7
5.7
1
3.7
1
2.2
3.7
0.7
3
ns
18
3.5
7.5
1.4
5.4
2
3.5
5.2
0.9
3
ns
250
MIN
UNIT
TYP
150
MAX
VCC = 2.5 V
± 0.2 V
MIN
85
MAX
VCC = 1.8 V
± 0.15 V
MAX
300
Operating Characteristics
for transparent mode, TA = 25°C
VCC = 0.8 V
VCC = 1.2 V
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
TYP
TYP
TYP
TYP
TYP
Power
dissipation
capacitance
1 fdata = 10 MHz,
fclk = VCC or
Outputs GND,
enabled, 1 fout = 10 MHz,
1 output OEAB = VCC,
switching OEBA = GND,
LE = VCC,
CL = 0 pF
30
31
33
36
44
pF
Power
dissipation
capacitance
1 fdata = 10 MHz,
fclk = VCC or
GND,
1 fout = not
switching,
OEAB = GND,
OEBA = VCC,
LE = VCC,
CL = 0 pF
9
9
10
12
16
pF
TEST
CONDITIONS
PARAMETER
Cpd
(each
bit) (1)
Cpd
(each
bit) (1)
(1)
6
Outputs
disabled
UNIT
Cpd (each bit) is the Cpd for each data bit (input and output circuitry) as it operates at 5 MHz (the clock is operating at 10 MHz in this
test, but its ICC component has been subtracted out).
SN74AUC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES418 – DECEMBER 2002 – REVISED JUNE 2005
Operating Characteristics
(1)
for clocked mode, TA = 25°C
VCC = 0.8 V
VCC = 1.2 V
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
TYP
TYP
TYP
TYP
TYP
Cpd
(each
bit) (2)
1 fdata = 5 MHz,
1 fclk = 10 MHz,
Outputs
Power
1 fout = 5 MHz,
enabled, 1
dissipation
OEAB = VCC,
output
capacitance
OEBA = GND,
switching
LE = GND,
CL = 0 pF
29
30
31
35
43
pF
Cpd(Z)
1 fdata = 5 MHz,
1 fclk = 10 MHz,
Outputs
fout = not
Power
disabled,
switching,
dissipation 1 clock
OEAB = GND,
capacitance and 1 data
OEBA = VCC,
switching
LE = GND,
CL = 0 pF
8
8
9
10
13
pF
1 fdata = 0 MHz,
1 fclk = 10 MHz,
fout = not
switching,
OEAB = GND,
OEBA = VCC,
LE = GND,
CL = 0 pF
31
32
32
34
39
pF
PARAMETER
Cpd
(each
clock) (3)
(1)
(2)
(3)
Outputs
Power
disabled,
dissipation
clock only
capacitance
switching
TEST
CONDITIONS
UNIT
Total device Cpd for multiple (n) outputs switching and (y) clocks inputs switching = {n * Cpd (each output)} + {y * Cpd (each clock)}
Cpd (each bit) is the Cpd for each data bit (input and output circuitry) as it operates at 5 MHz (the clock is operating at 10 MHz in this
test, but its ICC component has been subtracted out).
Cpd (each clock) is the Cpd for the clock circuitry only as it operates at 10 MHz.
7
SN74AUC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES418 – DECEMBER 2002 – REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
Open
RL
LOAD CIRCUIT
VCC
CL
RL
V∆
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
th
VCC
VCC/2
Input
VCC/2
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VCC/2
VCC/2
VOL
tPHL
VOH
Output
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
tPLZ
VCC
VCC/2
tPZH
VCC/2
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC/2
tPZL
VOH
Output
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VCC/2
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
8
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74AUC16501DGGR
PREVIEW
TSSOP
DGG
56
2000
TBD
Call TI
Call TI
SN74AUC16501DGVR
PREVIEW
TVSOP
DGV
56
2000
TBD
Call TI
Call TI
SN74AUC16501GQLR
PREVIEW
VFBGA
GQL
56
1000
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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