UC19432-SP www.ti.com SLUS951A – NOVEMBER 2009 – REVISED JULY 2010 Rad-Tolerant Class-V, Precision Analog Controller Check for Samples: UC19432-SP FEATURES • • • • 1 • • • • • • • (1) QML-V Qualified, SMD 5962-09233 Rad Tolerant: 30 kRad(Si) TID (1) – TID Dose Rate = 10 mRad/sec Programmable Transconductance for Optimum Current Drive Accessible 1.3 V precision Reference Both Error Amplifier Inputs Available 0.7% Overall Reference Tolerance 0.4% Initial Accuracy 2.4-V to 24-V Operating Supply Voltage and User Programmable Reference Reference Accuracy Maintained for Entire Range of Supply Voltage Superior Accuracy and Easier Compensation for Optoisolator Application Low Quiescent Current (0.5 mA Typ) JG PACKAGE (TOP VIEW) Radiation tolerance is a typical value based upon initial device qualification. Radiation Lot Acceptance Testing is available contact factory for details. DESCRIPTION The UC19432 is an adjustable precision analog controller with 100-mA sink capability if the ISET pin is grounded. A resistor between ISET and ground will modify the transconductance while decreasing the maximum current sink. This will add further control in the optocoupler configuration. The trimmed precision reference along with the non-inverting error amplifier inputs are accessible for custom configuration. A sister device, the UC19431 adjustable shunt regulator, has an on-board resistor network providing six preprogrammed voltage levels, as well as exernal programming capability. ORDERING INFORMATION TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING –55°C to 125°C CDIP-8 5962-0923301VPA UC19432-SP 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2010, Texas Instruments Incorporated UC19432-SP SLUS951A – NOVEMBER 2009 – REVISED JULY 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE UNIT VCC Supply voltage 24 V VCOLL Regulated output 24 V SENSE, EA input EA+ 6 V COMP EA compensation 6 V REF Reference output 6 V ICOLL Output sink current (continuous or time average) 125 mA ISET Output source current (continuous or time average) –125 mA 1 W Storage temperature range –65 to 150 °C Junction temperature –55 to 150 °C 300 °C Power dissipation at TA ≤ 25°C Derate 8 mW/°C for TA > 25°C Lead temperature (soldering, 10 seconds) (1) 2 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): UC19432-SP UC19432-SP www.ti.com SLUS951A – NOVEMBER 2009 – REVISED JULY 2010 ELECTRICAL CHARACTERISTICS over operating free-air temperature range, COLL output = 2.4 V to 24 V, VCC = 15 V, ICOLL = 10 mA, TA = TJ = –55°C to 125°C (unless otherwise noted). MIN TYP MAX UNIT Reference voltage tolerance PARAMETER TA = 25°C, VCOLL = 5 V TEST CONDITIONS 1.295 1.3 1.305 V Reference temperature tolerance VCOLL = 5 V 1.291 1.3 1.309 V Reference line regulation VCC = 2.4 V to 24 V, VCOLL = 5 V 10 38 mV Reference load regulation ICOLL = 10 mA TO 50 mA, VCOLL = 5 V 10 38 mV 10 mA Reference sink current Reference source current -10 EA input bias current –0.5 EA input offset voltage mA –0.2 mA -4 4 EA+ Operational voltage limitations 0.9 1.6 EA output current sink (internally limited) 16 mV V mA EA output current source -0.8 mA Minimum operating current VCC = 24 V, VCOLL = 5 V 0.5 0.8 mA Collector current limit (1) VCOLL = VCC = 24 V, Ref = 1.3 V, ISET = GND 130 155 mA Collector saturation ICOLL = 20 mA 0.7 1.1 1.5 V Transconductance (gm) (1) VCC = 2.4 V to 24 V, VCOLL = 3 V, ISET = GND –170 –140 –110 Error amplifier AVOL 60 90 dB Error amplifier GBW 1.5 3 MHz 3 MHz (2) Transconductance amplifier GBW (1) (2) mS Programmed transconductance and collector current limit equations are specified in the ISET pin description. Measured as ΔICOLL/ΔVCOMP for ICOLL = 5 mA to 20 mA. PIN DESCRIPTIONS COLL The collector of the output transistor with a maximum voltage of 24 V. This pin is the output of the transconducance amplifier. The overall open loop voltage gain of the transconductance amplifier is gm x RL, where gm is designed to be –140 mS ±30 mS and RL represents the output load. COMP The output of the error amplifier and the input to the transconductance amplifier. This pin is available to compensate the high frequency gain of the error amplifier. It is internally voltage limited to approximately 2 V. EA+ The non-inverting input to the error amplifier. GND The reference and power ground for the device. The power ground of the output ransistor is isolated on the chip from the substrate ground used to bias the remainder of the device. ISET The current set pin for the transconductance amplifier. The transconductance will be –140 mS as specified in the electrical table if this pin is grounded. If a resistance, RL, is added to the ISET pin, the resulting new transconductance is calculated using Equation 1. The maximum current will be approximated by Equation 2. REF -0.714 gm = ¾ (5.1 W + RL) (1) 0.65 V IMAX = 5.1 W + RL (2) The output of the trimmed precision reference. It can source or sink 10 mA and still maintain less than ±1% output variation. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): UC19432-SP 3 UC19432-SP SLUS951A – NOVEMBER 2009 – REVISED JULY 2010 www.ti.com SENSE The inverting terminal of the error amplifier used as both the voltage sense input to the error amplifier and its other compensation point. The error amplifier uses the SENSE input to compare against the 1.3-V on-chip reference. The SENSE pin is also used as the under-voltage lockout (UVLO). It is intended to keep the chip from operating until the internal reference is properly biased. The threshold is approximately 1 V. It is important that once the UVLO is released, the error amplifier can drive the transconductance amplifier to stabilize the loop. If a capacitor is connected between the SENSE and COMP pins to create a pole, it will limit the slew rate of the error amplifier. To increase the bandwidth and ensure startup a low load current, it is recommended to create a zero along with the pole as shown in he UC19431 shunt regulator application. The error amplifier must slew 2 V to drive the transconductance amplifier initially on. VCC The power connection for the device. The minimum to maximum operating voltage is 2.4 V to 24 V. The quiescent current is typically 0.5 mA. OVER-VOLTAGE COMPARATOR APPLICATION The signal VIN senses the input voltage. As long as the input voltage is less than 5.5 V, the output is equal to the voltage on VIN. During this region of operation, the diode is reversed biased which keeps the EA+ pin at 1.3 V. When VIN exceeds the over-voltage threshold of 5.5 V, the output is driven low. This forward biases the diode and creates hyseresis by changing the threshold to 4.5 V. Figure 1. 5.5-V Over-Voltage Comparator With Hysteresis 4 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): UC19432-SP UC19432-SP www.ti.com SLUS951A – NOVEMBER 2009 – REVISED JULY 2010 OPTOCOUPLER APPLICATION The optocoupler application shown in Figure 2 takes advantage of the accessible pins REF and ISET. The ISET pin has a 33-Ω resistor to ground that protects the optocoupler by limiting the current to about 16 mA. This also lowers the transconductance to approximately 19 mS. The ability to adjust the transconducance gives the designer further control of the loop gain. The REF pin is available to satisfy any high precision voltage requirements. Figure 2. 5-V Optocoupler Application Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): UC19432-SP 5 PACKAGE OPTION ADDENDUM www.ti.com 21-Aug-2012 PACKAGING INFORMATION Orderable Device 5962-0923301VPA Status (1) Package Type Package Drawing ACTIVE CDIP JG Pins Package Qty 8 1 Eco Plan TBD (2) Lead/ Ball Finish A42 MSL Peak Temp (3) Samples (Requires Login) N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UC19432-SP : • Catalog: UC19432 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). 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