SITRONIX ST7567

Sitronix
ST7567
65 x 132 Dot Matrix LCD Controller/Driver
1. INTRODUCTION
ST7567 is a single-chip dot matrix LCD driver which incorporates LCD controller and common/segment drivers. ST7567
can be connected directly to a microprocessor with 8-bit parallel interface or 4-line serial interface (SPI-4). Display data sent
from MPU is stored in the internal Display Data RAM (DDRAM) of 65x132 bits. The display data bits which are stored in
DDRAM are directly related to the pixels of LCD panel. ST7567 contains 132 segment-outputs, 64 common-outputs and 1
icon-common-output. With built-in oscillation circuit and low power consumption power circuit, ST7567 generates LCD
driving signal without external clock or power, so that it is possible to make a display system with the fewest components
and minimal power consumption.
2. FEATURES
Single-chip LCD Controller & Driver
Power Saving Mode, Select Common Driver Direction,
On-chip Display Data RAM (DDRAM)
Select Voltage Regulator Resistor Ratio (for V0).
Capacity: 65x132=8580 bits
External Hardware Reset Pin (RSTB)
Directly display RAM pattern from DDRAM
Built-in Oscillation Circuit
Selectable Display Duty (by SEL2 & SEL1)
1/65 duty : 65 common x 132 segment
Low Power Consumption Analog Circuit
1/55 duty : 55 common x 132 segment
Voltage Booster (4X, 5X)
1/49 duty : 49 common x 132 segment
High-accuracy Voltage Regulator for LCD Vop:
1/33 duty : 33 common x 132 segment
No external component required
(Thermal Gradient: -0.05%/°C)
Microprocessor Interface
Bidirectional 8-bit parallel interface supports:
Wide Operation Voltage Range
8080-series and 6800-series MPU
VDD1-VSS1=1.8V~3.3V
Serial interface (SPI-4) is also supported (write only)
VDD2-VSS2=2.4V~3.3V
Abundant Functions
VDD3-VSS3=2.4V~3.3V
Display ON/OFF, Normal/Reverse Display Mode, Set
Temperature Range: -30~85°C
Display Start Line, Read IC Status, Set all Display
Package Type: COG
Voltage Follower for LCD Bias Voltage
Points ON, Set LCD Bias, Electronic Volume Control,
Read-modify-Write, Select Segment Driver Direction,
ST7567
6800 , 8080 , 4-Line
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.
Ver 1.4b
1/49
2009/02/04
ST7567
3-1. ST7567 COG OUTLINE
Chip Size: 4840 X 660
Bump Height: 15
Unit:
um
12
27
Part Number
Chip Thickness
ST7567-G4
300
10
Bump Size
PAD No.
Size
1~12, 76~261
16 X 138.5
13~55, 65~75
50 X 45
56~64
45 X 45
35
Bump Space (minimum)
PAD No.
Space
1~12, 76~87, 88~108, 109~240, 241~261
Refer to Fig 1
13~55, 65~75
15
56~64
10
55-56, 64-65
12.5
Y
X
* Refer to section “PAD CENTER COORDINATES” for ITO layout.
11
16
38
54
7.5
35
10
16
Fig 1. Chip Outline
Ver 1.4b
2/49
2009/02/04
ST7567
3-2. PAD CENTER COORDINATES
65 Duty
PAD NO.
PIN Name
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
COM[53]
COM[54]
COM[55]
COM[56]
COM[57]
COM[58]
COM[59]
COM[60]
COM[61]
COM[62]
COM[63]
COMS1
CL
CSB
RSTB
A0
RWR
ERD
VDDH
D0
D1
D2
D3
D4
D5
D6
D7
VDD1
VDD1
VDD2
VDD2
VDD2
VDD3
VSS1
VSS1
VSS3
VSS2
VSS2
VSS2
V0in
-2363.00
-2336.00
-2309.00
-2282.00
-2255.00
-2228.00
-2201.00
-2174.00
-2147.00
-2120.00
-2093.00
-2066.00
-1970.00
-1905.00
-1840.00
-1775.00
-1710.00
-1645.00
-1580.00
-1515.00
-1450.00
-1385.00
-1320.00
-1255.00
-1190.00
-1125.00
-1060.00
-995.00
-930.00
-865.00
-800.00
-735.00
-670.00
-605.00
-540.00
-475.00
-410.00
-345.00
-280.00
-215.00
-74.25
-227.75
-74.25
-227.75
-74.25
-227.75
-74.25
-227.75
-74.25
-227.75
-74.25
-227.75
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
Fig 2. PAD Location
Ver 1.4b
3/49
2009/02/04
ST7567
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
V0in
V0s
V0out
V0out
XV0out
XV0out
XV0s
XV0in
XV0in
VMO
VMO
VGin
VGin
VGs
VGout
T[6]
T[7]
T[8]
TFCOM
T[1]
T[2]
T[3]
T[4]
T[5]
Vref
VSSL
VDDH
C86
PSB
SEL1
VSSL
SEL2
VDD1
VDD2
VDD3
COM[31]
COM[30]
COM[29]
COM[28]
COM[27]
-150.00
-85.00
-20.00
45.00
110.00
175.00
240.00
305.00
370.00
435.00
500.00
565.00
630.00
695.00
760.00
820.00
875.00
930.00
985.00
1040.00
1095.00
1150.00
1205.00
1260.00
1320.00
1385.00
1450.00
1515.00
1580.00
1645.00
1710.00
1775.00
1840.00
1905.00
1970.00
2066.00
2093.00
2120.00
2147.00
2174.00
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-274.50
-74.25
-227.75
-74.25
-227.75
-74.25
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
COM[26]
COM[25]
COM[24]
COM[23]
COM[22]
COM[21]
COM[20]
COM[19]
COM[18]
COM[17]
COM[16]
COM[15]
COM[14]
COM[13]
COM[12]
COM[11]
COM[10]
COM[9]
COM[8]
COM[7]
COM[6]
COM[5]
COM[4]
COM[3]
COM[2]
COM[1]
COM[0]
COMS2
SEG[0]
SEG[1]
SEG[2]
SEG[3]
SEG[4]
SEG[5]
SEG[6]
SEG[7]
SEG[8]
SEG[9]
SEG[10]
SEG[11]
2201.00
2228.00
2255.00
2282.00
2309.00
2336.00
2363.00
2363.00
2336.00
2309.00
2282.00
2255.00
2228.00
2201.00
2174.00
2147.00
2120.00
2093.00
2066.00
2039.00
2012.00
1985.00
1958.00
1931.00
1904.00
1877.00
1850.00
1823.00
1768.50
1741.50
1714.50
1687.50
1660.50
1633.50
1606.50
1579.50
1552.50
1525.50
1498.50
1471.50
-227.75
-74.25
-227.75
-74.25
-227.75
-74.25
-227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
Ver 1.4b
4/49
2009/02/04
ST7567
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
SEG[12]
SEG[13]
SEG[14]
SEG[15]
SEG[16]
SEG[17]
SEG[18]
SEG[19]
SEG[20]
SEG[21]
SEG[22]
SEG[23]
SEG[24]
SEG[25]
SEG[26]
SEG[27]
SEG[28]
SEG[29]
SEG[30]
SEG[31]
SEG[32]
SEG[33]
SEG[34]
SEG[35]
SEG[36]
SEG[37]
SEG[38]
SEG[39]
SEG[40]
SEG[41]
SEG[42]
SEG[43]
SEG[44]
SEG[45]
SEG[46]
SEG[47]
SEG[48]
SEG[49]
SEG[50]
SEG[51]
1444.50
1417.50
1390.50
1363.50
1336.50
1309.50
1282.50
1255.50
1228.50
1201.50
1174.50
1147.50
1120.50
1093.50
1066.50
1039.50
1012.50
985.50
958.50
931.50
904.50
877.50
850.50
823.50
796.50
769.50
742.50
715.50
688.50
661.50
634.50
607.50
580.50
553.50
526.50
499.50
472.50
445.50
418.50
391.50
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
SEG[52]
SEG[53]
SEG[54]
SEG[55]
SEG[56]
SEG[57]
SEG[58]
SEG[59]
SEG[60]
SEG[61]
SEG[62]
SEG[63]
SEG[64]
SEG[65]
SEG[66]
SEG[67]
SEG[68]
SEG[69]
SEG[70]
SEG[71]
SEG[72]
SEG[73]
SEG[74]
SEG[75]
SEG[76]
SEG[77]
SEG[78]
SEG[79]
SEG[80]
SEG[81]
SEG[82]
SEG[83]
SEG[84]
SEG[85]
SEG[86]
SEG[87]
SEG[88]
SEG[89]
SEG[90]
SEG[91]
364.50
337.50
310.50
283.50
256.50
229.50
202.50
175.50
148.50
121.50
94.50
67.50
40.50
13.50
-13.50
-40.50
-67.50
-94.50
-121.50
-148.50
-175.50
-202.50
-229.50
-256.50
-283.50
-310.50
-337.50
-364.50
-391.50
-418.50
-445.50
-472.50
-499.50
-526.50
-553.50
-580.50
-607.50
-634.50
-661.50
-688.50
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
Ver 1.4b
5/49
2009/02/04
ST7567
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
SEG[92]
SEG[93]
SEG[94]
SEG[95]
SEG[96]
SEG[97]
SEG[98]
SEG[99]
SEG[100]
SEG[101]
SEG[102]
SEG[103]
SEG[104]
SEG[105]
SEG[106]
SEG[107]
SEG[108]
SEG[109]
SEG[110]
SEG[111]
SEG[112]
SEG[113]
SEG[114]
SEG[115]
SEG[116]
SEG[117]
SEG[118]
SEG[119]
SEG[120]
SEG[121]
SEG[122]
SEG[123]
SEG[124]
SEG[125]
SEG[126]
SEG[127]
SEG[128]
SEG[129]
SEG[130]
SEG[131]
-715.50
-742.50
-769.50
-796.50
-823.50
-850.50
-877.50
-904.50
-931.50
-958.50
-985.50
-1012.50
-1039.50
-1066.50
-1093.50
-1120.50
-1147.50
-1174.50
-1201.50
-1228.50
-1255.50
-1282.50
-1309.50
-1336.50
-1363.50
-1390.50
-1417.50
-1444.50
-1471.50
-1498.50
-1525.50
-1552.50
-1579.50
-1606.50
-1633.50
-1660.50
-1687.50
-1714.50
-1741.50
-1768.50
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
COM[32]
COM[33]
COM[34]
COM[35]
COM[36]
COM[37]
COM[38]
COM[39]
COM[40]
COM[41]
COM[42]
COM[43]
COM[44]
COM[45]
COM[46]
COM[47]
COM[48]
COM[49]
COM[50]
COM[51]
COM[52]
-1823.00
-1850.00
-1877.00
-1904.00
-1931.00
-1958.00
-1985.00
-2012.00
-2039.00
-2066.00
-2093.00
-2120.00
-2147.00
-2174.00
-2201.00
-2228.00
-2255.00
-2282.00
-2309.00
-2336.00
-2363.00
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
74.25
227.75
Ver 1.4b
Note:
1.
Unit: um
2.
This is the default PAD Center Coordinate Table with
1/65 Duty. Other duty output mapping can be found
in Section FUNCTION DESCRIPTION and Fig 9.
3.
4.
Tolerance: +/- 0.05 um.
The definition of pin name is in full duty (65
duty).
5.
The definition of output pin name in different
duty (55 Duty, 49 Duty and 33 Duty) please refers
Fig 9.
6/49
2009/02/04
ST7567
4. BLOCK DIAGRAM
Fig 3.
Ver 1.4b
Block Diagram
7/49
2009/02/04
ST7567
5. PIN DESCRIPTION
LCD Driver Output Pins
Pin Name
Type
Description
No. of Pins
LCD segment driver outputs.
The display data and the frame control the output voltage.
SEG0 to SEG131
Display data
Frame
H
O
Segment Driver Output Voltage
Normal Display
Inverse Display
+
VG
VSS
H
-
VSS
VG
L
+
VSS
VG
L
-
VG
VSS
VSS
VSS
Display OFF, Power Save
132
LCD common driver outputs.
The internal scanning signal and the frame control the output voltage.
COM0 to COM63
Common Driver Output Voltage
Scan signal
Frame
H
+
XV0
H
-
V0
L
+
VM
L
-
VM
O
Normal Display
Display OFF, Power Save
COMS1, COMS2
(COMS)
Inverse Display
64
VSS
LCD common driver outputs for icons.
O
The output signals of these two pins are the same.
2
When icon feature is not used, these pins should be left open.
Microprocessor Interface Pins
Pin Name
Type
RSTB
I
CSB
I
A0
I
Description
No. of Pins
Hardware reset input pin. When RSTB is “L”, internal initialization is executed
and the internal registers will be initialized.
Chip select input pin. Interface access is enabled when CSB is “L”.
When CSB is non-active (CSB=“H”), D[7:0] pins are high impedance.
1
1
It determines whether the access is related to data or command.
A0=“H” : Indicates that signals on D[7:0] are display data.
1
A0=“L” : Indicates that signals on D[7:0] are command.
Read/Write execution control pin. When PSB is “H”,
C86
H
RWR
I
L
MPU Type
6800
series
8080
series
RWR
Description
Read/Write control input pin.
R/W
R/W=“H”: read.
R/W=“L”: write.
1
Write enable input pin.
/WR
Signals on D[7:0] will be latched at the rising
edge of /WR signal.
RWR is not used in serial interface and should fix to “H” by VDD1 or VDDH.
Ver 1.4b
8/49
2009/02/04
ST7567
Pin Name
Type
Description
No. of Pins
Read/Write execution control pin. When PSB is “H”,
MPU Type
C86
ERD
Description
Read/Write control input pin.
ERD
I
R/W=”H“: When E is “H”, D[7:0] are in output
6800
H
E
series
mode.
R/W=”L“: Signals on D[7:0] are latched at the
1
falling edge of E signal.
8080
L
Read enable input pin.
/RD
series
When /RD is “L”, D[7:0] are in output mode.
ERD is not used in serial interface and should fix to “H” by VDD1 or VDDH.
When using 8-bit parallel interface: (6800 or 8080 mode)
I/O
8-bit bi-directional data bus. Connect to the data bus of 8-bit microprocessor.
When CSB is non-active (CSB=“H”), D[7:0] pins are high impedance.
When using serial interface: 4-LINE
D[7:0]
8
D7=SDA : Serial data input.
I
D6=SCL : Serial clock input.
D[5:0] are not used and should connect to “H” by VDD1 or VDDH.
When CSB is non-active (CSB=“H”), D[7:0] pins are high impedance.
Note:
1.
After VDD1 is turned ON, any MPU interface pins cannot be left floating.
Configuration Pins
Pin Name
Type
Description
No. of Pins
VDDH
I
Logic “1” level for option pins which should connected to “H”.
2
VSSL
I
Logic “0” level for option pins which should connected to “L”.
2
PSB
I
PSB selects the interface type: Serial or Parallel.
1
C86 selects the microprocessor type in parallel interface mode.
C86
I
PSB
C86
Selected Interface
“H”
“H”
Parallel 6800 Series MPU Interface
“H”
“L”
Parallel 8080 Series MPU Interface
“L”
“X”
Serial 4-Line SPI Interface
1
Please refer to “APPLICATION NOTES” and “Microprocessor Interface”
(Section 6) for detailed connection of the selected interface.
These pins select the display duty and bias of ST7567.
SEL[2:1]
I
SEL2
SEL1
Duty
Bias
“L”
“L”
1/65
1/9 or 1/7
“L”
“H”
1/49
1/8 or 1/6
“H”
“L”
1/33
1/6 or 1/5
“H”
“H”
1/55
1/8 or 1/6
2
Note:
1.
Ver 1.4b
The detailed definition of output pin name can be found in Fig 9.
9/49
2009/02/04
ST7567
Power System Pins
Pin Name
Type
Description
No. of Pins
VDD1
Power
Digital power. If VDD1=VDD2, connect to VDD2 externally.
3
VDD2
Power
Analog power. If VDD1=VDD2, connect to VDD1 externally.
4
VDD3
Power
Power for reference voltage circuit.
2
VSS1
Power
Digital ground. Connect to VSS2 externally.
2
VSS2
Power
Analog ground. Connect to VSS1 externally.
3
VSS3
Power
Ground for reference voltage circuit.
1
V0 is the LCD driving voltage for common circuits at negative frame.
V0out is the output of V0 regulator. V0s is the feedback of V0 regulator.
V0out
V0in
Power
V0s
V0in is the V0 input of common circuits.
Be sure that: V0 ≥ VG > VM > VSS ≥ XV0 (under operation).
V0out, V0in & V0s should be separated in ITO layout.
2
2
1
V0out, V0in & V0s should be connected together in FPC layout.
XV0 is the LCD driving voltage for common circuits at positive frame.
XV0out
XV0in
Power
XV0s
XV0out is the output of XV0 regulator. XV0s is the feedback of XV0 regulator.
2
XV0in is the V0 input of common circuits.
2
XV0out, XV0in & XV0s should be separated in ITO layout.
1
XV0out, XV0in & XV0s should be connected together in FPC layout.
VG is the LCD driving voltage for segment circuits.
Vgout is the output of VG regulator. VGs is the feedback of VG regulator.
VGout
Vgin
Power
VGs
Vgin is the VG input of segment circuits.
Vgout, Vgin & VGs should be separated in ITO layout.
Vgout, Vgin & VGs should be connected together in FPC layout.
1
2
1
1.6 ≤ VG < VDD2.
VMO
Power
VM is the LCD driving voltage for common circuits.
0.8V ≤ VM < VDD2.
2
Test Pins
Pin Name
Type
Vref
T
T1~T8
T
TFCOM
T
CL
T
Ver 1.4b
Description
Test pin for power system.
This pin must be left open (without any kinds of connection).
Do NOT use. Reserved for testing.
Must be floating.
Do NOT use. Reserved for testing.
Must be floating.
Do NOT use. Reserved for testing.
Must be floating.
10/49
No. of Pins
1
8
1
1
2009/02/04
ST7567
Recommend ITO Resistance
Pin Name
ITO Resistance
VMO, Vref, T[1:8], TFCOM, CL
Floating
VDD1, VDD2, VDD3, VSS1, VSS2, VSS3
< 100Ω
V0(V0in, V0out, V0s), VG(Vgin, Vgout, VGs), XV0(XV0in, XV0out, XV0s)
< 300Ω
A0, RWR, ERD, CSB, D[7:0]
< 1KΩ
PSB, C86, SEL[2:1]
< 5KΩ
RSTB
*1
< 10KΩ
Note:
1.
To prevent the ESD pulse resetting the internal register, applications should increase the resistance of RSTB signal
(add a series resistor or increase ITO resistance). The value is different from modules.
2.
The option setting to be “H” should connect to VDD1 or VDDH.
3.
The option setting to be “L” should connect to VSS1 or VSSL.
Ver 1.4b
11/49
2009/02/04
ST7567
FUNCTION DESCRIPTION
Microprocessor Interface
Chip Select Input
CSB pin is used for chip selection. When CSB is “L”, the microprocessor interface is enabled and ST7567 can interface with
an MPU. When CSB is “H”, the inputs of A0, ERD and RWR with any combination will be ignored and D[7:0] are high
impedance. In 4-Line serial interface, the internal shift register and serial counter are reset when CSB is “H”.
Interface Selection
The interface selection is controlled by C86 and PSB pins. The selection for parallel or serial interface is shown in Table 1.
Table 1. Parallel/Serial Interface Mode
PSB
“H”
“H”
“L”
C86
CSB
A0
ERD
RWR
D[7:0]
MPU Interface
“H”
E
R/W
6800-series parallel interface
D[7:0]
CSB
A0
“L”
/RD
/WR
8080-series parallel interface
“X”
----Refer to serial interface.
4-Line SPI interface
The un-used pins are marked as “---” and should be fixed to “H” by VDD1 or VDDH.
Parallel Interface
When PSB= “H”, the 8-bit bi-directional parallel interface is enabled and the type of MPU is selected by “C86” pin as shown
in Table 2. The data transfer type is determined by signals on A0, ERD and RWR as shown in Table 3.
Table 2. Microprocessor Selection for Parallel Interface
PSB
“H”
“H”
C86
“H”
“L”
CSB
A0
CSB
A0
ERD
E
/RD
RWR
R/W
/WR
D[7:0]
D[7:0]
MPU Interface
6800-series parallel interface
8080-series parallel interface
Table 3. Parallel Data Transfer Type
Common Pins
CSB
“L”
A0
“H”
“H”
“L”
“L”
6800-Series
E (ERD)
“H”
“H”
“H”
“H”
R/W (RWR)
“H”
“L”
“H”
“L”
8080-Series
/RD (ERD)
“L”
“H”
“L”
“H”
/WR (RWR)
“H”
“L”
“H”
“L”
Description
Display data read out
Display data write
Internal status read
Writes to internal register (instruction)
Setting Serial Interface
Serial Mode
PSB
C86
CSB
A0
ERD
RWR
D[7:0]
4-Line SPI interface
“L”
X
CSB
A0
----SDA, SCLK, ---, ---, ---, ---, ---, --* The un-used pins are marked as “---” and should be fixed to “H” by VDD1 or VDDH.
* C86 is marked as “X” and can be fixed to “H” or “L”.
Note:
1.
The option setting to be “H” should connect to VDD1 or VDDH.
2.
The option setting to be “L” should connect to VSS1 or VSSL.
Ver 1.4b
12/49
2009/02/04
ST7567
4-line SPI interface (PSB=“L”, C86=“H” or “L”)
When ST7567 is active (CSB=“L”), serial data (SDA) and serial clock (SCLK) inputs are enabled. When ST7567 is not
active (CSB=“H”), the internal 8-bit shift register and 3-bit counter are reset. Serial data on SDA is latched at the rising edge
th
of serial clock on SCLK. After the 8 serial clock, the serial data will be processed to be 8-bit parallel data. The address
th
selection pin (A0), which is latched at the 8 clock, indicates the 8-bit parallel data is display data or instruction. The 8-bit
parallel data will be display data when A0 is “H” and will be instruction when A0 is “L”. The read feature is not available in
this mode. The DDRAM column address pointer will be increased by one automatically after each byte of DDRAM access.
Please note that the SCLK signal quality is very important and external noise maybe causes unexpected data/instruction
latch.
Fig 4.
4-Line SPI Access
Note:
Some MPU will set the interface to be Hi-Z (high impedance) mode when power saving mode or after hardware reset.
This is not allowed when the VDD1of ST7567 is turned ON. Because the floating input (especially for those control
pins such as CSB, RSTB, RWR or ERD…) maybe cause abnormal latch and cause abnormal display.
Ver 1.4b
13/49
2009/02/04
ST7567
Data Transfer
ST7567 uses bus latch and internal data bus for interface data transfer. When writing data from MPU to the DDRAM, data is
automatically transferred from the bus latch to the DDRAM as shown in Fig 5. When reading data from the on-chip DDRAM
to MPU, the first read cycle reads the content in bus latch (dummy read) and the data that MPU should read will be output
at the next read cycle as shown in Fig 6. That means: after setting the target address, a dummy read cycle is required
before the following read-operation. Therefore, the data of the specified address cannot be read at the first read of display
data right after setting the address, but can be read at the second read of display data.
Ver 1.4b
Fig 5.
Data Transfer : Write
Fig 6.
Data Transfer : Read
14/49
2009/02/04
ST7567
Display Data RAM (DDRAM)
ST7567 is built-in a RAM with 65X132 bit capacity which stores the display data. The display data RAM (DDRAM) store the
dot data of the LCD. It is an addressable array with 132 columns by 65 rows (8-page with 8-bit and 1-page with 1-bit). The
X-address is directly related to the column output number. Each pixel can be selected when the page and column
addresses are specified (please refer to Fig 7 for detailed illustration). The rows are divided into: 8 pages (Page-0 ~ Page-7)
each with 8 lines (for COM0~63) and Page-8 with only 1 line (COMS, for icon). The display data (D7~D0) corresponds to
the LCD common-line direction and D0 is on top. All pages can be accessed through D[7:0] directly except icon page. Icon
RAM uses only 1-bit of data bus (D0). Refer to Fig 8 for detailed illustration. The microprocessor can write to and read from
(only Parallel interfaces) DDRAM by the I/O buffer. Since the LCD controller operates independently, data can be written
into DDRAM at the same time as data is being displayed without causing the LCD flicker or data-conflict.
Fig 7.
DDRAM Mapping Mode (Default Setting)
Fig 8.
Ver 1.4b
DDRAM Format
15/49
2009/02/04
ST7567
Addressing
Data is downloaded into the Display Data RAM matrix in ST7567 as byte-format. The Display Data RAM has a matrix of 65
by 132 bits. The address ranges are: X=0~131 (column address), Y=0~8 (page address). Addresses outside these ranges
are not allowed.
Page Address Circuit
This circuit provides the page address of DDRAM. It incorporates 4-bit Page Address Register which can be modified by
the “Page Address Set” instruction only. The Page Address must be set before accessing DDRAM content. Page Address
“8” is a special RAM area for the icons with only one valid bit: D0.
Column Address Circuit
The column address of DDRAM is specified by the Column Address Set command. The column address is increased (+1)
after each display data access (read/write). This allows MPU accessing DDRAM content continuously. This feature stops at
the end of each page (Column Address “83h”) because the Column Address and Page Address circuits are independent.
For example, both Page Address and Column Address should be assigned for changing the DDRAM pointer from
(Page-0, Column-83h) to (Page-1, Column-0).
Furthermore, Register MX and MY makes it possible to invert the relationship between the DDRAM and the outputs
(COM/SEG). It is necessary to rewrite the display data into DDRAM after changing MX setting.
Ver 1.4b
16/49
2009/02/04
ST7567
The relation between DDRAM and outputs with different MX or MY setting is shown below.
Fig 9.
Ver 1.4b
DDRAM and Output Map (COM/SEG)
17/49
2009/02/04
ST7567
Line Address Circuit
The Line Address Circuit incorporates a counter and a Line Address register which is changed only by the “Display Start
Line Set” instruction. This circuit assigns DDRAM a Line Address corresponding to the first display line (COM0). Therefore,
by setting Line Address repeatedly, ST7567 can realize the screen scrolling without changing the contents of DDRAM as
shown in Fig 10. The last common is always the COMS (common output for the icons). That means the icons will never
7B
7C
7D
7E
7F
80
81
82
83
08
07
06
05
04
03
02
01
00
83
82
81
80
7F
7E
7D
7C
7B
00
01
02
03
04
05
06
07
08
scroll with the general display data.
64 Lines
Line Address (Hex), Start Line S[6:0] = 0x1C
Ver 1.4b
232
233
234
235
236
237
238
239
240
S123
S124
S125
S126
S127
S128
S129
S130
S131
S0
S1
S2
S3
S4
S5
S6
S7
S8
109
110
111
112
113
114
115
116
117
Start
Fig 10.
Start Line Function
18/49
2009/02/04
ST7567
Display Data Latch Circuit
The display data latch circuit latches temporarily display data of each segment output which will be output at the next clock.
The special functions such as reverse display, display OFF and display all points ON only change the data in the latch and
the content in the Display Data RAM is not changed.
Oscillation Circuit
The built-in oscillation circuit generates the system clock for the liquid crystal driving circuit. The oscillation circuit is enabled
after initializing ST7567. The clock will not be output to reduce the power consumption.
Liquid Crystal Driver Power Circuit
The built-in power circuits generate the voltage levels which are necessary to drive the liquid crystal. It consumes low power
with the fewest external components. The built-in power system has voltage booster, voltage regulator and voltage follower
circuits. Before power ST7567 OFF, a Power OFF procedure is needed (please refer to the OPERATION FLOW section).
External Components of Power Circuit
The recommended external power components need only 2 capacitors. The detailed values of these two capacitors are
determined by the panel size and loading.
IC Internal
IC External
V0
Generator
V0
C2
VG
Grnerator
VG
C1
VDD2
VSS2
VSS2
XV0
Generator
Fig 11.
R1
XV0
C1: 0.1uF~1.0uF
(Non-Polar/6V)
C2: 0.1uF~1.0uF
(Non-Polar/16V)
R1: Reserved
(Default NC)
Power Circuit
Regulator Circuit
The built-in high accuracy regulation circuit has 8 regulation ratios and each one has 64 EV-levels for voltage adjustment.
Without additional external component, the output voltage can be changed by instructions such as “Regulation Ratio” and
“Set EV”. The detailed setting method can be found in the INSTRUCTION DESCRIPTION section.
Ver 1.4b
19/49
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ST7567
RESET CIRCUIT
Setting RSTB to “L” can initialize internal function. While RSTB is “L”, no instruction except read status can be accepted.
RSTB pin must connect to the reset pin of MPU and initialization by RSTB pin is essential before operating. Please note the
hardware reset is not same as the software reset. When RSTB becomes “L”, the hardware reset procedure will start. When
RESET instruction is executed, the software reset procedure will start. The procedure is listed below:
Procedure
Hardware Reset
Software Reset
Display OFF: D=0, all SEGs/COMs output at VSS
V
X
Normal Display: INV=0, AP=0
V
X
SEG Normal Direction: MX=0
V
X
Clear Serial Counter and Shift Register (if using Serial Interface)
V
X
Bias Selection: BS=0
V
X
Booster Level BL=0
V
X
Exit Power Saving Mode
V
X
Power Control OFF: VB=0, VR=0, VF=0
V
X
Exit Read-modify-Write mode
V
V
Start Line S[5:0]=0
V
V
Column Address X[7:0]=0
V
V
Page Address Y[3:0]=0
V
V
COM Normal Direction: MY=0
V
V
V0 Regulation Ratio RR[2:0]=(1,0,0)
V
V
EV[5:0]=(1,0,0,0,0,0)
V
V
Exit Test Mode
V
V
After power-on, RAM data are undefined and the display status is “Display OFF”. It’s better to initialize whole DDRAM (ex:
fill all 00h or write the display pattern) before turning the Display ON. Besides, the power is not stable at the time that the
power is just turned ON. A hardware reset is needed to initialize those internal registers after the power is stable.
Ver 1.4b
20/49
2009/02/04
ST7567
8. INSTRUCTION TABLE
COMMAND BYTE
A0
R/W
(RWR)
D7
D6
D5
D4
D3
D2
D1
D0
(1) Display ON/OFF
0
0
1
0
1
0
1
1
1
D
D=1, display ON
D=0, display OFF
(2) Set Start Line
0
0
0
1
S5
S4
S3
S2
S1
S0
Set display start line
(3) Set Page Address
0
0
1
0
1
1
Y3
Y2
Y1
Y0
Set page address
(4)
Set Column Address
0
0
0
0
0
1
X7
X6
X5
X4
Set column address (MSB)
0
0
0
0
0
0
X3
X2
X1
X0
Set column address (LSB)
(5) Read Status
0
1
0
MX
D
RST
0
0
0
0
(6) Write Data
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write display data to RAM
(7) Read Data
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read display data from RAM
(8) SEG Direction
0
0
1
0
1
0
0
0
0
MX
Set scan direction of SEG
MX=1, reverse direction
MX=0, normal direction
(9) Inverse Display
0
0
1
0
1
0
0
1
1
INV
INV =1, inverse display
INV =0, normal display
(10) All Pixel ON
0
0
1
0
1
0
0
1
0
AP
AP=1, set all pixel ON
AP=0, normal display
(11) Bias Select
0
0
1
0
1
0
0
0
1
BS
Select bias setting
0=1/9; 1=1/7 (at 1/65 duty)
(12)
Read-modify-Write
0
0
1
1
1
0
0
0
0
0
Column address increment:
Read:+0 , Write:+1
INSTRUCTION
DESCRIPTION
Read IC Status
(13) END
0
0
1
1
1
0
1
1
1
0
Exit Read-modify-Write mode
(14) RESET
0
0
1
1
1
0
0
0
1
0
Software reset
(15) COM Direction
0
0
1
1
0
0
MY
-
-
-
Set output direction of COM
MY=1, reverse direction
MY=0, normal direction
(16) Power Control
0
0
0
0
1
0
1
VB
VR
VF
Control built-in power circuit
ON/OFF
(17) Regulation Ratio
0
0
0
0
1
0
0
RR2
RR1
RR0 Select regulation resistor ratio
0
0
1
0
0
0
0
0
0
0
0
0
0
EV5
EV4
EV3
EV2
EV1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
BL
(20) Power Save
0
0
(21) NOP
0
0
1
1
1
0
0
0
1
1
No operation
(22) Test
0
0
1
1
1
1
1
1
1
-
Do NOT use.
Reserved for testing.
(18) Set EV
(19) Set Booster
1
Double command!! Set
EV0 electronic volume (EV) level
Compound Command
Double command!!
Set booster level:
BL=0: 4X
BL=1: 5X
Display OFF + All Pixel ON
Note: Symbol “-” means this bit can be “H” or “L”.
Ver 1.4b
21/49
2009/02/04
ST7567
9. INSTRUCTION DESCRIPTION
Display ON/OFF
The D flag selects the display mode.
D7
A0
R/W(RWR)
0
0
1
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
D
D=1: Normal Display Mode.
D=0: Display OFF. All SEGs/COMs output with VSS.
Set Start Line
This instruction sets the line address of the Display Data RAM to determine the initial display line. The display data of the
specified line address is displayed at the top row (COM0) of the LCD panel.
D7
D6
D5
D4
D3
D2
D1
D0
A0
R/W(RWR)
0
0
0
1
S5
S4
S3
S2
S1
S0
S5
S4
S3
S2
S1
S0
Line address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
2
0
:
0
:
0
:
0
:
1
:
1
:
3
:
1
1
1
1
1
1
1
1
0
1
1
0
61
62
1
1
1
1
1
1
63
D3
D2
D1
D0
Y3
Y2
Y1
Y0
Set Page Address
Y [3:0] defines the Y address vector address of the display RAM.
A0
R/W(RWR)
D7
D6
D5
D4
0
0
1
0
1
1
Y3
Y2
Y1
Y0
Page Address
Valid Bit
0
0
0
0
0
0
0
1
Page0
Page1
D0~ D7
D0~ D7
0
:
0
:
1
:
0
:
Page2
:
D0~ D7
:
0
0
1
1
1
1
0
1
Page6
Page7
D0~ D7
D0~ D7
1
0
0
0
Page8 (icon page)
D0
Ver 1.4b
22/49
2009/02/04
ST7567
Set Column Address
The range of column address is 0…131. The parameter is separated into 2 instructions. The column address is increased
(+1) after each byte of display data access (read/write). This allows MPU accessing DDRAM content continuously. This
feature stops at the end of each page (Column Address “83h”).
D7
D6
D5
D4
D3
D2
D1
D0
A0
R/W(RWR)
0
0
0
0
0
1
X7
X6
X5
X4
A0
R/W(RWR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
X3
X2
X1
X0
D1
D0
0
0
X7
X6
X5
X4
X3
X2
X1
X0
Column address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
2
3
:
1
:
0
:
0
:
0
:
0
:
0
:
0
:
1
:
129
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
120
131
Read Status
Read the internal status of ST7567. The read function is not available in serial interface mode.
D7
D6
D5
D4
D3
D2
A0
R/W(RWR)
0
1
0
MX
D
Flag
MX
D
RST
RST
0
0
Description
MX=0: Normal direction (SEG0->SEG131)
MX=1: Reverse direction (SEG131->SEG0)
D=0: Display ON
D=1: Display OFF
RST=1: During reset (hardware or software reset)
RST=0: Normal operation
Write Data
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and
page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data
to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written.
A0
R/W(RWR)
D7
D6
D5
D4
D3
D2
D1
D0
1
0
Write Data
Read Data
8-bit data of Display Data from the RAM location specified by the column address and page address can be read to the
microprocessor. The read function is not available in serial interface mode.
A0
R/W(RWR)
D7
D6
D5
D4
D3
D2
D1
D0
1
Ver 1.4b
1
Read Data
23/49
2009/02/04
ST7567
SEG Direction
A0
R/W(RWR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
1
0
0
0
0
MX
Flag
MX
Description
MX=0: Normal direction (SEG0->SEG131)
MX=1: Reverse direction (SEG131->SEG0)
Inverse Display
This instruction changes the selected and non-selected voltage of SEG. The display will be inversed (white -> Black, Black
-> White) while the display data in the Display Data RAM is never changed.
A0
R/W(RWR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
1
0
0
1
1
INV
Flag
INV
Description
INV=0: Normal display
INV =1: Inverse display
All Pixel ON
This instruction will let all segments output the selected voltage and make all pixels turned ON.
A0
R/W(RWR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
1
0
0
1
0
AP
D3
D2
D1
D0
0
0
1
BS
Flag
AP
Description
AP =0: Normal display
AP =1: All pixels ON
Bias Select
Select LCD bias ratio of the voltage required for driving the LCD.
D7
D6
D5
D4
A0
R/W(RWR)
0
Duty
0
1
0
1
0
Reference LCD Bias Voltage (1/65 Duty with 1/9 Bias)
Bias
BS=0
BS=1
Symbol
Bias Voltage
1/65
1/9
1/7
1/49
1/33
1/8
1/6
1/6
1/5
V0
VG
V0
2/9 x V0
1/55
1/8
1/6
VM
VSS
1/9 x V0
VSS
Please Note:
* VG range: 1.24V ≤ VG < VDD2.
* VM range: 0.62V ≤ VM < VDD2.
Ver 1.4b
24/49
2009/02/04
ST7567
Read-modify-Write
This command is used paired with the “END” instruction. Once this command has been input, the display data read
operation will not change the column address, but only the display data write operation will increase the column address
(X[7:0]+1). This mode is maintained until the END command is input. This function makes it possible to reduce the load on
the MPU when there are repeating data changes in a specified display region, such as a blanking cursor.
D7
D6
D5
D4
D3
D2
D1
D0
A0
R/W(RWR)
0
0
1
1
1
0
0
0
0
0
In Read-modify-Write mode, other instructions aside from display data read/write commands can also be used.
Read-Modify-Write
Page Address Set
Column Address Set
Read-Modify-Write Cycle
Dummy Read
Data Read
No
Modify Data
Data Write (at same Address)
Finished?
Yes
Done
END
When the END command is input, the Read-modify-Write mode is released and the column address returns to the address
it was when the Read-modify-Write instruction was entered.
A0
R/W(RWR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
1
0
1
1
1
0
RESET
This instruction resets Start Line (S[5:0]), Column Address (X[7:0]), Page Address (Y[3:0]) and COM Direction (MY) to their
default setting. Please note this instruction is not complete same as hardware reset (RSTB=L) and cannot initialize the
built-in power circuit which is initialized by the RSTB pin. The detailed information is in “Section RESET CIRCUIT”.
A0
R/W(RWR)
D7
D6
D5
D4
D3
D2
D1
D0
0
Ver 1.4b
0
1
1
1
0
25/49
0
0
1
0
2009/02/04
ST7567
COM Direction
This instruction controls the common output status which changes the vertical display direction. The detailed information
can be found in Fig 9.
D7
D6
D5
D4
D3
D2
D1
D0
A0
R/W(RWR)
0
0
1
1
0
Flag
MY
0
MY
-
-
-
Description
MY=0: Normal direction (COM0->COM63)
MY=1: Reverse direction (COM63->COM0)
Power Control
This instruction controls the built-in power circuits. Typically, these 3 flags are turned ON at the same time.
D7
D6
D5
D4
D3
D2
D1
A0
R/W(RWR)
0
0
0
0
1
Flag
VB
VR
VF
0
D0
1
VB
VR
VF
D3
D2
D1
D0
0
RR2
RR1
RR0
Description
VB=0: Built-in Booster OFF
VB=1: Built-in Booster ON
VR=0: Built-in Regulator OFF
VR=1: Built-in Regulator ON
VF=0: Built-in Follower OFF
VF=1: Built-in Follower ON
Regulation Ratio
This instruction controls the regulation ratio of the built-in regulator.
A0
R/W(RWR)
D7
D6
D5
D4
0
0
0
0
1
RR2
RR1
RR0
Regulation Ratio (RR)
0
0
0
0
0
1
3.0
3.5
0
0
1
1
0
1
4.0
4.5
1
1
0
0
0
1
5.0
5.5
1
1
1
1
0
1
6.0
6.5
0
The operation voltage (V0) calculation formula is shown below: (RR comes from Regulation Ratio, EV comes from EV[5:0])
V0 = RR X [ 1 – (63 – EV) / 162 ] X 2.1, or V0 = RR X [ ( 99 + EV ) / 162 ] X 2.1
Ver 1.4b
SYMBOL
REGISTER
VALUE
RR
EV
RR[2:0]
EV[5:0]
3, 3.5, 4, 4.5, 5, 5.5, 6 and 6.5
0~63
26/49
2009/02/04
ST7567
Set EV
This is double byte instruction. The first byte set ST7567 into EV adjust mode and the following instruction will change the
EV setting. That means these 2 bytes must be used together. They control the electronic volume to adjust a suitable V0
voltage for the LCD.
D7
D6
D5
D4
D3
D2
D1
D0
A0
R/W(RWR)
0
0
0
0
1
0
0
0
0
EV5
0
EV4
0
EV3
0
EV2
0
EV1
1
EV0
Electronic Volume Set
Set EV (byte-1)
(0x81)
Set EV (byte-2)
(depends on requirement)
No
Set Complete?
Yes
Done
The maximum voltage that can be generated is dependent on the VDD2 voltage and the loading of LCD module. There are
8 V0 voltage curve can be selected. It is recommended the EV should be close to the center (1FH) for easy contrast
adjustment. Please refer to the “Selection of Application Voltage” section for detailed information.
EV[5:0] and RR[2:0] vs. V0 Voltage
Fig 21 Setting V0 Voltage
Ver 1.4b
27/49
2009/02/04
ST7567
Power Save (Compound Instruction)
st
nd
This is compound instruction. The 1 instruction is Display OFF (D=0) and the 2 instruction is All Pixel ON (AP=1). The
Power Save mode starts the following procedure: (the display data and register settings are still kept except D-Flag and
AP-Flag)
1.
Stops internal oscillation circuit;
2.
Stops the built-in power circuits;
3.
Stops the LCD driving circuits and keeps the common and segment outputs at VSS.
Normal Mode
Power Save Mode
Display OFF (AEH)
Cancel All Pixel ON (A4H)
All Pixel ON (A5H)
Display ON (AFH)
Power Save Mode
Normal Mode
Enter Power Save Mode
Exit Power Save Mode
After exiting Power Save mode, the settings will return to be as they were before.
Set Booster
This is double byte instruction. The first byte set ST7567 into booster configuration mode and the following instruction will
change the booster setting. That means these 2 bytes must be used together. They control the built-in booster circuit to
provide the power source of the built-in regulator. ST7567 booster is built-in booster capacitors. The only external
component is a keep capacitor between V0 and XV0. Booster level can be changed with instruction only without changing
hardware connection.
A0
R/W(RWR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
BL
D2
D1
D0
0
1
1
Booster Ratio Set
Set Booster (byte-1)
(F8H)
BL
Boost Level
0
X4
1
X5
Set Booster (byte-2)
(depends on requirement)
Set Complete?
No
Yes
Done
NOP
“No Operation” instruction. ST7567 will do nothing when receiving this instruction.
A0
R/W(RWR)
D7
D6
D5
D4
D3
0
0
1
1
1
0
0
Test
The test mode is reserved for IC testing. Please don’t use this instruction. If the test mode is enabled accidentally, it can be
cleared by: issuing an “L” pulse on RSTB pin, issuing RESET instruction or issuing NOP instruction.
A0
R/W(RWR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Note: “-” means “1” or “0”.
Ver 1.4b
1
1
1
1
28/49
1
1
1
-
2009/02/04
ST7567
10. OPERATION FLOW
This section introduces some reference operation flows.
Power ON
R
R
n
O
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F
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Power ON
Case 1: RSTB=L while Power ON
Wait power stable, t>1ms
(depends on system power)
Keep RSTB=L …*1
Wait reset start, t>5us
Set RSTB=H …*1
Wait reset finished, t>5us
Default State ……*2
Function Set (by user)
(11) Bias Select
(8) SEG Direction
(15) COM Direction
Function Set (by user)
(17) Regulation Ratio
(18) Set EV
Arrange to execute all these
procedures from releasing
the reset state to setting the
Power Control within 5ms.
In case of other models,
execute these procedures
from turning ON the power
to setting the Power Control
in 5ms.
……*3
Function Set (by user)
(16) Power Control
Case 2: RSTB=H while Power ON
VDD1 * 50%
VDDI
VDD1 * 90%
(VDD1)
tON-V2
VDDA
VDD2 * 90%
VDD2 * 50%
(VDD2,VDD3)
Initialize DDRAM (Page 0~8)
tRW
RSTB
VIL
tON-RST
[ Display ON ]
Normal Operating
Note: The detailed description can be found in the respective sections listed below.
1.
Please refer to the timing specification of tRW and tR.
2.
Refer to Section RESET CIRCUIT.
3.
The 5ms requirement depends on the characteristics of LCD panel and the external component of the power circuit. It
is recommended to check with the real products with external component.
4.
The detailed instruction functionality is described in Section 9. INSTRUCTION DESCRIPTION;
5.
Power stable is defined as the time that the later power (VDDI or VDDA) reaches 90% of its rated voltage.
Timing Requirement:
Item
VDDA power delay
Symbol
Requirement
tON-V2
0 ≤ tON-V2
Note
Applying VDDI and VDDA in any order will not damage IC.
If RSTB is Low, High or unstable during power ON, a
successful hardware reset by RSTB is required after VDDI is
stable.
RSTB input time
tON-RST
No Limitation
RSTB=L can be input at any time after power is stable.
tRW & tR should match the timing specification of RSTB.
To prevent abnormal display, the recommended timing is:
0 ≤ tON-RST ≤ 30 ms.
The requirement listed here is to prevent abnormal display on LCD module.
Ver 1.4b
29/49
2009/02/04
ST7567
Display Data
Write Display Data (After Initialized)
Function setup by command
(user setting)
(2) Display Start Line Set
(3) Page Address Set
(4) Column Address Set
Data setup by Data Write
(6) Display Data Write
Function setup by command
(user setting)
(1) Display ON/OFF
End of Write Display Data
Notes: Reference items
1.
The detailed instruction functionality is described in Section 9. INSTRUCTION DESCRIPTION;
2.
It is recommended to write display data (initialize DDRAM) before Display ON.
Refresh
It is recommended to use the refresh sequence regularly in a specified interval.
Ver 1.4b
30/49
2009/02/04
ST7567
Power-Save Flow and Sequence
ENTERING THE POWER SAVE MODE
EXITING THE POWER SAVE MODE
Normal Mode
Power Save Mode
Display OFF (AEH)
Cancel All Pixel ON (A4H)
All Pixel ON (A5H)
Display ON (AFH)
Power Save Mode
Normal Mode
Enter Power Save Mode
Exit Power Save Mode
INTERNAL SEQUENCE of EXIT POWER SAVE MODE
After receiving “PD=0”, the internal circuits (Power) will starts the following procedure.
Note:
1.
The power stable time is determined by LCD panel loading.
2.
The power stable time in this figure is base on: LCD Panel Size = 1.4” with C1=1uF, C2=1uF (VDD=2.7V, Vop=9V).
Ver 1.4b
31/49
2009/02/04
ST7567
Power OFF Flow and Sequence
In power save mode, LCD outputs are fixed to VSS and all analog outputs are discharged. The power can be turned OFF
after ST7567 is in the power save mode. The power save mode can be triggered by the following two methods.
R
R
n
P
o
w
O
F
F
F
o
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Reeefffeeerrreeen
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Po
ow
weeerrr O
OF
FF
FF
Flllo
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CASE 1: Use Power Save Instruction
Normal Mode
Display OFF (AEH)
All Pixel ON (A5H)
Wait 250ms
Turn VDD1~VDD3 OFF
Power OFF
Power OFF Flow
Instruction Flow
After the built-in power circuits are OFF and completely
discharged, the power (VDDI, VDDA) can be removed.
CASE 2: Use Hardware Reset Function
Normal Mode
Set RSTB=L (wait > tRW)
Set RSTB=H
Wait 250ms
Turn VDD1~VDD3 OFF
Power OFF
Power OFF Flow
Instruction Flow
After the built-in power circuits are OFF and completely
discharged, the power (VDDI, VDDA) can be removed.
Note:
1.
tPOFF: Internal Power discharge time. => 250ms (max).
2.
tV2OFF: Period between VDDI and VDDA OFF time. => 0 ms (min).
3.
It is NOT recommended to turn VDDI OFF before VDDA. Without VDDI, the internal status cannot be guaranteed and
internal discharge-process maybe stopped. The un-discharged power maybe flows into COM/SEG output(s) and the
liquid crystal in panel maybe polarized.
4.
IC will NOT be damaged if either VDDI or VDDA is OFF while another is ON.
5.
The timing is dependent on panel loading and the external capacitor(s).
6.
The timing in these figures is base on the condition that: LCD Panel Size = 1.4” with C1=1uF, C2=1uF.
7.
When turning VDDA OFF, the falling time should follow the specification:
20ms ≤ tPfall ≤ 0.2sec
Ver 1.4b
32/49
2009/02/04
ST7567
11. LIMITING VALUES
In accordance with the Absolute Maximum Rating System; please refer to notes 1 and 2.
Symbol
Conditions
Unit
Digital Power Supply Voltage
Parameter
VDD1
-0.3 ~ 3.6
V
Analog Power supply voltage
VDD2, VDD3
-0.3 ~ 3.6
V
LCD Power supply voltage
V0-XV0
-0.3 ~ 16
V
LCD Power supply voltage
VG
-0.3 ~ 3.6
V
LCD Power supply voltage
VM
-0.3 ~ VDD2
V
Vi
-0.3 ~ VDD1+0.3
Input Voltage
Operating temperature
Storage temperature
TOPR
TSTR
V
–30 to +85
°
C
–55 to +125
°
C
Notes
1.
Stresses above those listed under Limiting Values may cause permanent damage to the device.
2.
Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to
VSS unless otherwise noted.
3.
Insure the voltage levels of V0, VDD2, VG, VM, VSS and XV0 always match the correct relation:
V0 ≥ VDD2 > VG > VM > VSS ≥ XV0
Ver 1.4b
33/49
2009/02/04
ST7567
12. HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
13. DC CHARACTERISTICS
°
°
VSS=0V; Tamb = -30 C to +85 C; unless otherwise specified.
Item
Symbol
Condition
Rating
Min.
Typ.
Max.
Unit
Applicable
Pin
Operating Voltage (1)
VDD1
1.7
—
3.3
V
VDD1
Operating Voltage (2)
VDD2
2.4
—
3.3
V
VDD2
Operating Voltage (3)
VDD3
2.4
—
3.3
V
VDD3
Input High-level Voltage
VIHC
0.7 x VDD1
—
VDD1
V
Input Low-level Voltage
VILC
VSS1
—
0.3 x VDD1
V
Output High-level Voltage
VOHC
IOUT=1mA, VDD1=1.8V
0.8 x VDD1
—
VDD1
V
D[7:0]
Output Low-level Voltage
VOLC
IOUT=-1mA, VDD1=1.8V
VSS1
—
0.2 x VDD1
V
D[7:0]
MPU
Interface
MPU
Interface
MPU
Input Leakage Current
ILI
-1.0
—
1.0
µA
Output Leakage Current
ILO
-3.0
—
3.0
µA
—
0.6
0.8
KΩ
COMx
—
1.3
1.5
KΩ
SEGx
70
75
80
Hz
Vop=8.5V,
Liquid Crystal Driver ON
Resistance
RON
°
Ta=25 C
ΔV=0.85V
VG=1.9V,
ΔV=0.19V
Frame Frequency
Ver 1.4b
FR
Duty=1/65, Vop=8.5V
Ta = 25°C
34/49
Interface
MPU
Interface
2009/02/04
ST7567
Current consumption: During Display, with internal power system, current consumed by whole IC (bare die).
Test Pattern
Symbol
Condition
Rating
Unit
Min.
Typ.
Max.
—
150
300
µA
—
95
190
uA
—
8
16
µA
Note
VDD1=VDD2=VDD3=3.0V,
Display Pattern: SNOW
(Static)
ISS
Booster X5
VOP = 8.5 V, Bias=1/9
°
Ta=25 C
VDD1=VDD2=VDD3=3.0V,
Display OFF
ISS
Booster X5
VOP = 8.5 V, Bias=1/9
°
Ta=25 C
Power Down
ISS
VDD1=VDD2=VDD3=3.0V,
°
Ta=25 C
Note:
The Current Consumption is DC characteristics
Ver 1.4b
35/49
2009/02/04
ST7567
14. TIMING CHARACTERISTICS
System Bus Timing for 6800 Series MPU
°
(VDD1 = 3.3V , Ta =25 C)
Min.
Max.
tAW6
0
—
tAH6
10
—
System cycle time
tCYC6
240
—
Enable L pulse width (WRITE)
tEWLW
80
—
tEWHW
80
—
Enable L pulse width (READ)
tEWLR
80
—
Enable H pulse width (READ)
tEWHR
140
Write data setup time
tDS6
40
—
Write data hold time
tDH6
10
—
Item
Address setup time
Address hold time
Enable H pulse width (WRITE)
Read data access time
Signal
A0
E
D[7:0]
Read data output disable time
Symbol
Condition
tACC6
CL = 16 pF
—
70
tOH6
CL = 16 pF
5
50
Unit
ns
°
(VDD1 = 2.8V , Ta =25 C)
Item
Address setup time
Signal
Symbol
Condition
Min.
Max.
tAW6
0
—
tAH6
0
—
System cycle time
tCYC6
400
—
Enable L pulse width (WRITE)
tEWLW
220
—
tEWHW
180
—
Enable L pulse width (READ)
tEWLR
220
—
Enable H pulse width (READ)
tEWHR
180
—
tDS6
40
—
Address hold time
Enable H pulse width (WRITE)
A0
E
Write data setup time
Write data hold time
Read data access time
Read data output disable time
Ver 1.4b
D[7:0]
20
—
tACC6
tDH6
CL = 16 pF
—
140
tOH6
CL = 16 pF
10
100
36/49
Unit
ns
2009/02/04
ST7567
°
(VDD1 = 1.8V , Ta =25 C)
Item
Address setup time
Address hold time
Signal
A0
Symbol
Condition
tAW6
Min.
Max.
0
—
tAH6
0
—
System cycle time
tCYC6
640
—
Enable L pulse width (WRITE)
tEWLW
360
—
tEWHW
280
—
Enable L pulse width (READ)
tEWLR
360
—
Enable H pulse width (READ)
tEWHR
280
—
tDS6
80
—
tDH6
20
—
Enable H pulse width (WRITE)
E
Write data setup time
Write data hold time
Read data access time
Read data output disable time
D[7:0]
tACC6
CL = 16 pF
—
240
tOH6
CL = 16 pF
10
200
Unit
ns
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr + tf) ≦ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified.
*2 All timing is specified using 20% and 80% of VDD1 as the reference.
*3 tEWLW and tEWLR are specified as the overlap between CSB being “L” and E.
Ver 1.4b
37/49
2009/02/04
ST7567
System Bus Timing for 8080 Series MPU
°
(VDD1 = 3.3V , Ta =25 C)
Item
Address setup time
Address hold time
Signal
A0
System cycle time
/WR L pulse width (WRITE)
/WR
/WR H pulse width (WRITE)
/RD L pulse width (READ)
/RD H pulse width (READ)
RD
WRITE Data setup time
WRITE Data hold time
READ access time
D[7:0]
READ Output disable time
Symbol
Condition
tAW8
Min.
Max.
0
—
tAH8
10
—
tCYC8
240
—
tCCLW
80
—
tCCHW
80
—
tCCLR
140
—
tCCHR
80
tDS8
40
—
tDH8
20
—
tACC8
CL = 16 pF
—
70
tOH8
CL = 16 pF
5
50
Unit
ns
°
(VDD1 = 2.8V , Ta =25 C)
Item
Address setup time
Address hold time
Signal
A0
System cycle time
/WR L pulse width (WRITE)
/WR
/WR H pulse width (WRITE)
/RD L pulse width (READ)
/RD H pulse width (READ)
RD
WRITE Data setup time
WRITE Data hold time
READ access time
READ Output disable time
Ver 1.4b
D[7:0]
Symbol
Condition
Min.
Max.
tAW8
0
—
tAH8
0
—
tCYC8
400
—
tCCLW
220
—
tCCHW
180
—
tCCLR
220
—
tCCHR
180
—
tDS8
40
—
tDH8
20
—
tACC8
CL = 16 pF
—
140
tOH8
CL = 16 pF
10
100
38/49
Unit
ns
2009/02/04
ST7567
°
(VDD1 = 1.8V , Ta =25 C)
Item
Address setup time
Address hold time
Signal
A0
System cycle time
/WR L pulse width (WRITE)
/WR
/WR H pulse width (WRITE)
/RD L pulse width (READ)
/RD H pulse width (READ)
RD
WRITE Data setup time
WRITE Data hold time
READ access time
READ Output disable time
D[7:0]
Symbol
Condition
tAW8
Min.
Max.
0
—
tAH8
0
—
tCYC8
640
—
tCCLW
360
—
tCCHW
280
—
tCCLR
360
—
tCCHR
280
tDS8
80
—
tDH8
20
—
tACC8
CL = 16 pF
—
240
tOH8
CL = 16 pF
10
200
Unit
ns
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr + tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.
*2 All timing is specified using 20% and 80% of VDD1 as the reference.
*3 tCCLW and tCCLR are specified as the overlap between CSB being “L” and WR and RD being at the “L” level.
Ver 1.4b
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2009/02/04
ST7567
System Bus Timing for 4-Line Serial Interface
First bit
Last bit
°
(VDD1 = 3.3V , Ta =25 C)
Item
Signal
Serial clock period
SCLK “H” pulse width
SCLK
SCLK “L” pulse width
Address setup time
Address hold time
Data setup time
A0
SDA
Data hold time
CSB-SCLK time
CSB-SCLK time
CSB
Symbol
Min.
Max.
tSCYC
Condition
50
—
tSHW
25
—
tSLW
25
—
tSAS
20
—
tSAH
10
—
tSDS
20
—
tSDH
10
—
tCSS
20
—
tCSH
40
—
Unit
ns
°
(VDD1 = 2.8V , Ta =25 C)
Item
Signal
Serial clock period
SCLK “H” pulse width
SCLK
Symbol
Condition
Min.
Max.
tSCYC
100
—
tSHW
50
—
SCLK “L” pulse width
tSLW
50
—
Address setup time
tSAS
30
—
tSAH
20
—
tSDS
30
—
tSDH
20
—
tCSS
30
—
tCSH
60
—
Address hold time
Data setup time
Data hold time
CSB-SCLK time
CSB-SCLK time
Ver 1.4b
A0
SDA
CSB
40/49
Unit
ns
2009/02/04
ST7567
°
(VDD1 = 1.8V , Ta =25 C)
Item
Signal
Serial clock period
SCLK “H” pulse width
SCLK
SCLK “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CSB-SCLK time
CSB-SCLK time
A0
SDA
CSB
Symbol
Condition
Min.
Max.
tSCYC
200
—
tSHW
80
—
tSLW
80
—
tSAS
60
—
tSAH
30
—
tSDS
60
—
tSDH
30
—
tCSS
40
—
tCSH
100
—
Unit
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD1 as the standard.
Ver 1.4b
41/49
2009/02/04
ST7567
Hardware Reset Timing
tRW
RSTB
tR
Internal
Status
During Reset ...
Reset Finished
°
(VDD1 = 3.3V , Ta =25 C)
Item
Reset time
Reset “L” pulse width
Symbol
Condition
Min.
Max.
tR
—
1.0
tRW
1.0
—
Unit
us
°
(VDD1 = 2.8V , Ta =25 C)
Item
Reset time
Reset “L” pulse width
Symbol
Condition
Min.
Max.
tR
—
2.0
tRW
2.0
—
Unit
us
°
(VDD1 = 1.8V , Ta =25 C)
Item
Reset time
Reset “L” pulse width
Ver 1.4b
Symbol
Condition
Min.
Max.
tR
—
3.0
tRW
3.0
—
42/49
Unit
us
2009/02/04
ST7567
APPLICATION NOTE
Application Circuits
88
89
86
76
87
6800 Interface
Booster X4
Duty: 1/33
Vop: 5.5~6.7V
Bias: 1/6
C1=0.1uF~1uF (6V)
77
75
VDD3
C2=0.1uF~1uF (16V)
VDD2
C3=10pF~100pF (6V)
VDD1
108
SEL2
110
VSSL
109
SEL1
PSB
C86
VDDH
VSSL
64
59
56
Vref
T[5]
T[4]
T[3]
T[2]
T[1]
TFCOM
T[8]
T[7]
T[6]
VGout
54
VGs
VG
VGin
C1
VGin
VMO
VMO
TP3
XV0in
XV0in
47
XV0
XV0s
XV0out
XV0out
TP1
C2
V0out
V0out
42
V0s
V0in
V0in
VSS2
VSS2
VSS2
TP2
V0
R1
Default
NC
VSS
VSS3
VSS1
34
VSS1
VDD3
VDD2
VDD2
VDD2
VDD
VDD1
VDD1
D7
D7
D6
D6
D5
D4
D3
D3
D2
D2
D1
20
D0
D0
ERD
E
240
A0
242
RSTB
CSB
13
11
261
260
Ver 1.4b
1
D1
VDDH
RWR
241
D5
D4
CL
R/W
A0
RSTB
C3
CSB
Default
NC
12
2
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2009/02/04
ST7567
88
89
86
76
87
8080 Interface
Booster X4
Duty: 1/55
Vop: 6.0~7.5V
Bias: 1/6
C1=0.1uF~1uF (6V)
77
75
VDD3
C2=0.1uF~1uF (16V)
VDD2
C3=10pF~100pF (6V)
VDD1
108
SEL2
110
VSSL
109
SEL1
PSB
C86
VDDH
VSSL
64
59
56
Vref
T[5]
T[4]
T[3]
T[2]
T[1]
TFCOM
T[8]
T[7]
T[6]
VGout
54
VGs
VG
VGin
C1
VGin
VMO
VMO
TP3
XV0in
XV0in
47
XV0
XV0s
XV0out
XV0out
TP1
C2
V0out
V0out
42
V0s
V0in
V0in
VSS2
VSS2
VSS2
TP2
V0
R1
Default
NC
VSS
VSS3
VSS1
34
VSS1
VDD3
VDD2
VDD2
VDD2
VDD
VDD1
VDD1
D7
D7
D6
D6
D5
D4
D3
D3
D2
D2
D1
20
D0
240
D0
ERD
/RD
A0
RSTB
242
13
11
261
260
Ver 1.4b
1
D1
VDDH
RWR
241
D5
D4
/RW
A0
CSB
RSTB
C3
CL
CSB
Default
NC
12
2
44/49
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ST7567
Ver 1.4b
45/49
2009/02/04
ST7567
Selection of Application Voltage
Referential LCD Module Setting
VDD1=2.8V, VDD2=VDD3=2.8V, Panel Size=1.4”, Ta=25°C
Duty
Booster
1/65
X5
1/55
X5
1/49
X5
1/33
X5
Vop
Bias
8.5 ~ 9.5
1/9
6.5 ~ 7.5
1/7
7.5 ~ 8.5
1/8
5.5 ~ 6.5
1/6
7.5 ~ 8.5
1/8
5.5 ~ 6.5
1/6
5.5 ~ 6.5
1/6
4.5 ~ 5.5
1/5
It is recommended to reserve some range for user adjustment and temperature effect.
Note:
Positive Booster: (VDD2 x BL x BE) ≥ V0 or (VDD2 x BL x BE) ≥ Vop;
Negative Booster: [–VDD2 x (BL – 1) x BE] ≤ XV0 or [VDD2 x (BL – 1) x BE] ≥ (Vop – VG),
where VG = Vop x 2 / N;
Vop requirement: [VDD2 x (BL – 1) x BE] ≥ [Vop x (N – 2) / N] or [Vop ≤ VDD2 x (BL – 1) x BE x N / (N – 2)].
BL is the booster stage and BE is the booster efficiency. Referential values are listed below: (assume
VDD2=VDD3=2.8V)
Module Size ≤ 1.4”: BE=80% (Typical);
Module Size = 1.4”~1.8”: BE=76% (Typical).
Actual BE should be determined by module loading and ITO resistance value.
1.6 ≤ VG < VDD2. Recommend VG is: VDD2-VG around 0.5~0.8V.
VM=VG/2 and 0.8V ≤ VM < VDD2.
The worse condition should be considered:
Low temperature effect and display on with snow pattern on panel (max: 1.8”).
Ver 1.4b
46/49
2009/02/04
ST7567
ITO Layout Reference
The reference ITO layout is shown below:
VGout
VGs
VGin
VGin
XV0in
XV0in
XV0s
XV0out
XV0out
V0out
V0out
V0s
V0in
V0in
VSS2
VSS2
VSS2
VSS3
VSS1
VSS1
VDD3
VDD2
VDD2
VDD2
VDD1
VDD1
The equivalent circuit is shown below:
V
V
X
V
&
V
G
V000,,, X
XV
V000 &
&V
VG
G
V
V
D
D
VD
DD
D
V
V
S
S
VS
SS
S
Ideal Layout:
Ideal Layout:
Ideal Layout:
=> R4=0 Ohm. R2>>R1>R3.
=> R4=0 Ohm. R3>>R1>R2.
=> R4=0 Ohm. R2>>R1>R3.
Acceptable Layout:
Acceptable Layout:
Acceptable Layout:
=> R4≠0. R2>>R1>R3>R4.
=> R4≠0. R3>>R1>R2>R4.
=> R4≠0. R2>>R1>R3>R4.
Not Acceptable:
Not Acceptable:
Not Acceptable:
=> R4 ≥ (R1 or R2 or R3).
=> R4 ≥ (R1 or R2 or R3).
=> R4 ≥ (R1 or R2 or R3).
Ver 1.4b
47/49
2009/02/04
ST7567
ITO Layout Guide
The reference ITO layout is shown below:
Note:
Recommend ITO resistance refer to Page11.
Ver 1.4b
48/49
2009/02/04
ST7567
REVERSION HISTORY
Version
Date
Description
0.0
0.0a
0.1
2007/06/2
2007/06/19
0.1a
2008/01/21
1.0
2008/02/15
1.0a
2008/02/19
1.1
1.2
2008/03/21
2008/06/26
Rearrange section.
Rewrite description.
Add Application Circuit.
Add pad location.
Redraw application circuit (remove VMO capacitor).
Reserve R1 for abnormal power off procedure.
Rewrite description.
Add more application notes.
Fix Thermal Gradient.
Update DC Characteristics.
Update Timing Characteristic.
Update Chip Thickness.
Add Pass Number.
Modify outline description.
Fix some arrow direction in Block Diagram.
Add more information of operation flow.
Change DC Characteristics of VDD1 range: 1.7V ~ 3.3V.
Add ITO layout note.
Modify Voltage Booster Level.
Add Application Voltage Guide.
Modify storage temperature.
Modify Current Consumption of DC Characteristics.
Modify temperature range of Timing Characteristic.
Add ITO Layout Guide.
Modify Power ON Sequence.
Add Cap. C3 in Application Note.
Modify ITO Layout Guide.
Modify Application note.
1.3
2008/07/11
1.3a
2008/07/22
1.4
2008/10/16
1.4a
2008/11/06
Modify ITO Layout Guide.
1.4b
2009/02/04
Add description of output pin name in different duty.
Ver 1.4b
49/49
2009/02/04