SITRONIX ST7632

ST
Sitronix
ST7632
4K Color Dot Matrix LCD Controller/Driver
1. INTRODUCTION
The ST7632 is a driver & controller LSI for 4K color graphic dot-matrix liquid crystal display systems. It generates 396
Segment and 132 Common driver circuits. This chip is connected directly to a microprocessor, accepts Serial Peripheral
Interface (SPI) or 8-bit/16-bit parallel display data and stores in an on-chip display data RAM. It performs display data RAM
read/write operation with no external operating clock to minimize power consumption. In addition, because it contains
power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
2. FEATURES
On-chip Low Power Analog Circuit
Driver Output Circuits
− On-chip oscillator circuit
−396 segment outputs / 132 common outputs
− Voltage converter (x2, x3, x4, x5, x6, x7, x8)
Applicable Duty Ratios
− Voltage regulator
− Various partial display
− On-chip electronic contrast control function
− Partial window moving & data scrolling
− Voltage follower (LCD bias: 1/5 to 1/12)
On-chip Display Data RAM
Operating Voltage Range
− Capacity: 396 × 132 × 4 =209,088 bits
− Supply voltage (VDD, VDD1): 2.0 to 3.3V
− 256 colors (RGB)=(332) mode
(VDD2, VDD3, VDD4, VDD5): 2.6 to
−4K colors (RGB)=(444) mode
3.3V
−Dithered 65K colors (RGB)=(565) mode
V3 & V4 must large than VDD5
−Dithered 262K colors (RGB)=(666) mode
− LCD driving voltage (VLCD = V0 - VSS): 3.76 to 18.0 V
−Dithered 16M colors (RGB)=(888) mode
− Suggest Vop range=12V~14V,LCD bias=1/12.
Microprocessor Interface
LCD driving voltage (EEPROM)
− 8/16-bit parallel bi-directional interface with 6800-series
− To store contrast adjustment value for better display
Package Type
or 8080-series
− 4-line serial interface (4-line-SIF)
− Application for COG
− 3-line serial interface (3-line-SIF)
Par no.
ST7632
ST7632
Ver 1.7
Equipment
Type
Internal
Power
Supply
Thermal Gradient
-0.125( +-10% )%/℃
6800 , 8080 ,4-Line , 3-Line interface
1/96
2006/08/15
ST7632
3. ST7632 Pad Arrangement (COG)
Chip Size: 19,550 um × 1,473 um
Bump Pitch: PAD NO 1 ~ 496, 632~663: 40 um (COM/SEG), PAD NO 497 ~ 631: 110 um (I/O)
Bump size:
PAD NO.1~464: 25(x)um X 110(y)um
PAD No.465~496, 632~663: 110(x)um X 25(y)um
PAD N0. 497~631: 90(x)um X 40(y)um
Bump Height: 17um
Chip Thickness: 635 um
Bump size of
PAD 465~496
PAD 632~663
45
25
30
60
unit: um
Bump size of
PAD 1~464
(-7909.1,189.69)
110
110
30
25
unit: um
unit: um
464 463
1
465
663
Y
X
(0,0)
496
632
497
630 631
498
90
40
30
40
Bump size of
PAD 497 ~ 631
(9427.36, -645.88)
25
81.75
60
30
40
unit: um
45
(-174,-483)
unit: um
Ver 1.7
2/96
unit: um
2006/08/15
ST7632
4. Pad Center Coordinates
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
001
COM[32]
9384
625
036
SEG[394]
7882
625
002
COM[33]
9344
625
037
SEG[393]
7842
625
003
COM[34]
9304
625
038
SEG[392]
7802
625
004
COM[35]
9264
625
039
SEG[391]
7762
625
005
COM[36]
9224
625
040
SEG[390]
7722
625
006
COM[37]
9184
625
041
SEG[389]
7682
625
007
COM[38]
9144
625
042
SEG[388]
7642
625
008
COM[39]
9104
625
043
SEG[387]
7602
625
009
COM[40]
9064
625
044
SEG[386]
7562
625
010
COM[41]
9024
625
045
SEG[385]
7522
625
011
COM[42]
8984
625
046
SEG[384]
7482
625
012
COM[43]
8944
625
047
SEG[383]
7442
625
013
COM[44]
8904
625
048
SEG[382]
7402
625
014
COM[45]
8864
625
049
SEG[381]
7362
625
015
COM[46]
8824
625
050
SEG[380]
7322
625
016
COM[47]
8784
625
051
SEG[379]
7282
625
017
COM[48]
8744
625
052
SEG[378]
7242
625
018
COM[49]
8704
625
053
SEG[377]
7202
625
019
COM[50]
8664
625
054
SEG[376]
7162
625
020
COM[51]
8624
625
055
SEG[375]
7122
625
021
COM[52]
8584
625
056
SEG[374]
7082
625
022
COM[53]
8544
625
057
SEG[373]
7042
625
023
COM[54]
8504
625
058
SEG[372]
7002
625
024
COM[55]
8464
625
059
SEG[371]
6962
625
025
COM[56]
8424
625
060
SEG[370]
6922
625
026
COM[57]
8384
625
061
SEG[369]
6882
625
027
COM[58]
8344
625
062
SEG[368]
6842
625
028
COM[59]
8304
625
063
SEG[367]
6802
625
029
COM[60]
8264
625
064
SEG[366]
6762
625
030
COM[61]
8224
625
065
SEG[365]
6722
625
031
COM[62]
8184
625
066
SEG[364]
6682
625
032
COM[63]
8144
625
067
SEG[363]
6642
625
033
COM[64]
8104
625
068
SEG[362]
6602
625
034
COM[65]
8064
625
069
SEG[361]
6562
625
035
SEG[395]
7922
625
070
SEG[360]
6522
625
Ver 1.7
3/96
2006/08/15
ST7632
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
071
SEG[359]
6482
625
107
SEG[323]
5042
625
072
SEG[358]
6442
625
108
SEG[322]
5002
625
073
SEG[357]
6402
625
109
SEG[321]
4962
625
074
SEG[356]
6362
625
110
SEG[320]
4922
625
075
SEG[355]
6322
625
111
SEG[319]
4882
625
076
SEG[354]
6282
625
112
SEG[318]
4842
625
077
SEG[353]
6242
625
113
SEG[317]
4802
625
078
SEG[352]
6202
625
114
SEG[316]
4762
625
079
SEG[351]
6162
625
115
SEG[315]
4722
625
080
SEG[350]
6122
625
116
SEG[314]
4682
625
081
SEG[349]
6082
625
117
SEG[313]
4642
625
082
SEG[348]
6042
625
118
SEG[312]
4602
625
083
SEG[347]
6002
625
119
SEG[311]
4562
625
084
SEG[346]
5962
625
120
SEG[310]
4522
625
085
SEG[345]
5922
625
121
SEG[309]
4482
625
086
SEG[344]
5882
625
122
SEG[308]
4442
625
087
SEG[343]
5842
625
123
SEG[307]
4402
625
088
SEG[342]
5802
625
124
SEG[306]
4362
625
089
SEG[341]
5762
625
125
SEG[305]
4322
625
090
SEG[340]
5722
625
126
SEG[304]
4282
625
091
SEG[339]
5682
625
127
SEG[303]
4242
625
092
SEG[338]
5642
625
128
SEG[302]
4202
625
093
SEG[337]
5602
625
129
SEG[301]
4162
625
094
SEG[336]
5562
625
130
SEG[300]
4122
625
095
SEG[335]
5522
625
131
SEG[299]
4082
625
096
SEG[334]
5482
625
132
SEG[298]
4042
625
097
SEG[333]
5442
625
133
SEG[297]
4002
625
098
SEG[332]
5402
625
134
SEG[296]
3962
625
099
SEG[331]
5362
625
135
SEG[295]
3922
625
100
SEG[330]
5322
625
136
SEG[294]
3882
625
101
SEG[329]
5282
625
137
SEG[293]
3842
625
102
SEG[328]
5242
625
138
SEG[292]
3802
625
103
SEG[327]
5202
625
139
SEG[291]
3762
625
104
SEG[326]
5162
625
140
SEG[290]
3722
625
105
SEG[325]
5122
625
141
SEG[289]
3682
625
106
SEG[324]
5082
625
142
SEG[288]
3642
625
Ver 1.7
4/96
2006/08/15
ST7632
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
143
SEG[287]
3602
625
179
SEG[251]
2162
625
144
SEG[286]
3562
625
180
SEG[250]
2122
625
145
SEG[285]
3522
625
181
SEG[249]
2082
625
146
SEG[284]
3482
625
182
SEG[248]
2042
625
147
SEG[283]
3442
625
183
SEG[247]
2002
625
148
SEG[282]
3402
625
184
SEG[246]
1962
625
149
SEG[281]
3362
625
185
SEG[245]
1922
625
150
SEG[280]
3322
625
186
SEG[244]
1882
625
151
SEG[279]
3282
625
187
SEG[243]
1842
625
152
SEG[278]
3242
625
188
SEG[242]
1802
625
153
SEG[277]
3202
625
189
SEG[241]
1762
625
154
SEG[276]
3162
625
190
SEG[240]
1722
625
155
SEG[275]
3122
625
191
SEG[239]
1682
625
156
SEG[274]
3082
625
192
SEG[238]
1642
625
157
SEG[273]
3042
625
193
SEG[237]
1602
625
158
SEG[272]
3002
625
194
SEG[236]
1562
625
159
SEG[271]
2962
625
195
SEG[235]
1522
625
160
SEG[270]
2922
625
196
SEG[234]
1482
625
161
SEG[269]
2882
625
197
SEG[233]
1442
625
162
SEG[268]
2842
625
198
SEG[232]
1402
625
163
SEG[267]
2802
625
199
SEG[231]
1362
625
164
SEG[266]
2762
625
200
SEG[230]
1322
625
165
SEG[265]
2722
625
201
SEG[229]
1282
625
166
SEG[264]
2682
625
202
SEG[228]
1242
625
167
SEG[263]
2642
625
203
SEG[227]
1202
625
168
SEG[262]
2602
625
204
SEG[226]
1162
625
169
SEG[261]
2562
625
205
SEG[225]
1122
625
170
SEG[260]
2522
625
206
SEG[224]
1082
625
171
SEG[259]
2482
625
207
SEG[223]
1042
625
172
SEG[258]
2442
625
208
SEG[222]
1002
625
173
SEG[257]
2402
625
209
SEG[221]
962
625
174
SEG[256]
2362
625
210
SEG[220]
922
625
175
SEG[255]
2322
625
211
SEG[219]
882
625
176
SEG[254]
2282
625
212
SEG[218]
842
625
177
SEG[253]
2242
625
213
SEG[217]
802
625
178
SEG[252]
2202
625
214
SEG[216]
762
625
Ver 1.7
5/96
2006/08/15
ST7632
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
215
SEG[215]
722
625
251
SEG[179]
-718
625
216
SEG[214]
682
625
252
SEG[178]
-758
625
217
SEG[213]
642
625
253
SEG[177]
-798
625
218
SEG[212]
602
625
254
SEG[176]
-838
625
219
SEG[211]
562
625
255
SEG[175]
-878
625
220
SEG[210]
522
625
256
SEG[174]
-918
625
221
SEG[209]
482
625
257
SEG[173]
-958
625
222
SEG[208]
442
625
258
SEG[172]
-998
625
223
SEG[207]
402
625
259
SEG[171]
-1038
625
224
SEG[206]
362
625
260
SEG[170]
-1078
625
225
SEG[205]
322
625
261
SEG[169]
-1118
625
226
SEG[204]
282
625
262
SEG[168]
-1158
625
227
SEG[203]
242
625
263
SEG[167]
-1198
625
228
SEG[202]
202
625
264
SEG[166]
-1238
625
229
SEG[201]
162
625
265
SEG[165]
-1278
625
230
SEG[200]
122
625
266
SEG[164]
-1318
625
231
SEG[199]
82
625
267
SEG[163]
-1358
625
232
SEG[198]
42
625
268
SEG[162]
-1398
625
233
SEG[197]
2
625
269
SEG[161]
-1438
625
234
SEG[196]
-38
625
270
SEG[160]
-1478
625
235
SEG[195]
-78
625
271
SEG[159]
-1518
625
236
SEG[194]
-118
625
272
SEG[158]
-1558
625
237
SEG[193]
-158
625
273
SEG[157]
-1598
625
238
SEG[192]
-198
625
274
SEG[156]
-1638
625
239
SEG[191]
-238
625
275
SEG[155]
-1678
625
240
SEG[190]
-278
625
276
SEG[154]
-1718
625
241
SEG[189]
-318
625
277
SEG[153]
-1758
625
242
SEG[188]
-358
625
278
SEG[152]
-1798
625
243
SEG[187]
-398
625
279
SEG[151]
-1838
625
244
SEG[186]
-438
625
280
SEG[150]
-1878
625
245
SEG[185]
-478
625
281
SEG[149]
-1918
625
246
SEG[184]
-518
625
282
SEG[148]
-1958
625
247
SEG[183]
-558
625
283
SEG[147]
-1998
625
248
SEG[182]
-598
625
284
SEG[146]
-2038
625
249
SEG[181]
-638
625
285
SEG[145]
-2078
625
250
SEG[180]
-678
625
286
SEG[144]
-2118
625
Ver 1.7
6/96
2006/08/15
ST7632
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
287
SEG[143]
-2158
625
323
SEG[107]
-3598
625
288
SEG[142]
-2198
625
324
SEG[106]
-3638
625
289
SEG[141]
-2238
625
325
SEG[105]
-3678
625
290
SEG[140]
-2278
625
326
SEG[104]
-3718
625
291
SEG[139]
-2318
625
327
SEG[103]
-3758
625
292
SEG[138]
-2358
625
328
SEG[102]
-3798
625
293
SEG[137]
-2398
625
329
SEG[101]
-3838
625
294
SEG[136]
-2438
625
330
SEG[100]
-3878
625
295
SEG[135]
-2478
625
331
SEG[99]
-3918
625
296
SEG[134]
-2518
625
332
SEG[98]
-3958
625
297
SEG[133]
-2558
625
333
SEG[97]
-3998
625
298
SEG[132]
-2598
625
334
SEG[96]
-4038
625
299
SEG[131]
-2638
625
335
SEG[95]
-4078
625
300
SEG[130]
-2678
625
336
SEG[94]
-4118
625
301
SEG[129]
-2718
625
337
SEG[93]
-4158
625
302
SEG[128]
-2758
625
338
SEG[92]
-4198
625
303
SEG[127]
-2798
625
339
SEG[91]
-4238
625
304
SEG[126]
-2838
625
340
SEG[90]
-4278
625
305
SEG[125]
-2878
625
341
SEG[89]
-4318
625
306
SEG[124]
-2918
625
342
SEG[88]
-4358
625
307
SEG[123]
-2958
625
343
SEG[87]
-4398
625
308
SEG[122]
-2998
625
344
SEG[86]
-4438
625
309
SEG[121]
-3038
625
345
SEG[85]
-4478
625
310
SEG[120]
-3078
625
346
SEG[84]
-4518
625
311
SEG[119]
-3118
625
347
SEG[83]
-4558
625
312
SEG[118]
-3158
625
348
SEG[82]
-4598
625
313
SEG[117]
-3198
625
349
SEG[81]
-4638
625
314
SEG[116]
-3238
625
350
SEG[80]
-4678
625
315
SEG[115]
-3278
625
351
SEG[79]
-4718
625
316
SEG[114]
-3318
625
352
SEG[78]
-4758
625
317
SEG[113]
-3358
625
353
SEG[77]
-4798
625
318
SEG[112]
-3398
625
354
SEG[76]
-4838
625
319
SEG[111]
-3438
625
355
SEG[75]
-4878
625
320
SEG[110]
-3478
625
356
SEG[74]
-4918
625
321
SEG[109]
-3518
625
357
SEG[73]
-4958
625
322
SEG[108]
-3558
625
358
SEG[72]
-4998
625
Ver 1.7
7/96
2006/08/15
ST7632
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
359
SEG[71]
-5038
625
395
SEG[35]
-6478
625
360
SEG[70]
-5078
625
396
SEG[34]
-6518
625
361
SEG[69]
-5118
625
397
SEG[33]
-6558
625
362
SEG[68]
-5158
625
398
SEG[32]
-6598
625
363
SEG[67]
-5198
625
399
SEG[31]
-6638
625
364
SEG[66]
-5238
625
400
SEG[30]
-6678
625
365
SEG[65]
-5278
625
401
SEG[29]
-6718
625
366
SEG[64]
-5318
625
402
SEG[28]
-6758
625
367
SEG[63]
-5358
625
403
SEG[27]
-6798
625
368
SEG[62]
-5398
625
404
SEG[26]
-6838
625
369
SEG[61]
-5438
625
405
SEG[25]
-6878
625
370
SEG[60]
-5478
625
406
SEG[24]
-6918
625
371
SEG[59]
-5518
625
407
SEG[23]
-6958
625
372
SEG[58]
-5558
625
408
SEG[22]
-6998
625
373
SEG[57]
-5598
625
409
SEG[21]
-7038
625
374
SEG[56]
-5638
625
410
SEG[20]
-7078
625
375
SEG[55]
-5678
625
411
SEG[19]
-7118
625
376
SEG[54]
-5718
625
412
SEG[18]
-7158
625
377
SEG[53]
-5758
625
413
SEG[17]
-7198
625
378
SEG[52]
-5798
625
414
SEG[16]
-7238
625
379
SEG[51]
-5838
625
415
SEG[15]
-7278
625
380
SEG[50]
-5878
625
416
SEG[14]
-7318
625
381
SEG[49]
-5918
625
417
SEG[13]
-7358
625
382
SEG[48]
-5958
625
418
SEG[12]
-7398
625
383
SEG[47]
-5998
625
419
SEG[11]
-7438
625
384
SEG[46]
-6038
625
420
SEG[10]
-7478
625
385
SEG[45]
-6078
625
421
SEG[9]
-7518
625
386
SEG[44]
-6118
625
422
SEG[8]
-7558
625
387
SEG[43]
-6158
625
423
SEG[7]
-7598
625
388
SEG[42]
-6198
625
424
SEG[6]
-7638
625
389
SEG[41]
-6238
625
425
SEG[5]
-7678
625
390
SEG[40]
-6278
625
426
SEG[4]
-7718
625
391
SEG[39]
-6318
625
427
SEG[3]
-7758
625
392
SEG[38]
-6358
625
428
SEG[2]
-7798
625
393
SEG[37]
-6398
625
429
SEG[1]
-7838
625
394
SEG[36]
-6438
625
430
SEG[0]
-7878
625
Ver 1.7
8/96
2006/08/15
ST7632
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
431
COM[66]
-8020
625
467
COM[102]
-9664
526
432
COM[67]
-8060
625
468
COM[103]
-9664
486
433
COM[68]
-8100
625
469
COM[104]
-9664
446
434
COM[69]
-8140
625
470
COM[105]
-9664
406
435
COM[70]
-8180
625
471
COM[106]
-9664
366
436
COM[71]
-8220
625
472
COM[107]
-9664
326
437
COM[72]
-8260
625
473
COM[108]
-9664
286
438
COM[73]
-8300
625
474
COM[109]
-9664
246
439
COM[74]
-8340
625
475
COM[110]
-9664
206
440
COM[75]
-8380
625
476
COM[111]
-9664
166
441
COM[76]
-8420
625
477
COM[112]
-9664
126
442
COM[77]
-8460
625
478
COM[113]
-9664
86
443
COM[78]
-8500
625
479
COM[114]
-9664
46
444
COM[79]
-8540
625
480
COM[115]
-9664
6
445
COM[80]
-8580
625
481
COM[116]
-9664
-34
446
COM[81]
-8620
625
482
COM[117]
-9664
-74
447
COM[82]
-8660
625
483
COM[118]
-9664
-114
448
COM[83]
-8700
625
484
COM[119]
-9664
-154
449
COM[84]
-8740
625
485
COM[120]
-9664
-194
450
COM[85]
-8780
625
486
COM[121]
-9664
-234
451
COM[86]
-8820
625
487
COM[122]
-9664
-274
452
COM[87]
-8860
625
488
COM[123]
-9664
-314
453
COM[88]
-8900
625
489
COM[124]
-9664
-354
454
COM[89]
-8940
625
490
COM[125]
-9664
-394
455
COM[90]
-8980
625
491
COM[126]
-9664
-434
456
COM[91]
-9020
625
492
COM[127]
-9664
-474
457
COM[92]
-9060
625
493
COM[128]
-9664
-514
458
COM[93]
-9100
625
494
COM[129]
-9664
-554
459
COM[94]
-9140
625
495
COM[130]
-9664
-594
460
COM[95]
-9180
625
496
COM[131]
-9664
-634
461
COM[96]
-9220
625
497
V0IN
-5444
-660
462
COM[97]
-9260
625
498
V0IN
-5334
-660
463
COM[98]
-9300
625
499
V0IN
-5224
-660
464
COM[99]
-9340
625
500
V0IN
-5114
-660
465
COM[100]
-9664
606
501
V0IN
-5004
-660
466
COM[101]
-9664
566
502
V0IN
-4894
-660
Ver 1.7
9/96
2006/08/15
ST7632
PAD No.
PIN Name
X
Y
PAD No.
503
V0OUT
-4784
-660
539
504
V0OUT
-4674
-660
505
V0OUT
-4564
506
V0OUT
507
X
Y
D1
-824
-660
540
D2
-714
-660
-660
541
D3
-604
-660
-4454
-660
542
D4
-494
-660
V0OUT
-4344
-660
543
D5
-384
-660
508
V0OUT
-4234
-660
544
D6
-274
-660
509
V1
-4124
-660
545
D7
-164
-660
510
V2
-4014
-660
546
VSS
-54
-660
511
V3
-3904
-660
547
VDD
56
-660
512
V4
-3794
-660
548
D8
166
-660
513
VREF
-3684
-660
549
D9
276
-660
514
VSS
-3574
-660
550
D10
386
-660
515
VSS
-3464
-660
551
D11
496
-660
516
VSS
-3354
-660
552
D12
606
-660
517
VSS
-3244
-660
553
D13
716
-660
518
VSS
-3134
-660
554
D14
826
-660
519
VSS
-3024
-660
555
D15
936
-660
520
VSS1
-2914
-660
556
VSS
1046
-660
521
VSS1
-2804
-660
557
VDD
1156
-660
522
VDD1
-2694
-660
558
E_RD
1266
-660
523
VDD1
-2584
-660
559
RST
1376
-660
524
VDD
-2474
-660
560
VSS
1486
-660
525
VDD
-2364
-660
561
VDD
1596
-660
526
VDD
-2254
-660
562
IF1
1706
-660
527
VDD
-2144
-660
563
IF2
1816
-660
528
VDD
-2034
-660
564
IF3
1926
-660
529
VDD
-1924
-660
565
CSEL
2036
-660
530
CL
-1814
-660
566
VSS
2146
-660
531
CLS
-1704
-660
567
VDD
2256
-660
532
VSS
-1594
-660
568
SI
2366
-660
533
VDD
-1484
-660
569
SCL
2476
-660
534
A0
-1374
-660
570
/CS
2586
-660
535
RW_WR
-1264
-660
571
VDD
2696
-660
536
VSS
-1154
-660
572
VDD
2806
-660
537
VDD
-1044
-660
573
VDD
2916
-660
538
D0
-934
-660
574
VDD
3026
-660
Ver 1.7
10/96
PIN Name
2006/08/15
ST7632
PAD No.
PIN Name
X
Y
PAD No.
575
VDD
3136
-660
611
576
VDD
3246
-660
577
VDD1
3356
578
VDD1
579
PIN Name
X
Y
VDD2
7096
-660
612
VDD2
7206
-660
-660
613
VDD2
7316
-660
3466
-660
614
VDD2
7426
-660
VSS1
3576
-660
615
VDD5
7536
-660
580
VSS1
3686
-660
616
VDD5
7646
-660
581
VSS
3796
-660
617
VDD5
7756
-660
582
VSS
3906
-660
618
VDD5
7866
-660
583
VSS
4016
-660
619
TCAP
7978
-660
584
VSS
4126
-660
620
VOUTIN
8090
-660
585
VSS
4236
-660
621
VOUTIN
8200
-660
586
VSS
4346
-660
622
VOUTIN
8310
-660
587
VSS2
4456
-660
623
VOUTIN
8420
-660
588
VSS2
4566
-660
624
VOUTIN
8530
-660
589
VSS2
4676
-660
625
VOUTIN
8640
-660
590
VSS2
4786
-660
626
VOUTOUT
8750
-660
591
VSS2
4896
-660
627
VOUTOUT
8860
-660
592
VSS2
5006
-660
628
VOUTOUT
8970
-660
593
VSS2
5116
-660
629
VOUTOUT
9080
-660
594
VSS2
5226
-660
630
VOUTOUT
9190
-660
595
VSS2
5336
-660
631
VOUTOUT
9300
-660
596
VSS2
5446
-660
632
COM[0]
9664
-634
597
VSS2
5556
-660
633
COM[1]
9664
-594
598
VSS2
5666
-660
634
COM[2]
9664
-554
599
VSS4
5776
-660
635
COM[3]
9664
-514
600
VSS4
5886
-660
636
COM[4]
9664
-474
601
VDD4
5996
-660
637
COM[5]
9664
-434
602
VDD4
6106
-660
638
COM[6]
9664
-394
603
VDD3
6216
-660
639
COM[7]
9664
-354
604
VDD3
6326
-660
640
COM[8]
9664
-314
605
VDD2
6436
-660
641
COM[9]
9664
-274
606
VDD2
6546
-660
642
COM[10]
9664
-234
607
VDD2
6656
-660
643
COM[11]
9664
-194
608
VDD2
6766
-660
644
COM[12]
9664
-154
609
VDD2
6876
-660
645
COM[13]
9664
-114
610
VDD2
6986
-660
646
COM[14]
9664
-74
Ver 1.7
11/96
2006/08/15
ST7632
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
647
COM[15]
9664
-34
655
COM[23]
9664
286
648
COM[16]
9664
6
656
COM[24]
9664
326
649
COM[17]
9664
46
657
COM[25]
9664
366
650
COM[18]
9664
86
658
COM[26]
9664
406
651
COM[19]
9664
126
659
COM[27]
9664
446
652
COM[20]
9664
166
660
COM[28]
9664
486
653
COM[21]
9664
206
661
COM[29]
9664
526
654
COM[22]
9664
246
662
COM[30]
9664
566
663
COM[31]
9664
606
Ver 1.7
12/96
2006/08/15
ST7632
5. BLOCK DIAGRAM
SEG0 TO SEG395
V0IN
V1
V2
V3
V4
SEGMENT DRIVERS
COM0 TO COM131
COMMON
DRIVERS
CSEL
VSS
DATA LATCHES
COMMON
OUTPUT
CONTROLLER
CIRCUIT
V/F
Circuit
FRC/PWM FUNCTION
CIRCUIT
V0OUT
RESET
V/R
Circuit
VREF
VDD5
VDD4
VDD3
VDD2
OSCILLATOR
DISPLAY DATA RAM
(DDRAM)
[396X132X4]
CLS
VDD1
TIMING
GENERATOR
DISPLAY
ADDRESS
COUNTER
V/C
Circuit
ADDRESS COUNTER
OTP
VOUTIN
VOUTOUT
VSS2
VSS4
VSS1
VSS
VDD
BUS
HOLDER
INSTRUCTION
DECODER
MPU INTERFACE(PARALLEL & SERIAL)
TCAP
D0 to D15
SI
13/96
SCL
E_RD
RW_WR
A0
/CS
/RST
IF3
IF2
IF1
Ver 1.7
DATA
REGISTER
INSTRUCTION
REGISTER
2006/08/15
ST7632
6. PIN DESCRIPTION
6.1 POWER SUPPLY
Name
I/O
Description
VDD
Power
Power supply for logic circuit
VDD1
Power
Power supply for OSC circuit
VDD2
Power
Power supply for Booster Circuit
VDD3
Power
Power supply for LCD.
VDD4
Power
Power supply for LCD.
VDD5
Power
Power supply for LCD.
VSS
Power
Ground. Ground system should be connected together.
VSS1
Power
Ground. Ground system should be connected together.
VSS2
Power
Ground. Ground system should be connected together.
VSS4
Power
Ground. Ground system should be connected together.
VOUTOUT
Power
VOUTIN
Power
If the internal voltage generator is used, the VOUTIN & VOUTOUT must be connected together.
If an external supply is used, this pin must be left open.
An external LCD supply voltage can be supplied using the VOUTIN pad. In this case, VOUTOUT has
to be left open, and the internal voltage generator has to be programmed to zero. (SET register
VC=0)
LCD driver supply voltages
The voltage determined by LCD pixel is impedance-converted by an operational amplifier for
application.
V0IN
V0IN & V0OUT should be connected together.
V0OUT
Voltages should have the following relationship;
V1
Power
V2
V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
When the internal power circuit is active, these voltages are generated as following table according
V3
to the state of LCD bias.
V4
LCD bias
V1
V2
V3
V4
1/N bias
(N-1) / N x V0
(N-2) / N x V0
(2/N) x V0
(1/N) x V0
NOTE: N = 5 to 12
VREF
O
Reference voltage output for monitor only. Left it opened.
6.2 LCD DRIVER SUPPLY
Name
I/O
CLS
I
Description
When using internal clock oscillator, connect CLS to VDD.
When using external clock oscillator, connect CLS to VSS.
When using internal clock oscillator, it’s oscillator output. (when CLS=”H”)
CL
I/O
When using external clock oscillator, it’s oscillator input.
Ver 1.7
14/96
(when CLS=”L”)
2006/08/15
ST7632
6.3 SYSTEM CONTROL
Name
I/O
Description
CSEL
I
Must contact to VSS
TCAP
I
Test pin. Do not use. Let it open.
6.4 MICROPROCESSOR INTERFACE
Name
I/O
RST
I
Description
Reset input pin
When RESETB is “L”, initialization is executed.
Parallel / Serial data input select input
IF[3:1]
I
IF1
IF2
IF3
MPU interface type
H
H
H
80 series 16-bit parallel
H
H
L
80 series 8-bit parallel
H
L
L
68 series 16-bit parallel
L
H
H
68 series 8-bit parallel
L
L
H
9-bit serial (3 line)
L
L
L
8-bit serial (4 line)
Chip select input pins
/CS
I
Data/instruction I/O is enabled only when /CS is "L". When chip select is non-active, D0 to D7
are high impedance.
Register select input pin
A0
I
− A0 = "H": D0 to D15 or SI are display data
− A0 = "L": D0 to D15 or SI are control data
In 3-line interface not let it floating, contact it to VSS or VDD.
Read / Write execution control pin
MPU type
RW_WR
Description
Read / Write control input pin
6800-series
RW_WR
RW
RW = “H” : read
RW = “L” : write
I
Write enable clock input pin
8080-series
/WR
The data on D0 to D15 are latched at the
rising edge of the /WR signal.
When not use, contact it to VDD.
Ver 1.7
15/96
2006/08/15
ST7632
Read / Write execution control pin
MPU Type
E_RD
Description
Read / Write control input pin
− RW = “H”: When E is “H”, D0 to D15 are in an output
6800-series
E_RD
E
status.
I
− RW = “L”: The data on D0 to D15 are latched at the
falling edge of the E signal.
Read enable clock input pin
8080-series
/RD
When /RD is “L”, D0 to D15 are in an output status.
When not use, contact it to VDD
They connect to the standard 8-bit or 16 bit MPU bus via the 8/16 –bit bi-directional bus.
When the following interface is selected and the CS pin is high, the following pins become high
D15 to D0
I/O
impedance.
1.
8-bit parallel: D15-D8 are in the state of high impedance, should contact to “H” level.
2.
Serial interface: D15-D0 are in the state of high impedance, should contact to “H” level.
This pin is used to input serial data when the serial interface is selected.(3 line and 4 line)
SI
I
When not use contact it to VSS or VDD.
This pin is used to input serial clock when the serial interface is selected.
SCL
I
The data is converted in the rising edge. (3 line and 4 line)
When not use contact it to VSS or VDD.
NOTE: Microprocessor interface pins should not be floating in any operation mode.
6.5 LCD DRIVER OUTPUTS
Name
I/O
Description
LCD segment driver outputs
The display data and the M signal control the output voltage of segment driver.
Segment driver output voltage
Display data
M (Internal)
SEG0
to
O
SEG395
Reverse display
H
H
V0
V2
H
L
VSS
V3
L
H
V2
V0
L
L
V3
VSS
VSS
VSS
Power save mode
Ver 1.7
Normal display
16/96
2006/08/15
ST7632
LCD common driver outputs
The internal scanning data and M signal control the output voltage of common driver.
Scan data
M (Internal)
Common driver output voltage
H
H
VSS
H
L
V0
L
H
V1
L
L
V4
COM0
to
O
COM131
Power save mode
VSS
ST7632 I/O PIN ITO Resister Limitation
PIN Name
ITO Resister
IF[2:0],CLS,CSEL
No Limitation
VREF, TCAP, CLP
Floating
VDD, VDD1~VDD5, VSS, VSS1, VSS2, VSS4, VOUTIN, VOUTOUT
<100Ω
V0IN, V0OUT, V1, V2, V3, V4
<100Ω
A0, RW_WR, E_RD, /CS, D0 …D15, SCL, SI
<1KΩ
RESB
<10KΩ
Suggest Vop range : 12v~14v
Ver 1.7
17/96
2006/08/15
ST7632
7. FUNCTIONAL DESCRIPTION
7.1 MICROPROCESSOR INTERFACE
Chip Select Input
There is /CS pin for chip selection. The ST7632 can interface with an MPU when /CS is "L". When these pins are set to any
other combination, A0, E_RD, and RW_WR inputs are disabled and D0 to D15 are to be high impedance. And, in case of
serial interface, the internal shift register and the counter are reset.
7.1.1 Selecting Parallel / Serial Interface
ST7632 has six types of interface with an MPU, which are two serial and four parallel interfaces. This parallel or serial
interface is determined by IF pin as shown in table 7.1.1.
Table 7.1.1 Parallel / Serial Interface Mode
IF1
IF2
IF3
Interface type
/CS
A0
E_RD
RW_WR
D15 to D8 D7 to D0
SI
SCL
H
H
H
80 serial 16-bit parallel
/CS
A0
/RD
/WR
D15 to D8 D7 to D0
VDD
VDD
H
H
L
80 serial 8-bit parallel
/CS
A0
/RD
/WR
fix to VDD D7 to D0
VDD
VDD
H
L
L
68 serial 16-bit parallel
/CS
A0
E
RW
D15 to D8 D7 to D0
VDD
VDD
L
H
H
68 serial 8-bit parallel
/CS
A0
E
RW
fix to VDD D7 to D0
VDD
VDD
L
L
H
9-bit SPI mode (3 line)
/CS
VDD
VDD
VDD
fix to VDD
SI
SCL
L
L
L
8-bit SPI mode (4 line)
/CS
A0
VDD
VDD
fix to VDD
SI
SCL
7.1.2 8- or 16-bit Parallel Interface
The ST7632 identifies type of the data bus signals according to combinations of A0, E_RD and RW_WR SIGNALS 8-bit as
shown in table 7.1.2.
Table 7.1.2 Parallel Data Transfer
Common
6800-series
8080-series
Description
A0
RW
E
/RD
/WR
H
H
H
L
H
Display data read out
H
L
H
H
L
Display data write
L
H
H
L
H
Register status read
L
L
H
H
L
Writes to internal register (instruction)
Relation between Data Bus and Gradation Data
ST7632 offers the 256-color display (8 gray scale) out of 4096, the 4096-color display (16 gray scale), the dithered 65K
color display, dithered 262K color display, and dithered 16M color display.
When using 256-color display out of 4096 colors, you can specify color for each of R, G and B using the palette function.
When using 4096-color display, you can select the type A or B display mode depending on the data bus and RGB you use.
When using 65K, 262K, and 16M color, you can specify color for each of R, G, B using the palette function.
Ver 1.7
18/96
2006/08/15
ST7632
Use the command for switching between these modes.
(1) 256-color display out of 4096 colors
Using RGBSET8 command enables you to set color for each of R, G and B by turning on palette function prepared to
convert 3-bit or 2-bit data to 4-bit data.
1. 8-bit mode
D7, D6, D5, D4, D3, D2, D1, D0 : RRRGGGBB (8 bits) data is converted to RRRRGGGGBBBB (12 bits) and then
stored on the display RAM.
(2) 4096-color display
1. 8-bit mode
D7, D6, D5, D4, D3, D2, D1, D0: XXXXRRRR
1st write
D7, D6, D5, D4, D3, D2, D1, D0: GGGGBBBB
2nd write
A single pixel of data is read after the second write operation as shown, and it is written in the display RAM.
2. 16-bit mode
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: XXXXRRRRGGGGBBBB
A single pixel of data is read and written in the display RAM in a single write operation.
“XXXX” are dummy bits, and they are ignored for display.
(3) 65K color display
1. 8-bit mode
D7, D6, D5, D4, D3, D2, D1, D0: RRRRRGGG
1st write
D7, D6, D5, D4, D3, D2, D1, D0: GGGBBBBB
2nd write
A single pixel of data is read after the second write operation as shown, and it is written in the display RAM.
2. 16-bit mode
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRGGGGGGBBBBB (16 bits)
Data is acquired through signal write operation and then written to the display RAM.
(4) 262K color display
1. 8-bit mode
D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRXX
1st write
D7, D6, D5, D4, D3, D2, D1, D0: GGGGGGXX
2nd write
D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBXX
3rd write
A single pixel of data is read after the third write operation as shown, and it is written in the display RAM.
2. 16 bit mode
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRXXGGGGGGXX
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBXXXXXXXXXXXX
A single pixel of data is read after the second write operation as shown, and it is written in the display RAM.
“XXXX” are dummy bits, and they are ignored for display.
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(5) 16M color display
1. 8-bit mode
D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRRR
1st write
D7, D6, D5, D4, D3, D2, D1, D0: GGGGGGGG
2nd write
D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBBB
3rd write
A single pixel of data is read after the third write operation as shown, and it is written in the display RAM.
2. 16 bit mode
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRRRGGGGGGGG
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBBBXXXXXXXX
A single pixel of data is read after the second write operation as shown, and it is written in the display RAM.
7.1.3 8- and 9-bit Serial Interface
The 8-bit serial interface uses four pins /CS, SI, SCL, and A0 to enter commands and data. Meanwhile, the 9-bit serial
interface uses three pins /CS, SI and SCL for the same purpose.
Data read is not available with the serial interface. Data entered must be 8 bits. Refer to the following chart for entering
commands, parameters or gray-scale data.
The relation between gray-scale data and data bus in the serial input is the same as that in the 8-bit parallel interface mode
at every gradation.
(1) 8-bit serial interface (4 line)
When entering data (parameters): A0= HIGH at the rising edge of the 8th SCL.
When entering command: A0= LOW at the rising edge of the 8th SCL
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(2) 9-bit serial interface (3 line)
When entering data (parameters): SI= HIGH at the rising edge of the 1st SCL.
When entering command: SI= LOW at the rising edge of the 1st SCL.
l
If /CS is caused to HIGH before 8 bits from D7 to D0 are entered, the data concerned is invalidated. Before entering
succeeding sets of data, you must correctly input the data concerned again.
l
In order to avoid data transfer error due to incoming noise, it is recommended to set /CS at HIGH on byte basis to
initialize the serial-to-parallel conversion counter and the register.
l
When executing the command RAMWR, set /CS to HIGH after writing the last address (after starting the 9th pulse in
case of 9-bit serial input or after starting the 8th pulse in case of 8-bit serial input).
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7-2 ACCESS TO DDRAM AND INTERNAL REGISTERS
ST7632 realizes high-speed data transfer because the access from MPU is a sort of pipeline processing done via the bus
holder attached to the internal, requiring the cycle time alone without needing the wait time.
For example, when MPU writes data to the DDRAM, the data is once held by the bus holder and then written to the
DDRAM before the succeeding write cycle is started. When MPU reads data from the DDRAM, the first read cycle is
dummy and the bus holder holds the data read in the dummy cycle, and then it read from the bus holder to the system bus
in the succeeding read cycle. Fig. 7.2.1 illustrates these relations.
MPU signal
Write
Operation
A0
/WR
DATA
N
D(N)
D(N+1) D(N+2)
D(N+3)
N
D(N)
D(N+1)
D(N+2)
D(N+3)
N
N+1
N+2
N+3
Dummy
D(N)
Internal signals
/WR
BUS HOLDER
COLUMN ADDRESS
MPU signal
Read
Operation
A0
/WR
/RD
DATA
N
D(N+1)
Internal signals
/WR
/RD
BUS HOLDER
N
COLUMN ADDRESS
N
D(N)
D(N+1)
D(N+2)
D(N)
D(N+1)
D(N+2)
Fig 7.2.1
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7-3 DISPLAY DATA RAM (DDRAM)
7.3.1 DDRAM
It is 396 X 132 X 4 bits capacity RAM prepared for storing dot data. You can access a desired bit by specifying the page
address and column address. Since display data from MCU D7 to D0 and D15 to D8 correspond to one or two pixels of
RGB, data transfer related restrictions are reduced, realizing the display flexing.
The RAM on ST7632 is separated to a block per 4 lines to allow the display system to process data on the block basis.
MPU’s read and write operations to and from the RAM are performed via the I/O buffer circuit; Reading of the RAM for the
liquid crystal drive is controlled from another separate circuit. Refer to the following memory map for the RAM
configuration.
Memory Map (When using the 8 gray-scale. 8-bit mode)
RGB alignment (Command of data control parameter2=000)
Column
Data control command (BCH)
LCD
P11:0
0
1
131
read
P11:1
131
130
0
direction
Color
Data
Page
Block
P10:0
P10:1
0
131
1
130
2
129
3
128
4
127
5
126
6
125
7
124
8
123
9
122
124
7
125
6
126
5
127
4
128
3
129
2
130
1
131
0
R
G
B
R
G
B
R
G
B
D7
D4
D1
D7
D4
D1
D7
D4
D1
D6
D3
D0
D6
D3
D0
D6
D3
D0
D5
D2
D5
D2
D5
D2
0
1
3
4
393
392
0
1
2
31
32
SEGout
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Memory Map (When using the 16 gray-scale Type B. 8-bit mode)
RGB alignment (Command of data control parameter2=000)
Column
Data control command (BCH)
LCD
P11:0
read
Color
0
direction
Data
Page
G
B
R
G
B
R
G
B
D3
D7
D3
D3
D7
D3
D3
D7
D3
D2
D6
D2
D2
D6
D2
D2
D6
D2
D1
D5
D1
D1
D5
D1
D1
D5
D1
D0
D4
D0
D0
D4
D0
D0
D4
D0
131
Color
Data
Page
P10:0
131
R
P11:1
Block
1
130
0
R
G
B
R
G
B
R
G
B
D3
D7
D3
D3
D7
D3
D3
D7
D3
D2
D6
D2
D2
D6
D2
D2
D6
D2
D1
D5
D1
D1
D5
D1
D1
D5
D1
D0
D4
D0
D0
D4
D0
D0
D4
D0
0
1
2
3
4
5
393
394
395
P10:1
0
131
1
130
2
129
3
128
4
127
5
126
6
125
7
124
8
123
9
122
124
7
125
6
126
5
127
4
128
3
129
2
130
1
131
0
0
1
2
31
32
SEGout
You can change position of R and B with DATACTL command.
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Memory Map (When using the 16 gray-scale Type B. 16-bit mode, 16 gray-scale 65K (8bit/16bit), 16 gray-scale
262K(8bit/16bit), and 16 gray-scale 65M(8bit/16bit) mode. )
RGB alignment (Command of data control parameter2=000)
Column
Data control command (BCH)
LCD
P11:0
read
Color
0
direction
Data
Page
G
B
R
G
B
R
G
B
D11
D7
D3
D11
D7
D3
D11
D7
D3
D10
D6
D2
D10
D6
D2
D10
D6
D2
D9
D5
D1
D9
D5
D1
D9
D5
D1
D8
D4
D0
D8
D4
D0
D8
D4
D0
131
Color
Data
Page
P10:0
131
R
P11:1
Block
1
130
0
R
G
B
R
G
B
R
G
B
D11
D7
D3
D11
D7
D3
D11
D7
D3
D10
D6
D2
D10
D6
D2
D10
D6
D2
D9
D5
D1
D9
D5
D1
D9
D5
D1
D8
D4
D0
D8
D4
D0
D8
D4
D0
0
1
2
3
4
5
393
394
395
P10:1
0
131
1
130
2
129
3
128
4
127
5
126
6
125
7
124
8
123
9
122
124
7
125
6
126
5
127
4
128
3
129
2
130
1
131
0
0
1
2
31
32
SEGout
You can change position of R and B with DATACTL command.
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7.3.2 Page Address Control Circuit
This circuit is used to control the address in the page direction when MPU accesses the DDRAM or when reading the
DDRAM to display image on the LCD.
You can specify a scope of the page address with page address set command. When the page-direction scan is specified
with DATACTL command and the address are incremented from the start up to the end page, the column address is
incremented by 1 and the page address returns to start page.
The DDRAM supports up to 132 lines, and thus the total page becomes 132.
In the read operation, as the end page is reached, the column address is automatically incremented by 1 and the page
address is returned to start page.
Using the address normal/inverse parameter of DATACTL command allows you to inverse the correspondence between
the DDRAM address and command output.
7.3.3 Column Address Control Circuit
This circuit is used to control the address in the column direction when MPU accesses the DDRAM. You can specify a
scope of the column address using column address set command. When the column-direction scan is specified with
DATACTL command and the address are incremented from the start up to the end page, the page address is incremented
by 1 and the column address returns to start column.
In the read operation, too, the column address is automatically incremented by 1 and returned to start page as the end
column is reached.
Just like the page address control circuit, using the column address Normal/Reverse parameter of DATACTL command
enables to inverse the correspondence between the DDRAM column address and segment output. This arrangement
relaxes restrictions in the chip layout on the LCD module.
7.3.4 I/O Buffer Circuit
It is the bi-directional buffer used when MPU reads or writes the DDRAM. Since MPU’s read or write of DDRAM is
performed independently from data output to the display data latch circuit, asynchronous access to the DDRAM while the
LCD is turned on does not cause troubles such as flicking of the display images.
7.3.5 Block Address Circuit
The circuit associates pages on DDRAM with COM output. ST7632 processes signals for the liquid crystal display on
4-page basis. Thus, when specifying a specific area in the area scroll display or partial display, you must designate it in
block.
7.3.6 Display data Latch Circuit
This circuit is used to temporarily hold display data to be output from the DDRAM to the SEG decoder circuit. Since display
normal/inverse and display on/off commands are used to control data in the latch circuit alone, they do not modify data in
the DDRAM.
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7.4 Area Scroll Display
Using area scroll set and scroll start set commands allows you to scroll the display screen partially. You can select any one
of the following four scroll patterns.
Center screen scroll
Top screen scroll
Fixed area
Scroll area
Bottom screen scroll
Whole screen scroll
DDRAM
0
1
2
(32+1) blocks
=132 line
27
28
Fixed area
30
Scroll area
31
32
Ver 1.7
Background area
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ST7632
7.5 Partial Display
Using partial in command allows you turn on the partial display (division by line) of the screen. This mode requires less
current consumption than the whole screen display, making it suitable for the equipment in the standby state.
: Display area (partial display area)
: Non-display area
If the partial display region is out of the Max. Display range, it would be no operation
-COM0
-COM1
-COM2
-COM3
-COM4
-COM5
-COM6
-COM7
-COM8
-COM9
-COM10
-COM11
-COM12
-COM13
-COM14
-COM15
-COM16
-COM17
-COM18
-COM19
-COM20
-COM21
-COM22
-COM23
Figure 7.5.1.Reference Example for Partial Display
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-COM0
-COM1
-COM2
-COM3
-COM4
-COM5
-COM6
-COM7
-COM8
-COM9
-COM10
-COM11
-COM12
-COM13
-COM14
-COM15
-COM16
-COM17
-COM18
-COM19
-COM20
-COM21
-COM22
-COM23
Figure 7.5.2.Partial Display (Partial Display Duty=16,initial COM0=0)
-COM0
-COM1
-COM2
-COM3
-COM4
-COM5
-COM6
-COM7
-COM8
-COM9
-COM10
-COM11
-COM12
-COM13
-COM14
-COM15
-COM16
-COM17
-COM18
-COM19
-COM20
-COM21
-COM22
-COM23
Figure 7.5.3.Moving Display (Partial Display Duty=16,Initial COM0=8)
7.6 Gray-Scale Display
ST7632 incorporates a 4FRC & 31 PWM function circuit to display a 16 gray-scale display.
7.7 Oscillation circuit
This is on-chip Oscillator without external resistor. When the internal oscillator is used, CLS must connect to VDD; when
the external oscillator is used, CL could be input pin. This oscillator signal is used in the voltage converter and display
timing generation circuit.
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7.8 Display Timing Generator Circuit
This circuit generates some signals to be used for displaying LCD. The display clock, CL (internal), generated by oscillation
clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is
generated in synchronization with the display clock and the display data latch circuit latches the 132-bit display data in
synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the
access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M), which
enables the LCD driver to make an AC drive waveform, and also generates an internal common timing signal and start
signal to the common driver. The frame signal or the line signal changes the M by setting internal instruction. Driving
waveform and internal timing signal are shown in Figure 7.8.1.
131 132
1
2
3
4
5
6
7
8
9
10
11
12
124 125 126 127 128 129 130 131 132 1
2
3
4
5
CL(Internal)
FR(Internal)
M(Internal)
COM0
VLCD
V1
V2
V3
V4
VSS
COM1
VLCD
V1
V2
V3
V4
VSS
SEGn
VLCD
V1
V2
V3
V4
VSS
Figure 7.8.1 2-frame AC Driving Waveform (Duty Ratio: 1/132)
131
132
1
2
3
4
5
6
7
8
9
10
11
12
123
124
125
126
127
128
129
130
131
132
1
2
3
4
CL(Internal)
FR(Internal)
M(Internal)
VLCD
V1
V2
V3
V4
Vss
COM0
VLCD
V1
V2
V3
V4
Vss
COM1
VLCD
V1
V2
V3
V4
Vss
SEGn
Figure 7.8.2 N-Line Inversion Driving Waveform (N=5,Duty Ratio=1/132)
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7.9 Liquid Crystal drive Circuit
This driver circuit is configured by 132-channel common drivers and 396-channel segment drivers. This LCD panel driver
voltage depends on the combination of display data and M signal.
VDD
VSS
VLCD
V1
V2
V3
V4
VSS
VLCD
V1
V2
V3
V4
VSS
VLCD
V1
V2
V3
V4
VSS
VLCD
V1
V2
V3
V4
VSS
M
COM0
COM1
COM0
COM2
COM3
COM4
COM5
COM6
COM1
COM7
COM8
COM9
COM2
COM10
COM11
COM12
COM13
COM14
SEG0
SEG 0
1
2
3
4
VLCD
V1
V2
V3
V4
VSS
SEG1
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7.10 Liquid Crystal Driver Power Circuit
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power
consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage
follower circuits. They are controlled by power control instruction. For details, refers to "Instruction Description". Table
7.10.1 shows the referenced combinations in using Power Supply circuits.
Table 7.10.1 Recommended Power Supply Combinations
Power
User setup
V/C
V/R
V/F
circuits
circuits
circuits
111
ON
ON
ON
011
OFF
ON
ON
control
VOUT
V0
V1 to V4
Open
Open
Open
Open
Open
(VC VR VF)
Only the internal power
supply circuits are used
Only the voltage
regulator circuits and
External
voltage follower circuits
input
are used
Only the voltage follower
External
001
OFF
OFF
ON
Open
circuits are used
Open
input
Only the external power
000
OFF
OFF
OFF
supply circuits are used
External
External
input
input
Open
7.10.1 Voltage Converter Circuits
These circuits boost up the electric potential between VDD2 and Vss to 2, 3, 4, 5, 6, 7 or 8 times toward positive side and
booster voltage is outputted from VOUOUT pin. It is possible to select the lower boosting level in any boosting circuit by
“ANASET” instruction.
7.10.2 Voltage Regulator Circuits
SET VOP (SETVOP)
The set VOP function is used to program the optimum LCD supply voltage V0.
SETVOP
For example when Vop[8:0] is 257DEC = 13.88V.
The VOP value is programmed via the Vop[8:0] register.
V0=a+( Vop[8:6]Vop[5:0])．b
Ex:Vop[5:0]=000001, Vop[8:6]=100
→ Vop [8:0]=100000001
→ 3.6+257x0.04=13.88
l
a is a fixed constant value (see table 7.10.2).
l
b is a fixed constant value (see table 7.10.2).
l
Vop[8:0] is the programmed VOP value. The programming range for Vop[8:0] is 4 to 410 (05 to 19A hex).
l
VOP[5:0] is the set contrast value which can be set via the interface and is in two’s complement format.(See
command VOLUP & VOLDOWN)
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Table 7.10.2
SYMBOL
VALUE
UNIT
a
3.6
V
b
0.04
V
The VOP[8:0] value must be in the VLCD programming range as given in Fig.7.10.2. Evaluating equation (1), values
outside the programming range indicated in Fig.7.10.2 may result. Calculated values below VOP[8:0]=4 will be
mapped to VOP[8:0]=4, resulting VOP values higher than VOP[8:0]=410 will be mapped to VOP=410.
VLCD
Programming range (05HEX to 19AHEX)
b
a
Vop
00
01
02
03
04
05
06
.....
410DEC
Vop[8:0] programming, (05hex to 19Ahex)
Fig. 7.10.2 VLCD programming range
As the programming range for the internally generated V0 allows values above the max. Allowed V0 (18V) the
user has to ensure while setting the VOP register and the temperature compensation that under all
conditions and including all tolerances the V0 remains below 18V.
Ver 1.7
Par no.
Equipment Type
Thermal Gradient
ST7632
Internal Power Supply
-0.125( +-10% )%/℃
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Booster Efficiency
By Booster Stages (2X, 3X, 4X, 5X, 6X, 7X, 8X) and Booster Efficiency (Level1~4) commands, we could easily set the best
Booster performance with suitable current consumption. If the Booster Efficiency is set to higher level (level4 is higher than
level1), The Boost Efficiency is better than lower level, and it just need few more power consumption current. It could be
applied to each multiple voltage Condition.
When the LCD Panel loading is heavier, the performance of Booster will be not in a good working condition. User could set
the BE level to be higher and just need few more current. Never consider to change to higher Booster Stage at beginning
stage unless it really necessary.
The Booster Efficiency Command could be used together with Booster Stage Command to choose one best Boost output
condition. Users could see the Booster Stage Command as a large scale operation, and see the Booster Efficiency
Command as a small scale operation. These commands are very convenient for using.
Level1
Vout Voltage
Level2
Level3
Level4
5X boost
Loading
VSS Current
Level1
Level2
Level3
Level4
5X Current
Loading
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RESET CIRCUIT
When Power is Turned On
Input power (VDD1~VDD5)
↓
Be sure to apply POWER-ON RESET (RES = LOW)
↓
<Display Setting>
<<State after resetting>>
Display control (DISCTL)
Setting clock dividing ratio:
1 dividing
Duty setting:
1/4
Setting reverse rotation number of line:
11h reverse rotations
Common scan direction (COMSCN)
Setting scan direction:
COM1 -> COM68, COM69 -> COM132
Oscillation ON (OSCON)
Oscillation OFF
↓
Sleep-out (SLIPOUT)
Sleep-in
↓
<Power Supply Setting>
<<State after resetting>>
Electronic volume control (VOLCTR)
Setting volume value :
0
Setting built-in resistance value:
0 (3.76)
Power control (PWRCTR)
Setting operation of power supply circuit:
All OFF
↓
<Display Setting 2>
<<State after resetting>>
Normal rotation of display (DISNOR)/Inversion of display (DISINV): Normal rotation of display
Partial-in (PTLIN)/Partial-out (PTLOUT)
Partial-out
Setting fix area:
0
Area scroll set (ASSET)
Setting area scroll region:
0
Setting area scroll type:
Full-screen scroll
Scroll start set (SCSTART)
Setting scroll start address:
0
↓
<Display Setting 3>
<<State after resetting>>
Data control (DATCTL)
Setting Normal/Reverse rotation of page address:
Normal rotation
Setting Normal/Reverse rotation of column address:
Normal rotation
Setting direction of address scanner:
Column direction
Ver 1.7
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Setting RGB arrangement:
RGB
Setting gradation:
8 gradations
256-color position set (RGBSET8)
Setting color position at 256-color
↓
<RAM Setting>
All 0
<<State after resetting>>
Page address set (PASET)
Setting start page address:
0
Setting end page address:
0
Column address set (CASET)
Setting start column address:
0
Setting end column address:
0
↓
<RAM Write>
<<State after resetting>>
Memory write command (RAMWR)
Writing displayed data : Repeat as many as the number needed
and exit by entering other command.
↓
<Waiting (approximately 100ms)>
Wait until the power supply voltage has stabilized.
Enter the power supply control command first, then wait at least
100ms before entering the display ON command when the built-in
power supply circuit operates.
If you do not wait, an unwanted display may appear on the
liquid crystal panel.
↓
Display ON (DISON):
Ver 1.7
Display OFF
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ST7632
8. COMMANDS
Ext=0
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
DISON
0
1
0
1
0
1
0
1
1
1
1
Display On
AF
None
1
DISOFF
0
1
0
1
0
1
0
1
1
1
0
Display Off
AE
None
2
DISNOR
0
1
0
1
0
1
0
0
1
1
0
Normal Display
A6
None
3
DISINV
0
1
0
1
0
1
0
0
1
1
1
Inverse Display
A7
None
4
COMSCN
0
1
0
1
0
1
1
1
0
1
1
Com Scan Direc.
BB
1 byte
5
DISCTR
0
1
0
1
1
0
0
1
0
1
0
Display Control
CA
3 byte
6
SLPIN
0
1
0
1
0
0
1
0
1
0
1
Sleep In
95
None
7
SLPOUT
0
1
0
1
0
0
1
0
1
0
0
Sleep Out
94
None
8
PASET
0
1
0
0
1
1
1
0
1
0
1
Page Addr. Set
75
2 byte
9
CASET
0
1
0
0
0
0
1
0
1
0
1
Column Addr. Set
15
2 byte
10
DATCTL
0
1
0
1
0
1
1
1
1
0
0
Data Scan Direction
BC
3 byte
11
RGBSET8
0
1
0
1
1
0
0
1
1
1
0
256-color position set
CE
20 byte
12
RAMWR
0
1
0
0
1
0
1
1
1
0
0
Writing to Memory
5C
Data
13
RAMRD
0
1
0
0
1
0
1
1
1
0
1
Reading from Memory
5D
Data
14
PLTIN
0
1
0
1
0
1
0
1
0
0
0
Partial display in
A8
2 byte
15
PLTOUT
0
1
0
1
0
1
0
1
0
0
1
Partial display out
A9
None
16
RMWIN
0
1
0
1
1
1
0
0
0
0
0
Read and Modify Write
E0
None
17
RMWOUT
0
1
0
1
1
1
0
1
1
1
0
RMW end
EE
None
18
ASCSET
0
1
0
1
0
1
0
1
0
1
0
Area Scroll Set
AA
4 byte
19
SCSTART
0
1
0
1
0
1
0
1
0
1
1
Scroll Start Set
AB
1 byte
20
OSCON
0
1
0
1
1
0
1
0
0
0
1
Internal OSC on
D1
None
21
OSCOFF
0
1
0
1
1
0
1
0
0
1
0
Internal OSC off
D2
None
22
PWRCTL
0
1
0
0
0
1
0
0
0
0
0
Power Control
20
1 byte
23
VOLCTR
0
1
0
1
0
0
0
0
0
0
1
EC control
81
2 byte
24
VOLUP
0
1
0
1
1
0
1
0
1
1
0
EC increase 1
D6
None
25
VOLDOWN
0
1
0
1
1
0
1
0
1
1
1
EC decrease 1
D7
None
26
RESERVED
0
1
0
1
0
0
0
0
0
1
0
Not Use
82
EPSRRD1
0
1
0
0
1
1
1
1
1
0
0
READ Register1
7C
None
28
EPSRRD2
0
1
0
0
1
1
1
1
1
0
1
READ Register2
7D
None
29
NOP
0
1
0
0
0
1
0
0
1
0
1
NOP Instruction
25
None
30
STREAD
0
0
1
MRW Set
0
1
0
0
0
0
0
0
0
0
1
Memory R/W Register Set
01
1 byte
32
CVV
0
1
0
0
0
0
0
0
1
0
0
Control Vout-V0
04
1 byte
33
CATR
0
1
0
0
0
0
0
0
1
1
0
Close Autoread
06
1 byte
34
Ver 1.7
Status Read
Function
Hex Parameter Index
27
Status Read
37/96
31
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ST7632
EEOK
0
1
0
0
0
0
0
0
1
1
1
EEPROM Function Strat
07
1 byte
35
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Red1 Set
0
1
0
0
0
1
0
0
0
0
0
FRAME 1 Red PWM Set 20
16 byte
1
Red2 Set
0
1
0
0
0
1
0
0
0
0
1
FRAME 2 Red PWM Set 21
16 byte
2
Red3 Set
0
1
0
0
0
1
0
0
0
1
0
FRAME 3 Red PWM Set 22
16 byte
3
Red4 Set
0
1
0
0
0
1
0
0
0
1
1
FRAME 4 Red PWM Set 23
16 byte
4
Grn1 Set
0
1
0
0
0
1
0
0
1
0
0
FRAME 1 Grn PWM Set
24
16 byte
5
Grn2 Set
0
1
0
0
0
1
0
0
1
0
1
FRAME 2 Grn PWM Set
25
16 byte
6
Grn3 Set
0
1
0
0
0
1
0
0
1
1
0
FRAME 3 Grn PWM Set
26
16 byte
7
Grn4 Set
0
1
0
0
0
1
0
0
1
1
1
FRAME 4 Grn PWM Set
27
16 byte
8
Blu1 Set
0
1
0
0
0
1
0
1
0
0
0
FRAME 1 Blu PWM Set
28
16 byte
9
Blu2 Set
0
1
0
0
0
1
0
1
0
0
1
FRAME 2 Blu PWM Set
29
16 byte
10
Blu3 Set
0
1
0
0
0
1
0
1
0
1
0
FRAME 3 Blu PWM Set
2A
16 byte
11
Blu4 Set
0
1
0
0
0
1
0
1
0
1
1
FRAME 4 Blu PWM Set
2B
16 byte
12
ANASET
0
1
0
0
0
1
1
0
0
1
0
Analog
32
4 byte
13
DITHOFF
0
1
0
0
0
1
1
0
1
0
0
Dithering Circuit Off
34
None
14
DITHON
0
1
0
0
0
1
1
0
1
0
1
Dithering Circuit On
35
None
15
EPCTIN
0
1
0
1
1
0
0
1
1
0
1
Control EEPROM
CD
1 byte
17
EPCOUT
0
1
0
1
1
0
0
1
1
0
0
Cancel EEPROM
CC
None
18
EPMWR
0
1
0
1
1
1
1
1
1
0
0
Write to EEPROM
FC
None
19
EPMRD
0
1
0
1
1
1
1
1
1
0
1
Read from EEPROM
FD
None
20
Ext=1
Command
Function
Hex Parameter Index
Ext=1 or Ext=0
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Ext In
0
1
0
0
0
1
1
0
0
0
0
Ext=0 Set
30
None
--
Ext Out
0
1
0
0
0
1
1
0
0
0
1
Ext=1 Set
31
None
--
Ver 1.7
38/96
Function
Hex Parameter Index
2006/08/15
ST7632
EXT=”0”
(1) Display ON (DISON) Command: 1; Parameter: None (AFH)
It is used to turn the display on. When the display is turned on, segment outputs and common outputs are generated at the
level corresponding to the display data and display timing. You can’t turn on the display as long as the sleep mode is
selected. Thus, whenever using this command, you must cancel the sleep mode first.
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
1
1
1
1
Command
(2) Display OFF (DISOFF) Command: 1; Parameter: None (AEH)
It is used to forcibly turn the display off. As long as the display is turned off, every on segment and common outputs are
forced to Vss level.
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
1
1
1
0
(3) Normal display (DISNOR) Command: 1; Parameter: None (A6H)
It is used to normally highlight the display area without modifying contents of the display data RAM.
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
0
1
1
0
(4) Inverse display (DISINV) Command: 1; Parameter: None (A7)
It is used to inversely highlight the display area without modifying contents of the display data RAM. This command does
not invert non-display areas in case of using partial display.
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
0
1
1
1
(5) Common scan (COMSCAN) Command: 1; Parameter: 1 (BBH)
It is used to specify the direction the common output direction. This command helps increasing degrees of freedom of
wiring on the LCD panel.
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
1
0
1
1
1
0
1
1
－
Parameter1 (P1)
１
１
0
*
*
*
*
*
P12
P11
P10
Command Scan direction
When 1/132 is selected for the display duty, pins and common output are scanned in the order shown below.
Common scan direction
P12 P11 P10
COM0 pin
Ver 1.7
COM65 pin
COM66 pin
COM131 pin
0
0
0
0
à
65
66
à
131
0
0
1
0
à
65
131
à
66
0
1
0
65
à
0
66
à
131
0
1
1
65
à
0
131
à
66
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ST7632
Common scan direction
Original graphic :
Com0
Com66
Com65
Com131
P12:P11:P10:0:0:0 (0à65,66à131)
P12:P11:P10:0:0:1 (0à65, 131à66)
Com0
Com66
Com65
Com131
Com0
Com131
Com65
Com66
P12:P11:P10:0:1:0 (65à0, 66à131)
P12:P11:P10:0:1:1 (65à0, 131à66)
Com65
Com66
Com0
Com131
Com65
Com131
Com0
Com66
Ver 1.7
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ST7632
(6) Display control (DISCTL) Command: 1; Parameter: 3 (CAH)
This command and succeeding parameters are used to perform the display timing-related setups. This command must be
selected before using SLPOUT. Don’t change this command while the display is turned on.
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
1
1
0
0
1
0
1
0
－
Parameter1(P1)
1
1
0
*
*
*
P14
P13
P12
*
*
CL dividing ratio,F1 and F2
drive pattern.
Parameter2(P2)
1
1
0
0
0
P25
P24
P23
P22
P21
P20 Drive duty
Parameter3(P3)
1
1
0
*
*
*
P34
P33
P32
P31
P30 FR inverse-set value
P1: it is used to specify the CL dividing ratio.
P10, P11: do not use
P14, P13, P12: CL dividing ratio. They are used to change number of dividing stages of external or internal clock.
P14
P13
P12
CL dividing ratio
0
0
0
Not divide
0
0
1
2 divisions
0
1
0
Not divide
0
1
1
Not divide
P2: It is used to specify the duty of the module on block basis.
Duty
*
*
P25
P24
P23
P22
P21
P20
(Numbers of display lines)/4-1
Example: 1/128 duty
0
0
0
1
1
1
1
1
128/4-1=31
P3: It is used to specify number of lines to be inversely highlighted on LCD panel from P33 to P30 (lines can be inversely
highlighted in the range of 2 to 16)
Inversely highlighted line
*
*
*
P34
P33
P32
P31
P30
Inversely highlighted lines-1
Example: 11H
0
0
0
0
1
0
1
0
11-1=10
Example: 13H
0
0
0
1
1
1
0
0
13-1=12
In the default, 11H inverse highlight is selected.
P34=”0”: Inversion occur every frame. P34=”1”: Independent from frames.
(7) Sleep in (SPLIN) Command: 1; Parameter: None (95H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
1
0
1
0
1
(8) Sleep out (SLPOUT) Command: 1;Parameter: None (94H)
Command
Ver 1.7
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
1
0
1
0
0
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ST7632
(9) Page address set (PASET) Command: 1; Parameter: 2 (75H)
When MPU makes access to the display data RAM, this command and succeeding parameters are used to specify the
page address area. As the addresses are incremented from the start to the end page in the page-direction scan, the
column address is incremented by 1 and the page address is returned to the start page. Note that the start and end page
must be specified as a pair. Also, the relation “start page <end page” must be maintained.
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
0
1
1
1
0
1
0
1
－
Parameter1(P1)
1
1
0
P17
P16
P15
P14
P13
P12
P11
P10 Start page
Parameter2(P2)
1
1
0
P27
P26
P25
P24
P23
P22
P21
P20 End page
(10) Column address set (CASET) Command: 1; Parameter: 2 (15H)
When MPU makes access to the display data RAM, this command and succeeding parameters are used to specify the
column address area. As the addresses are incremented from the start to the end column in the column-direction scan, the
page address is incremented by 1 and the column address is returned to the start column. Note that the start and end page
must be specified as a pair. Also, the relation “start column <end column” must be maintained.
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
0
0
0
1
0
1
0
1
－
Parameter1(P1)
1
1
0
P17
P16
P15
P14
P13
P12
P11
P10
Start address
Parameter2(P2)
1
1
0
P27
P26
P25
P24
P23
P22
P21
P20
End address
(11) Data control (DATCTL) Command: 1;Parameter: 3 (BCH)
This command and succeeding parameters are used to perform various setups needed when MPU operates display data
stored on the built-in RAM.
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
0
1
0
1
0
1
1
1
1
0
0
－
Normal/Reverse display of
Parameter1(P1)
1
1
0
*
*
*
*
*
P12
P11
P10 page address and
page-address scan direction.
Parameter2(P2)
1
1
0
*
*
*
*
*
*
*
P20 RGB arrangement
Parameter3(P3)
1
1
0
*
*
P35
P34
P33
P32
P31
P30 Gray-scale setup
P1: It is used to specify the normal or inverse display of the page address and also to specify the page address scanning
direction.
P10: Normal/Reverse display of the page address. P10=0: Normal and P10=1: Reverse
P11: Normal/Reverse turn of column address. P11=0: Normal rotation and P11=1: Reverse rotation.
P12: Address-scan direction. P12=0: In the column direction and P12=1: In the page direction.
Ver 1.7
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ST7632
Page address and page-address scan direction.
P12=0 Column direction
P11=0
P11=1
P10=0
0
1
2
P10=1
131
130
129
129
130
131
2
1
0
0
131
1
130
2
129
129
2
130
1
131
0
1
130
2
129
129
2
130
1
131
0
P12=1 Page direction
P11=0
P11=1
P10=0
0
1
2
0
131
P10=1
131
130
129
129
130
131
2
1
0
Examples of Normal or Inverse page/column scan direction
Ver 1.7
43/96
2006/08/15
ST7632
c
ST7632
( BUMP SIDE )
ST7632
( BUMP SIDE )
(a) COMMAND #BCH, DATA #00H
(b) COMMAND #BCH, DATA #01H
ST7632
( BUMP SIDE )
ST7632
( BUMP SIDE )
(c) COMMAND #BCH, DATA #02H
(d) COMMAND #BCH, DATA #03H
Different RAM accessing setupunder COMMAND #BBH, DATA #00H
(a) COMMAND #BCH, DATA #00H
(b) COMMAND #BCH, DATA #01H
(c) COMMAND #BCH, DATA #02H
(d) COMMAND #BCH, DATA #03H
Ver 1.7
44/96
2006/08/15
ST7632
ST7632
( BUMP SIDE )
ST7632
( BUMP SIDE )
(e) COMMAND #BCH, DATA #04H
(f) COMMAND #BCH, DATA #05H
ST7668
( BUMP SIDE )
ST7632
( BUMP SIDE )
(g) COMMAND #BCH, DATA #06H
(h) COMMAND #BCH, DATA #07H
Figure 8.2.3 Different RAM accessing setup when CSEL=0 under COMMAND #BBH, DATA #00H (continue)
(e) COMMAND #BCH, DATA #04H
(f) COMMAND #BCH, DATA #05H
(g) COMMAND #BCH, DATA #06H
Ver 1.7
45/96
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ST7632
P2: RGB arrangement. This parameter allows you to change RGB arrangement of the segment output according to RGB
arrangement on the LCD panel. In this case, writing position of data {R=(D7, D6, D5), G=(D4, D3, D2), B=(D1, D0)} on the
display memory is changed.
Line
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
…
SEG395
Even page
R
G
B
R
G
B
R
G
…
B
Odd page
R
G
B
R
G
B
R
G
…
B
1
B
G
R
B
G
R
B
G
…
R
2
B
G
R
B
G
R
B
G
…
R
P20
0
1
P3: Gray scale setup. Using this parameter, you can a select desired display colors between the 256 colors (8 gray-scale)
or 4096 colors (16 gray-scales) for the display color. For 16 gray-scale display, you can select the Type A, Type B, 65K,
262K, and 16M display mode depending on the difference in RGB data arrangement.
P35
P34
P33
P32
P31
P30
Numbers of gray-scale
0
0
0
0
0
1
8 gray-scale
0
0
0
1
0
0
16 gray-scale display 4K
0
0
1
0
0
0
16-gray 65K
0
1
0
0
0
0
16-gray 262K
1
0
0
0
0
0
16-gray 16M
(12) 256-color position set (RGBSET8) Command: 1;Parameter: 20 (CEH)
When turning on 256-color display (8 gray-scale), this command allows you to choose colors to represent each of red,
green and blue from 4096 colors.
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
1
1
0
0
1
1
1
0
--
Parameter(P1)
1
1
0
*
*
*
*
P13
P12
P11
P10
Intermediate red tone
000
Intermediate red tone
Parameter(P8)
1
1
0
*
*
*
*
P83
P82
P81
P80
111
Intermediate green tone
Parameter(P9)
1
1
0
*
*
*
*
P93
P92
P91
P90
000
Intermediate green
Parameter(P16)
1
1
0
*
*
*
*
P163
P162
P161
P160
tone 111
Parameter(P17)
1
1
0
*
*
*
*
P173
P172
P171
P170
Intermediate blue tone 00
Parameter(P20)
1
1
0
*
*
*
*
P203
P202
P201
P200
Intermediate blue tone 11
Data (Red and Green: 3 bits and Blue: 2 bits) to be written from MPU to the DDRAM are converted to 4-bit data before the
write operation takes place. When reading data from the DDRAM, data on red and green are converted to 3 bits and that
on blue are converted 2 bits before the output.
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(13) Memory write (RAMWR) Command: 1;Parameter: Numbers of data written (5CH)
When MPU writes data to the display memory, this command turns on the data entry mode. Entering this command always
sets the page and column address at the start address. You can rewrite contents of the display data RAM by entering data
succeeding to this command. At the same time, this operation increments the page or column address as applicable. The
write mode is automatically cancelled if any other command is entered.
1. 8-bit bus
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
0
1
0
1
1
1
0
0
－
Parameter
1
1
0
A0
RD
RW
D15
D14
…
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
*
*
…
*
*
0
1
0
1
1
1
0
0
Memory write
parameter
1
1
0
Data to be written
Data to be written
2. 16-bit bus
Data to be written
Write date
(14) Memory read (RAMRD) Command: 1; Parameter: Numbers of data read (5DH)
When MPU read data from the display memory, this command turns on the data read mode. Entering this command
always sets the page and column address at the start address. After entering this command, you can read contents of the
display data RAM. At the same time, this operation increments the page or column address as applicable. The data read
mode is automatically cancelled if any other command is entered.
1. 8-bit bus
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
0
1
0
1
1
1
0
1
--
Parameter
1
0
1
A0
RD
RW
D15
Command
0
1
0
*
parameter
1
0
1
Data to be read
Data to be read
2. 16-bit bus
D14
….
D9
D8
*
*
*
*
D7
D6
D5
D4
D3
D2
D1
D0
Function
0
1
0
1
1
1
0
1
Memory read
Data to be read
Read date
(15) Partial in (PTLIN) Command: 1; Parameter: 2 (A8H)
This command and succeeding parameters specify the partial display area. This command is used to turn on partial display
of the screen (dividing screen by lines) in order to save power. Since ST7632 processes the liquid crystal display signal on
4-line basis (block basis), the display and non-display areas are also specified on 4-bit line (block basis).
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
1
0
1
0
1
0
0
0
--
Parameter(P1)
1
1
0
*
*
P15
P14
P13
P12
P11
P10
Start block address
Parameter(P2)
1
1
0
*
*
P25
P24
P23
P22
P21
P20
End block address
A block address that can be specified for the partial display must be the display one (don’t try to specify an address not to
be displayed when scrolled).
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ST7632
(16) Partial out (PTLOUT) Command: 1; Parameter: 0 (A9H)
This command is used to exit from the partial display mode.
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
1
0
0
1
(17) Read modify write in (RMWIN) Command: 1; Parameter: 0 (E0H)
This command is used along with the column address set command, page address set command and read modify write out
command. This function is used when frequently modifying data to specify a specific display area such as blinking cursor.
First set a specific display area using the column and page address commands. Then, enter this command to set the
column and page addresses at the start address of the specific area. When this operation is complete, the column (page)
address won’t be modified by the display data read command. It is incremented only when the display data write command
is used. You can cancel this mode by entering the read modify write out or any other command
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
0
0
0
0
Page address set
Column address set
Read-modify-write cycle
Dummy read
Data read
Data write
NO
Is modification
Complete
YES
END
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(18) Read modify write out (RMWOUT) Command: 1; Parameter: 0 (EEH)
Enter this command cancels the read modify write mode
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
1
1
1
0
Command
(19) Area scroll set (ASCSET) Command: 1; Parameter: 4 (AAH)
It is used when scrolling only the specified portion of the screen (dividing the screen by lines). This command and
succeeding parameters specify the type of area scroll, FIX area and scroll area.
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
1
0
1
0
1
0
1
0
Parameter(P1)
1
1
0
*
*
P15
P14
P13
P12
P11
P10
Top block address
Parameter(P2)
1
1
0
*
*
P25
P24
P23
P22
P21
P20
Bottom block address
Parameter(P3)
1
1
0
*
*
P35
P34
P33
P32
P31
P30
Number of specified blocks
Parameter(P4)
1
1
0
*
*
*
*
*
*
P41
P40
Area scroll mode
--
P4: It is used to specify an area scroll mode.
P41
P40
Type of area scroll
0
0
Center screen scroll
0
1
Top screen scroll
1
0
Bottom screen scroll
1
1
Whole screen scroll
Center screen scroll
Fixed area
Ver 1.7
Top screen scroll
Bottom screen scroll
Whole screen scroll
Scroll area
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ST7632
Since ST7632 processes the liquid crystal display signals on the four-line basis (block basis), FIX and scroll areas are also
specified on the four-line basis (block basis).
DDRAM address corresponding to the top FIX area is set in the block address incrementing direction starting with 0 block.
DDRAM address corresponding to the bottom FIX area is set in the block address decreasing direction starting with 41st
block. Other DDRAM blocks excluding the top and bottom FIX areas are assigned to the scroll + background areas.
P1: It is used to specify the top block address of the scroll+ background areas. Specify the 0th block for the top screen scroll
or whole screen scroll.
P2: It specifies the bottom address of the scroll+ background areas. Specify the 32th block for the bottom or whole screen
scroll.
Required relation between the start and end blocks (top block address<bottom block address) must be maintained.
P3: It specifies a specific number of blocks {Numbers of (Top FIX area +Scroll area) block-1}. When the bottom scroll or
whole screen scroll, the value is identical with P2.
You can turn on the area scroll function by executing the area scroll set command first and then specifying the display start
block of the scroll area with the scroll start set command.
[Area Scroll Setup Example]
In the center screen scroll of 1/120 duty (display range: 120 lines=30 blocks), if 8 lines=2 blocks and 8 lines=2 blocks are
specified for the top and bottom FIX areas, 104 lines =26 blocks is specified for the scroll areas, respectively, 12 lines = 3
blocks on the DDRAM are usable as the background area. Value of each parameter at this time is as shown below.
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
P1
1
1
0
*
*
0
0
0
0
1
0
Top block address = 2
P2
1
1
0
*
*
0
1
1
1
1
0
Bottom block address = 30
P3
1
1
0
*
*
0
1
1
0
1
1
Number of specific blocks = 27
P4
1
1
0
*
*
*
*
*
*
0
0
Area scroll mode = center
(20) Scroll start address set (SCSTART) Command:1 Parameter: 1 (ABH)
This command and succeeding parameters are used to specify the start block address of the scroll area. Note that you
must execute this command after executing the area scroll set command. Scroll becomes available by dynamically
changing the start block address.
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
1
0
1
0
1
0
1
1
Parameter(P1)
1
1
0
*
*
P15
P14
P13
P12
P11
P10
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Function
-Start block address
2006/08/15
ST7632
(21) Internal oscillation on (OSCON) Command: 1; Parameter: 0 (D1H)
This command turns on the internal oscillation circuit. It is valid only when the internal oscillation circuit of CLS = HIGH is
used.
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
1
0
0
0
1
(22) Internal oscillation off (OSOFF) Command: 1; Parameter: 0 (D2H)
It turns off the internal oscillation circuit. This circuit is turned off in the reset mode.
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
1
0
0
1
0
(23) Power control set (PWRCTR) Command: 1; Parameter: 1 (20H)
This command is used to turn on or off the Booster circuit, voltage regulator circuit, and follower voltage.
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
1
0
0
0
1
0
0
0
0
Parameter(P1)
1
1
0
*
*
*
*
P13
*
P11
P10
Function
-LCD drive power
P10: It turns on or off the regulator circuit.
P10 = “1”: ON. P10 =” 0”: OFF
P11: It turns on or off the follower circuit.
P11 = “1”: ON. P11 =” 0”: OFF
P12: can not use
P13:It turns on or off the booster circuit.
P13 = “1”: ON. P13 =” 0”: OFF
(24) Electronic volume control (VOLCTR) Command: 1; Parameter: 2 (81H)
The command is used to program the optimum LCD supply voltage VLCD. Reference to 7.10.2
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
1
0
0
0
0
0
0
1
Parameter(P1)
1
1
0
*
*
P15
P14
P13
P12
P11
P10
Set Vop[5:0]
Parameter(P2)
1
1
0
*
*
*
*
*
P18
P17
P16
Set Vop[8:6]
Function
--
(25) Increment electronic control (VOLUP) Command: 1; Parameter: 0 (D6H)
With the VOLUP and VOLDOWN command the VLCD voltage and therewith the contrast of the LCD can be adjusted.
This command increments electronic control value Vop[5:0]of voltage regulator circuit by 1.
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
1
0
1
1
0
If you set the electronic control value to 111111, the control value is set to 000000 after this command has been executed.
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(26) Decrement electronic control (VOLDOWN) Command: 1; Parameter: 0 (D7H)
With the VOLUP and VOLDOWN command the VLCD voltage and therewith the contrast of the LCD can be adjusted.
This command decrements electronic control value Vop[5:0]of voltage regulator circuit by 1.
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
1
0
1
1
1
Command
If you set the electronic control value to 000000, the control value is set to 111111 after this command has been executed.
Table 8.1.1 Possible Vop[5:0] values
Electronic Control Value
Decimal Equivalent
VLCD Offset
111111
31
+1240 mV
111110
30
+1200 mV
111101
29
+1160 mV
…
…
…
000010
2
+80 mV
000001
1
+40 mV
000000
0
0 mV
111111
-1
-40 mV
111110
-2
-80 mV
…
…
…
100010
-30
-1200 mV
100001
-31
-1240 mV
100000
-32
-1280mV
(27) Reserved (82H)
Do not use this command
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
0
0
0
1
0
(28) Read Register 1 (EPSRRD1) Command: 1; Parameter: 0 (7CH)
Issue the EPSRRD1 and STREAD (Status Read) commands in succession to read the Electronic Control value.
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
1
1
1
1
0
0
Issue the Status Read command immediately after this command. Also, always issue the NOP command after the
STREAD (Status Read) command.
(29) Read Register 2 (EPSRRD2) Command: 1 ;Parameter: 0 (7DH)
Issue the EPSRRD1 and STREAD (Status Read) commands in succession to read the built-in resistance ratio.
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
1
1
1
1
0
1
Issue the Status Read command immediately after this command. Also, always issue the NOP command after the
STREAD (Status Read) command.
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(30) Non-operating (NOP) Command: 1; Parameter: 0 (25H)
This command does not affect the operation.
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
0
0
1
0
1
Command
This command, however, has the function of canceling the IC test mode. Thus, it is recommended to enter it periodically to
prevent malfunctioning due to noise and such.
(31) Status read (STREAD) Command: 1; Parameter: None
It is the command for reading the internal condition of the IC. One status can be displayed depending on the setting.
A0
RD
RW
0
0
1
Command
D7
D6
D5
D4
D3
D2
D1
D0
Status data
Status after reset or after NOP operation
D7: Area scroll mode
Refer to P41 (ASCSET)
D6: Area scroll mode
Refer to P40 (ASCSET)
D5: RMW on/off
0 : Out
1 : In
D4: Scan direction
0 : Column
1 : Page
D3: Display ON/OFF
0 : OFF
1 : ON
D2: EEPROM access
0: OutAccess
1: InAccess
D1: Display normal/inverse
0 : Inverse
1 : Normal
D0: Partial display
0 : OFF
1 : ON
(32) Memory R/W Register Set (MRW Set) Command: 1; Parameter: 1 (01H)
This command can set memory read/write register.It must be issued in the initial flow and set parameter =F0H.
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
0
0
0
0
0
0
0
1
--
Parameter(P1)
1
1
0
1
1
1
1
0
0
0
0
F0H
(33) Control Vout V0(CVV) Command: 1; Parameter: 1 (04H)
Using this command can control the relationship of VOUT and V0. It must be issued in the initial flow and set parameter
=04H.
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
0
0
0
0
0
1
0
0
--
Parameter(P1)
1
1
0
0
0
0
0
0
1
1
0
06H
(34) Close Autoread (CATR) Command: 1; Parameter: 1 (06H)
This command is used for closing the autoread function of EEPROM. It must be issued in the initial flow and set parameter
=41H.
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
0
0
0
0
1
1
0
0
--
Parameter(P1)
1
1
0
0
1
0
0
0
0
0
1
41H
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Function
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ST7632
(35) EEPROM Function Strat(EEOK) Command:1;Parameter:1(07)
In the OTP read flow,this command can increase the clock of EEPROM.It must be issued in the initial flow and set
parameter=1BH.
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
0
0
0
0
0
1
1
1
--
Parameter(P1)
1
1
0
0
0
0
1
1
0
1
1
1BH
EXT=”1”
(1)Set Red 1 value (Red1 set) Command: 1; Parameter: 16 (20H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Red1 Set
0
1
0
0
0
1
0
0
0
0
0
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
0
0
1
0
0
0
0
0
Parameter1(P1)
1
1
0
*
*
*
P14 P13 P12 P11 P10 Set red level 0 and 1st frame
Parameter2(P2)
1
1
0
*
*
*
P24 P23 P22 P21 P20 Set red level 1 and 1st frame
Parameter14(P14)
1
1
0
*
*
*
P144 P143 P142 P141 P140 Set red level 13 and 1st frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set red level 15 and 1st frame
FRAME 1 Red PWM Set
Function
－
(2)Set Red 2 value (Red2 set) Command: 1; Parameter: 16 (21H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Red2 Set
0
1
0
0
0
1
0
0
0
0
1
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
0
0
1
0
0
0
0
0
Parameter1(P1)
1
1
0
*
*
*
P14 P13 P12 P11 P10 Set red level 0 and 2nd frame
Parameter2(P2)
1
1
0
*
*
*
P24 P23 P22 P21 P20 Set red level 1 and 2nd frame
Parameter14(P14)
1
1
0
*
*
*
P144 P143 P142 P141 P140 Set red level 13 and 2nd frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set red level 15 and 2nd frame
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Function
FRAME 2 Red PWM Set
Function
－
2006/08/15
ST7632
(3) Set Red 3 value (Red3 set) Command: 1; Parameter: 16 (22H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Red3 Set
0
1
0
0
0
1
0
0
0
1
0
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
0
0
1
0
0
0
0
0
Parameter1(P1)
1
1
0
*
*
*
P14 P13 P12 P11 P10 Set red level 0 and 3rd frame
Parameter2(P2)
1
1
0
*
*
*
P24 P23 P22 P21 P20 Set red level 1 and 3rdframe
Parameter14(P14)
1
1
0
*
*
*
P144 P143 P142 P141 P140 Set red level 13 and 3rd frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set red level 15 and 3rd frame
FRAME 3 Red PWM Set
Function
－
(4) Set Red 4 value (Red4 set) Command: 1; Parameter: 16 (23H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Red4 Set
0
1
0
0
0
1
0
0
0
1
1
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
0
0
1
0
0
0
0
0
Parameter1(P1)
1
1
0
*
*
*
P14 P13 P12 P11 P10 Set red level 0 and 4th frame
Parameter2(P2)
1
1
0
*
*
*
P24 P23 P22 P21 P20 Set red level 1 and 4thframe
Parameter14(P14)
1
1
0
*
*
*
P144 P143 P142 P141 P140 Set red level 13 and 4th frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set red level 15 and 4th frame
Ver 1.7
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Function
FRAME 4 Red PWM Set
Function
－
2006/08/15
ST7632
The default value of Red level set
RED1SET
RED2SET
RED3SET
RED4SET
FRAM1
FRAM2
FRAM3
FRAME4
red level0
00
00
00
00
red level1
03
03
03
03
red level2
06
06
06
06
red level3
08
08
08
09
red level4
0B
0B
0B
0C
red level5
0E
0E
0E
0D
red level6
10
11
10
11
red level7
12
13
12
13
red level8
14
15
14
15
red level9
17
17
17
16
red level10
19
19
19
18
red level11
1A
1B
1A
1B
red level12
1C
1C
1C
1B
red level13
1D
1D
1D
1E
red level14
1E
1E
1E
1F
red level15
1F
1F
1F
1F
(5) Set Green 1 value (Grn1 set) Command: 1; Parameter: 16 (24H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Grn 1 Set
0
1
0
0
0
1
0
0
1
0
0
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
0
0
1
0
0
0
0
0
Parameter1(P1)
1
1
0
*
*
*
P14 P13 P12 P11 P10 Set green level 0 and 1st frame
Parameter2(P2)
1
1
0
*
*
*
P24 P23 P22 P21 P20 Set green level 1 and 1st frame
Parameter14(P14)
1
1
0
*
*
*
P144 P143 P142 P141 P140 Set green level 13 and 1st frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set green level 15 and 1st frame
Ver 1.7
56/96
Function
FRAME 1 Grn PWM Set
Function
－
2006/08/15
ST7632
(6) Set Green 2 value (Grn2 set) Command: 1;Parameter: 16 (25H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Grn2 Set
0
1
0
0
0
1
0
0
1
0
1
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
0
0
1
0
0
0
0
0
Parameter1(P1)
1
1
0
*
*
*
P14 P13 P12 P11 P10 Set green level 0 and 2nd frame
Parameter2(P2)
1
1
0
*
*
*
P24 P23 P22 P21 P20 Set green level 1 and 2nd frame
Parameter14(P14)
1
1
0
*
*
*
P144 P143 P142 P141 P140 Set green level 13 and 2nd frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set green level 15 and 2nd frame
FRAME 2 Grn PWM Set
Function
－
(7) Set Green 3 value (Grn3 set) Command: 1; Parameter: 16 (26H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Grn3 Set
0
1
0
0
0
1
0
0
1
0
1
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
0
0
1
0
0
0
0
0
Parameter1(P1)
1
1
0
*
*
*
P14 P13 P12 P11 P10 Set green level 0 and 3rd frame
Parameter2(P2)
1
1
0
*
*
*
P24 P23 P22 P21 P20 Set green level 1 and 3rdframe
Parameter14(P14)
1
1
0
*
*
*
P144 P143 P142 P141 P140 Set green level 13 and 3rd frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set green level 15 and 3rd frame
Ver 1.7
57/96
Function
FRAME 3 Grn PWM Set
Function
－
2006/08/15
ST7632
(8) Set Green 4 value (Grn4 set) Command: 1;Parameter: 16 (27H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Grn4 Set
0
1
0
0
0
1
0
0
1
1
1
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
0
0
1
0
0
0
0
0
Parameter1(P1)
1
1
0
*
*
*
P14
P13 P12 P11 P10 Set green level 0 and 4th frame
Parameter2(P2)
1
1
0
*
*
*
P24
P23 P22 P21 P20 Set green level 1 and 4thframe
Parameter14(P14)
1
1
0
*
*
*
P144 P143 P142 P141 P140 Set green level 13 and 4th frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set green level 15 and 4th frame
FRAME 4 Grn PWM Set
Function
－
The default value of Green level set
GRN1SET
GRN2SET
GRN3SET
GRN4SET
FRAM1
FRAM2
FRAM3
FRAME4
green level0
00
00
00
00
green level1
03
03
03
03
green level2
06
06
06
06
green level3
08
08
08
09
green level4
0B
0B
0B
0C
green level5
0E
0E
0E
0D
green level6
10
11
10
11
green level7
12
13
12
13
green level8
14
15
14
15
green level9
17
17
17
16
green level10
19
19
19
18
green level11
1A
1B
1A
1B
green level12
1C
1C
1C
1B
green level13
1D
1D
1D
1E
green level14
1E
1E
1E
1F
green level15
1F
1F
1F
1F
Ver 1.7
58/96
2006/08/15
ST7632
(9) Set Blue 1 value (Blu 1 set) Command: 1; Parameter: 16 (28H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Grn 1 Set
0
1
0
0
0
1
0
0
1
0
0
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
0
0
1
0
0
0
0
0
Parameter1(P1)
1
1
0
*
*
*
P14 P13 P12 P11 P10 Set blue level 0 and 1st frame
Parameter2(P2)
1
1
0
*
*
*
P24 P23 P22 P21 P20 Set blue level 1 and 1st frame
Parameter14(P14)
1
1
0
*
*
*
P144 P143 P142 P141 P140 Set blue level 13 and 1st frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set blue level 15 and 1st frame
FRAME 1 Blu PWM Set
Function
－
(10) Set Blue 2 value (Blu2 set) Command: 1; Parameter: 16 (29H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Grn2 Set
0
1
0
0
0
1
0
0
1
0
1
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
0
0
1
0
0
0
0
0
Parameter1(P1)
1
1
0
*
*
*
P14 P13 P12 P11 P10 Set blue level 0 and 2nd frame
Parameter2(P2)
1
1
0
*
*
*
P24 P23 P22 P21 P20 Set blue level 1 and 2nd frame
Parameter14(P14)
1
1
0
*
*
*
P144 P143 P142 P141 P140 Set blue level 13 and 2nd frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set blue level 15 and 2nd frame
Ver 1.7
59/96
Function
FRAME 2 Blu PWM Set
Function
－
2006/08/15
ST7632
(11) Set Blue 3 value (Blu3 set) Command: 1; Parameter: 16 (2AH)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Grn3 Set
0
1
0
0
0
1
0
0
1
1
0
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
0
0
1
0
0
0
0
0
Parameter1(P1)
1
1
0
*
*
*
P14
P13
P12
P11
P10 Set blue level 0 and 3rd frame
Parameter2(P2)
1
1
0
*
*
*
P24
P23
P22
P21
P20 Set blue level 1 and 3rdframe
Parameter14(P14)
1
1
0
*
*
*
P144 P143 P142 P141 P140 Set blue level 13 and 3rd frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set blue level 15 and 3rd frame
FRAME 3 Blu PWM Set
Function
－
(12) Set Blue 4 value (Blu4 set) Command: 1; Parameter: 16 (2BH)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Grn4 Set
0
1
0
0
0
1
0
0
1
1
1
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
0
0
1
0
0
0
0
0
Parameter1(P1)
1
1
0
*
*
*
P14 P13 P12 P11 P10 Set blue level 0 and 4th frame
Parameter2(P2)
1
1
0
*
*
*
P24 P23 P22 P21 P20 Set blue level 1 and 4thframe
Parameter14(P14)
1
1
0
*
*
*
P144 P143 P142 P141 P140 Set blue level 13 and 4th frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set blue level 15 and 4th frame
Ver 1.7
60/96
Function
FRAME 4 Blu PWM Set
Function
－
2006/08/15
ST7632
The default value of Blue level set
GRN1SET
GRN2SET
GRN3SET
GRN4SET
FRAM1
FRAM2
FRAM3
FRAME4
blue level0
00
00
00
00
blue level1
03
03
03
03
blue level2
06
06
06
06
blue level3
08
08
08
09
blue level4
0B
0B
0B
0C
blue level5
0E
0E
0E
0D
blue level6
10
11
10
11
blue level7
12
13
12
13
blue level8
14
15
14
15
blue level9
17
17
17
16
blue level10
19
19
19
18
blue level11
1A
1B
1A
1B
blue level12
1C
1C
1C
1B
blue level13
1D
1D
1D
1E
blue level14
1E
1E
1E
1F
blue level15
1F
1F
1F
1F
(13) ANASET Command 1; Parameter: 4 (32H)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
0
0
1
1
0
0
1
0
Parameter1(P1)
1
1
0
*
*
*
*
*
P12
P11
P10 OSC frequency Adjustment
Parameter2(P2)
1
1
0
*
*
*
*
*
*
P21
P20 Booster Efficiency Set
Parameter3(P3)
1
1
0
*
*
*
*
*
P32
P31
P30 Booster setting
Parameter4(P4)
1
1
0
*
*
*
*
*
P42
P41
P40 Bias setting
Ver 1.7
61/96
Function
－
2006/08/15
ST7632
P1: Oscillator frequency adjustment (vdd=2.8V)
P12
P11
P10
CL(kHz)
0
0
0
10
0
0
1
10.5
0
1
0
11.5
0
1
1
13
1
0
0
15
1
0
1
17
1
1
0
20.5
1
1
1
25.5
FRAME=CL/(1/DUTY+1)
Ex:1/132 duty,(P12,P11,P10)=(0,0,0) , Frame=10k/(132+1)=75.19Hz
P2: Booster Efficiency set
(vdd=2.8v)
P21
P20
Frequency(kHz)
0
0
1000
0
1
840
1
0
650
1
1
450
P3: Booster setting
P32
P31
P30
0
0
0
Booster off
0
0
1
2 times boosting circuit
0
1
0
3 times boosting circuit
0
1
1
4 times boosting circuit
1
0
0
5 times boosting circuit
1
0
1
6 times boosting circuit
1
1
0
7 times boosting circuit
1
1
1
8 times boosting circuit
Ver 1.7
62/96
2006/08/15
ST7632
P4: Select LCD bias ratio of the voltage required for driving the LCD.
P42
P41
P40
LCD bias
0
0
0
1/12
0
0
1
1/11
0
1
0
1/10
0
1
1
1/9
1
0
0
1/8
1
0
1
1/7
1
1
0
1/6
1
1
1
1/5
(14) Color Dither OFF (DITHOFF) Command: 1; Parameter: None (34H)
Turn off the dithering circuit.
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
1
0
1
0
0
(15) Color Dither ON (DITHON) Command: 1; Parameter: None (35H)
Turn on the dithering circuit.
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
1
0
1
0
1
(16) Control EEPROM:1 Parameter: 1 (CDH)
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
1
1
0
0
1
1
0
1
Parameter (P1)
1
1
0
*
*
P15
*
*
*
*
*
P15: when setting “1” è The Write Enable of EEPROM will be opened.
P15: when setting “0” è The Read Enable of EEPROM will be opened.
(17) Cancel EEPROM Command: 1;Parameter : None (CCH)
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
0
1
1
0
0
(18) Write data to EEPROM (EPMWR) Command: 1; Parameter: None (FCH)
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
1
1
1
0
0
(19) Read data from EEPROM (EPMWR) Command: 1; Parameter: None (FDH)
Command
Ver 1.7
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
1
1
1
0
1
63/96
2006/08/15
ST7632
EXT=”1” or “0”
(1) Extension instruction disable (EXT IN) Command:1 Parameter: None (30H)
Use the “Ext=0” command table
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
1
0
0
0
0
(2) Extension instruction enable (EXT OUT) Command:1 Parameter: None (31H)
Use the extended command table (EXT=”1”)
Command
Ver 1.7
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
1
0
0
0
1
64/96
2006/08/15
ST7632
EEPROM Setting Following
The ST7632 chip provides the Write and Read function to write the Electronic Control value and Built-in resistance ratio
into and read them from the built-in EEPROM. Using the Write and Read functions, you can store these values appropriate
to each LCP panel. This function is very convenient for user in setting from some different panel’s voltage. But using this
function must attention the setting procedure. Please see the following diagram.
Note: When writing value to EEPROM, the voltage of Voutin must be more than 16V.
Increase or decrease EC value
(command D6 or D7)
( get the V0 value you need)
Display Off (command AEH)
Open Extension mode
(command 31H)
Open EEPROM Enable
(command CDH)
(parameter 20H)
Display On (command AFH)
Wait for 100ms
Turn off the power
Write into EEPROM
(command FCH)
Wait for 100ms
Wait for 100ms
Turn on the power
Disable EEPROM
(command CCH)
Check the EC value
Close Extension mode
(command 30H)
Referential Instruction Setup Flow: Initializing with the built-in Power Supply Circuits
Ver 1.7
65/96
2006/08/15
ST7632
User System Setup by External Pins
Start of Initialization
Power ON(VDD-VSS) Keeping the /RES Pin="L"
Waiting for Stabilizing the Power
/RES Pin="H"
Load EE Flow
Command 06H Parameter 41H
Command 07H Parameter 1BH
Command 31H
Command CDH Parameter 0FH
DELAY 100ms
Command FDH
DELAY 50ms
Command CCH
Command 30H
User Application Setup by Internal Instructions
[Display Duty Select]
[Osc on]
[Sleep out]
User LCD Power Setup by Internal Instructions
[Electronic volume set]
[DC-DC Step-up Register Select]
[Regulator Resistor]
[LCD Bias Register Select]
[Page and Column Set]
Initial Function set
Command 06H---(1)
Parameter 41H----(1)
Command 01H---(2)
Parameter F0H----(2)
Command 04H---(3)
Parameter 06H----(3)
Display on
End of Initialization
Initializing with the Built-in Power Supply Circuits
Ver 1.7
66/96
2006/08/15
ST7632
Example： 128X128 INITIAL FLOW
;;;;;;;;;;;;OTP READ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
COMMAND #06H
;INITIAL FUNCTION(1)
PARA
#41H
;
;
COMMAND #07H
;START OTP
PARA
#1BH
;
;
COMMAND #31H
;SET
EXT=1
COMMAND #CDH
;CONTROL EEPROM ENABLE
PARA
#0FH
;READ ENABLE
CALL
DELAY_100MS
;
COMMAND #FDH
;READ EEPROM
CALL
DELAY_50MS
;
COMMAND #CCH
;DISABLE EEPROM
COMMAND #30H
;
;;;;;;;;;;;;;INITIAL LCD;;;;;;;;;;;;;;;;;;;;;;;;;
COMMAND #CAH
;DISPLAY CONTROL (DISCTL)
PARA
#00000000B
;CL DIVIDINB RATIO
PARA
#00011111B
;DRIVE DUTY (DUTY)/4-1
PARA
#00000000B
;
;
COMMAND #D1H
;TURN ON OSC
;
COMMAND #94H
;SLEEP OUT
;
COMMAND #81H
;ELECTRONIC VOLUME CONTROL
PARA
#00011111B
;B5~B0==>VPR8~VPR5
PARA
#00000011B
;B2~B0==>RA/RB RATIO
;
COMMAND #20H
;POWER CONTROL
PARA
#00001111B
;B0:R,B1:F,B3:B,B2,B4:DON'T USE
;
COMMAND #31H
;SET EXT=1 (OPEN EXT)
;
COMMAND #32H
;ANALOG SET
PARA
#00000000B
;B2~B0==> OSC FREQUENCY ADJUSTMENT
PARA
#00000011B
;B1~B0==> BOOSTER EFFICIENY SET
PARA
#00000001B
;B2~B0==>BOOSTER SET (2X)
PARA
#00000000B
;B2~B0==>BIAS SET
COMMAND
PARA
PARA
PARA
PARA
#32H
#00000000B
#00000011B
#00000101B
#00000000B
;ANALOG SET
;B2~B0==> OSC FREQUENCY ADJUSTMENT
;B1~B0==> BOOSTER EFFICIENY SET
;B2~B0==>BOOSTER SET (6X)
;B2~B0==>BIAS SET
;
;SET EXT=0 (CLOSE EXT)
;
;DATA CONTROL
;USE B2~B0
;USE B0==>0==>RGB,B0==>1==>BGR
;16 GRAY-SCALE DISPLAY TYPE B,4096
;
;COM DIRECTION
;
;
COMMAND #30H
COMMAND
PARA
PARA
PARA
#BCH
#00000011B
#00000000B
#00000100B
COMMAND #BBH
PARA
#00000001B
Ver 1.7
67/96
2006/08/15
ST7632
COMMAND #75H
PARA
#00000000B
PARA
#128
;PAGE ADDRESS SET
;B7~B0==>START PAGEPARA
;;B7~B0==>STOP PAGE
;
COMMAND #15H
;COLUMN ADDRESS SET
PARA
#00000000B
;B7~B0==>START COLUMN
PARA
#128
;B7~B0==>STOP COLUMN(B)
COMMAND #A7H
;INVERSE DISPLAY
;
COMMAND #A6H
;NORMAL DISPLAY
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;----------------INITIAL CODE ------------------;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
COMMAND #06H
;INITIAL FUNCTION (1)
PARA
#41H
;
;
COMMAND #01H
;INITIAL FUNCTION (2)
PARA
#F0H
;
;
;
COMMAND #04H
;INITIAL FUNCTION (3)
PARA
#06H
;
;
COMMAND #AFH
;DISPLAY ON
RET
;
Ver 1.7
68/96
2006/08/15
ST7632
Sleep In/Out
Referential Instruction Setup Flow: Data Displaying
End of Initialization
Display Data RAM Addressing by Instruction
[Initial Display Line]
[Set Page Address]
[Set Column Address]
Write Display Data by Instruction
[Display Data Write]
Turn Display ON/OFF Instruction
[Display ON/OFF]
End of Data Display
Data Displaying
Ver 1.7
69/96
2006/08/15
ST7632
Referential Instruction Setup Flow: Power OFF
Optional Status
Set Sleep In
/RES Pin =“L”
Power OFF (VDD-VSS)
End of Power OFF
VDD
tOFF
/RES
tR
Internal
status
Normal operation
Sleep in
Power off
Power OFF
Ver 1.7
70/96
2006/08/15
ST7632
Partial Display In/Out
Ver 1.7
71/96
2006/08/15
ST7632
9. LIMITING VALUES
In accordance with the Absolute Maximum Rating System; see notes 1 and 2.
Parameter
Symbol
Conditions
Unit
Power Supply Voltage
VDD,VDD1~5
–0.5 ~ 4.0
V
Power supply voltage (VDD standard)
VOUTIN
–0.5 ~ +20
V
Power supply voltage (VDD standard)
V1, V2, V3, V4
0.3 to VOUTIN
V
Input voltage
VIN
–0.5 to VDD+0.5
V
Output voltage
VO
–0.5 to VDD+0.5
V
Operating temperature (Die)
TOPR
–30 to +85
°C
Storage temperature (Die)
TSTR
–40 to +125
°C
VLCD
V1 to V4
VDD
VDD
VSS
VSS
System (MPU) side
VSS
ST7632 chip side
Notes
1. Stresses above those listed under Limiting Values may cause permanent damage to the device.
2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to
VSS unless otherwise noted.
3. Insure that the voltage levels of V1, V2, V3, and V4 are always such that
VOUTIN ≧ V0 ≧ V1 ≧ V2 ≧ V3 ≧ V4 ≧ VSS
Ver 1.7
72/96
2006/08/15
ST7632
10. HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices”).
11. DC CHARACTERISTICS
VDD = 2.6 V to 3.3V; VSS= 0 V; VLCD = 4.0 to 18.0V; Tamb = -30℃ to +85℃; unless otherwise specified.
Rating
Item
Applicable
Symbol Condition
Operating Voltage (1)
Units
VDD1
Min.
Typ.
2.0
—
Pin
Max.
3.3(+10%
V
VSS *1
3.3
V
VSS2
VDD
V
*2
0.2 x VDD V
*2
VDD
V
*3
*3
Range)
VDD2
High-level Input Voltage
VIHC
0.8 x VDD —
Low-level Input Voltage
VILC
VSS
High-level Output Voltage
VOHC
0.8 x VDD —
Low-level Output Voltage
VOLC
VSS
—
0.2 x VDD V
Input leakage current
ILI
VIN = VDD or VSS
–1.0
—
1.0
μA
*4
Output leakage current
ILO
VIN = VDD or VSS
–3.0
—
3.0
μA
*5
—
2.0
3.5
Liquid Crystal Driver ON
(Relative to VSS)
—
Operating Voltage (2)
Ta =
VOUTIN =
25°C
15.0 V
2.6
—
KΩ
RON
Resistance
(Relative VOUTIN = 8.0
To VSS) V
Internal Oscillator fOSC
Oscillator
SEGn
COMn *6
—
3.2
5.4
10.2
--
10.3
kHz
73.2
77
80.9
Hz
*7
Ta = 25°C
1/132 duty
Frequency Frame frequency fFRAME
31 PWM
Rating
Item
Input voltage
Symbol
VDD
Condition
Units Applicable Pin
(Relative To VSS)
Min.
Typ.
2.0
—
Max.
3.3(+10%
V
Internal Power
Range)
Supply Step-up output
VOUOUT
(Relative To VSS)
—
—
18
V
VOUOUT
VOUTIN
(Relative To VSS)
—
—
18
V
VOUTIN
voltage Circuit
Voltage regulator
Circuit Operating
Voltage
Ver 1.7
73/96
2006/08/15
ST7632
Dynamic Consumption Current : During Display, with the Internal Power Supply OFF Current consumed by total ICs when
an external power supply is used .
Rating
Test pattern
Symbol
Display Pattern
Condition
VDD = 2.8 V, 1/12 bias ,6x
ISS
SNOW (die)
Sleep In
ISS
V0 – VSS = 12.5 V
Ta = 25°C
Units
Notes
420
μA
*8
10
μA
die
Min.
Typ.
Max.
—
350
—
—
Notes to the DC characteristics
1. The maximum possible VLCD voltage that may be generated is dependent on voltage, temperature and (display) load,
Internal clock
2. Power-down mode. During power down all static currents are switched off.
3. If external VLCD, the display load current is not transmitted to IDD.
4. VLCD external voltage applied to VOUTIN pin; VOUTIN disconnected from VOUOUT
References for items mark with *
*1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden
fluctuations to the voltage while the MPU is being accessed.
*2 The A0, D0 to D5, D6 (SI), D7 (SCL), /RD (E), /WR ,/(R/W),CL, RESB ,and terminals.
*3 The D0 to D7 erminals.
*4 The A0,/RD (E), /WR ,/(R/W),/CS,RESB ,and terminals.
*5 Applies when the D0 to D5, D6 (SI), D7 (SCL) terminals are in a high impedance state.
*6 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the
various power supply terminals (V1, V2, V3, and V4). These are specified for the operating voltage range.
RON = 0.1 V /ΔI (Where ΔI is the current that flows when 0.1 V is applied while the power supply is ON.)
*7 The relationship between the oscillator frequency and the frame rate frequency.
*8,9 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on.
Ver 1.7
74/96
2006/08/15
ST7632
12. TIMING CHARACTERISTICS
System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
A0
tAW8
tAH8
/CS
tCYC8
tCCLR,tCCLW
WR,RD
tCCHR,tCCHW
tDS8
tDH8
D0 to D7
(Write)
tACC8
tOH8
D0 to D7
(Read)
Figure 39.
(VDD = 3.3V , Ta =-30°C ~85°C, die)
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
tAH8
30
—
tAW8
30
—
tCYC8
370
—
tCCLW
120
—
tCCHW
250
—
tCCLR
60
—
Enable H pulse width (READ)
tCCHR
140
WRITE Data setup time
tDS8
200
—
tDH8
30
—
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
WR
Enable H pulse width (WRITE)
Enable L pulse width (READ)
ns
RD
WRITE Address hold time
D0 to D7
READ access time
tACC8
CL = 100 pF
—
70
READ Output disable time
tOH8
CL = 100 pF
—
50
Ver 1.7
75/96
2006/08/15
ST7632
(VDD = 2.8 V , Ta =-30°C ~85°C, die )
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
tAH8
30
—
tAW8
30
—
tCYC8
470
—
tCCLW
200
—
tCCHW
280
—
tCCLR
80
—
Enable H pulse width (READ)
tCCHR
190
—
WRITE Data setup time
tDS8
280
—
tDH8
30
—
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
WR
Enable H pulse width (WRITE)
Enable L pulse width (READ)
RD
WRITE Address hold time
D0 to D7
READ access time
tACC8
CL = 100 pF
—
140
READ Output disable time
tOH8
CL = 100 pF
—
100
ns
(VDD = 2.0V , Ta =-30°C ~85°C, die )
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
tAH8
30
—
tAW8
30
—
tCYC8
880
—
tCCLW
340
—
tCCHW
540
—
tCCLR
170
—
Enable H pulse width (READ)
tCCHR
360
WRITE Data setup time
tDS8
420
—
tDH8
30
—
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
WR
Enable H pulse width (WRITE)
Enable L pulse width (READ)
ns
RD
WRITE Address hold time
D0 to D7
READ access time
tACC8
CL = 100 pF
—
240
READ Output disable time
tOH8
CL = 100 pF
—
200
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tCCLW and tCCLR are specified as the overlap between /CS being “L” and WR and RD being at the “L” level.
Ver 1.7
76/96
2006/08/15
ST7632
System Bus Read/Write Characteristics 1 (For the 6800 Series MPU)
A0
R/W
tAW6
tAH6
CS1
(CS2="1")
tCYC6
tEWLR,tEWLW
E
tEWHR,tEWHW
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
Figure 40.
(VDD = 3.3 V , Ta =-30°C ~85°C, die )
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
tAH6
30
—
tAW6
30
—
tCYC6
380
—
tEWLW
120
—
tEWHW
260
—
tEWLR
60
—
Enable H pulse width (READ)
tEWHR
130
WRITE Data setup time
tDS6
200
—
tDH6
30
—
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
WR
Enable H pulse width (WRITE)
Enable L pulse width (READ)
ns
RD
WRITE Address hold time
D0 to D7
READ access time
tACC6
CL = 100 pF
—
70
READ Output disable time
tOH6
CL = 100 pF
—
50
Ver 1.7
77/96
2006/08/15
ST7632
(VDD = 2.8V , Ta =-30°C ~85°C, die )
Rating
Item
Signal
Symbol
Condition
Min.
Max.
tAH6
30
—
tAW6
30
—
tCYC6
490
—
tEWLW
200
—
tEWHW
290
—
tEWLR
80
—
Enable H pulse width (READ)
tEWHR
190
—
WRITE Data setup time
tDS6
290
—
tDH6
40
—
Address hold time
A0
Address setup time
System cycle time
Enable L pulse width (WRITE)
WR
Enable H pulse width (WRITE)
Enable L pulse width (READ)
RD
WRITE Address hold time
D0 to D7
Units
ns
READ access time
tACC6
CL = 100 pF
—
140
READ Output disable time
tOH6
CL = 100 pF
—
100
(VDD =2.0V , Ta =-30°C ~85°C, die )
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
tAH6
30
—
tAW6
30
—
tCYC6
890
—
tEWLW
340
—
tEWHW
550
—
tEWLR
170
—
Enable H pulse width (READ)
tEWHR
360
—
WRITE Data setup time
tDS6
420
—
tDH6
30
—
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
WR
Enable H pulse width (WRITE)
Enable L pulse width (READ)
RD
WRITE Address hold time
D0 to D7
READ access time
tACC6
CL = 100 pF
—
240
READ Output disable time
tOH6
CL = 100 pF
—
200
ns
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tEWLW and tEWLR are specified as the overlap between /CS being “L” and E.
Ver 1.7
78/96
2006/08/15
ST7632
SERIAL INTERFACE(4-Line Interface)
tCCSS
tCSH
/CS1
(CS2="1")
tSAS
tSAH
A0
tSCYC
tSLW
SCL
tSHW
tf
tr
tSDS
tSDH
SI
Fig 41.
(VDD=3.3V, Ta =-30°C ~85°C, die)
Rating
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Symbol
Condition
Units
Min.
Max.
tSCYC
110
—
tSHW
60
—
tSLW
50
—
tSAS
30
—
tSAH
50
—
tSDS
30
—
tSDH
50
—
tCSS
30
—
tCSH
60
—
A0
Address hold time
Data setup time
SI
Data hold time
CS-SCL time
CSB
CS-SCL time
ns
(VDD=2.8V, Ta =-30°C ~85°C, die)
Rating
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Symbol
Condition
Units
Min.
Max.
tSCYC
130
—
tSHW
70
—
tSLW
50
—
tSAS
40
—
tSAH
60
—
tSDS
40
—
tSDH
50
—
tCSS
40
—
tCSH
90
—
A0
Address hold time
Data setup time
SI
Data hold time
CS-SCL time
CSB
CS-SCL time
Ver 1.7
79/96
ns
2006/08/15
ST7632
(VDD=2.0V, Ta =-30°C ~85°C, die)
Rating
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Symbol
Condition
Units
Min.
Max.
tSCYC
240
—
tSHW
140
—
tSLW
110
—
tSAS
60
—
tSAH
90
—
tSDS
60
—
tSDH
90
—
tCSS
60
—
tCSH
140
—
A0
Address hold time
Data setup time
SI
Data hold time
CS-SCL time
CSB
CS-SCL time
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
SERIAL INTERFACE(3-Line Interface)
tCCSS
tCSH
/CS1
(CS2="1")
tSCYC
tSLW
SCL
tSHW
tf
tr
tSDS
tSDH
SI
Fig 42.
(VDD=3.3V, Ta =-30°C ~85°C, die)
Rating
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Data setup time
Symbol
Condition
Units
Min.
Max.
tSCYC
110
—
tSHW
60
—
tSLW
50
—
tSDS
30
—
tSDH
50
—
tCSS
30
—
tCSH
60
—
SI
Data hold time
CS-SCL time
CSB
CS-SCL time
Ver 1.7
80/96
ns
2006/08/15
ST7632
(VDD=2.8V, Ta =-30°C ~85°C, die)
Rating
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Data setup time
Symbol
Condition
Units
Min.
Max.
tSCYC
120
—
tSHW
70
—
tSLW
50
—
tSDS
40
—
tSDH
50
—
tCSS
40
—
tCSH
90
—
SI
Data hold time
CS-SCL time
CSB
CS-SCL time
ns
(VDD=2.0V, Ta =-30°C ~85°C, die)
Rating
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Data setup time
Symbol
Condition
Units
Min.
Max.
tSCYC
260
—
tSHW
140
—
tSLW
120
—
tSDS
60
—
tSDH
90
—
tCSS
60
—
tCSH
120
—
SI
Data hold time
CS-SCL time
CSB
CS-SCL time
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
Ver 1.7
81/96
2006/08/15
ST7632
13. RESET TIMING
tRW
/RES
tR
Internal
status
During reset
Reset complete
Fig 43.
(VDD = 3.3V , Ta =-30°C ~85°C, die)
Rating
Item
Signal
Reset time
Reset “L” pulse width
RESB
Symbol
Condition
Units
Min.
Typ.
Max.
tR
—
—
1
us
tRW
1
—
—
us
(VDD = 2.8V , Ta =-30°C ~85°C, die )
Rating
Item
Signal
Reset time
Reset “L” pulse width
RESB
Symbol
Condition
Units
Min.
Typ.
Max.
tR
—
—
1.5
us
tRW
1.5
—
—
us
(VDD = 2.0V , Ta =-30°C ~85°C, die )
Rating
Item
Signal
Reset time
Reset “L” pulse width
Ver 1.7
RESB
Symbol
Condition
Units
Min.
Typ.
Max.
tR
—
—
2.0
us
tRW
2.0
—
—
us
82/96
2006/08/15
ST7632
The pinning of the ST7632 is optimized for single plane wiring e.g. for chip-on-glass display modules. Display size:
Display 132 X 132 pixels
Display 128 X 128 pixels
COM
COM
VDD: VDD, VDD1
VSS1
VSS2
VSS4
*6 if external oscillator
VDD2
VDD
ST7632
VDD
VSS
VLCDOUT
VLCDIN
V0OUT
V0IN
SEG
5
CLVCD
VDD2: VDD2, VDD3,
VDD4, VDD5
I/O
CVDD
Fig 44. Application diagram: internal charge pump is used and s single VDD
Display 132 X 132 pixels
Display 128 X 128 pixels
COM
ST7632
VDD2
VDD
*6 if external oscillator
VDD: VDD, VDD1
VDD2: VDD2, VDD3,
VDD4, VDD5
COM
VSS1
VSS2
VSS4
VLCDOUT
VLCDIN
V0OUT
V0IN
SEG
5
VDD1 CVDD1
CLVCD
I/O VDD2
CVDD2 VSS
Fig 45. Application diagram: Internal charge pump is used and two
separate VDD1(VDD2)
Ver 1.7
83/96
2006/08/15
ST7632
Display 132 X 132 pixels
Display 128 X 128 pixels
SEG
ST7632
VDD2
VDD
*6 if external oscillator
VDD: VDD, VDD1
VDD2: VDD2, VDD3,
VDD4, VDD5
COM
VSS1
VSS2
VSS4
VLCDOUT
VLCDIN
V0OUT
V0IN
COM
5
VL2
I/O VDD2
CVDD VSS
Fig 46. application diagram : External high voltage generation is used
The requiblue minimum value for the external capacitors in an application with the ST7632 are:
CVLCD = min. 3.3uF CVDD1,2= min. 1.0 μF
Higher capacitor values are recommended for ripple.
Ver 1.7
84/96
2006/08/15
ST7632
14. THE MPU INTERFACE (REFERENCE EXAMPLES)
The ST7632 Series can be connected to either 8080 Series MPUs or to 6800 Series MPUs. Moreover, using the serial
interface it is possible to operate the ST7632 series chips with fewer signal lines.
The display area can be enlarged by using multiple ST7632 Series chips. When this is done, the chip select signal can be
used to select the individual Ics to access.
(1) 8080 Series MPUs
VDD
VCC
VDD
A0
A0
MPU
ST7632
CS1
CS1
D0 to D7
E (/RD)
R/W (/WR)
/RES
DO to D7
RD
WR
RES
GND
IF1
IF2
IF3
VSS
RESET
VSS
(2) 6800 Series MPUs
V DD
V DD
A0
A0
CS1
CS1
DO to D 7
RD
WR
RES
GND
IF1
IF2
IF3
ST7632
MPU
VCC
D 0 to D7
/RD (E)
/W R (R/W )
/RES
V SS
RESET
V SS
(3) Using the Serial Interface (4-line interface)
VDD
V CC
V DD
A0
CS1
CS1
IF1
IF2
IF3
Port 1
Port 2
RE S
GND
ST7632
MPU
A0
SI
SCL
/RE S
V SS
RESET
V SS
Ver 1.7
85/96
2006/08/15
ST7632
(4) Using the Serial Interface (3-line interface)
V DD or V SS
V CC
V DD
IF1
IF2
IF3
CS1
Port 1
Port 2
RES
GND
ST7632
MPU
CS1
SI
SCL
/RES
V SS
RESET
V SS
Ver 1.7
86/96
2006/08/15
1.5M
Ver 1.7
C3
C4
C5
C6
C8
C7
Vss
87/96
Note :
6800--16 bit interface
IF1: IF2: IF3 = 1 : 0: 0
CLS='1',using internal colock
Vdd operation voltage range 2.0V to 3.6V
Vdd2 operation voltage range 2.4 V to 3.3 V
Vop=12~14V
C3~C7=1uF~3.3uF
C8,C9=0.1uF~1uF
2006/08/15
/CS
C9
1.5M
VDD2
COM72
COM71
COM70
COM69
COM68
COM67
COM66
SEG0
SEG1
SEG2
SEG3
COM37
COM36
COM35
COM34
COM33
COM32
SEG392
SEG393
SEG394
SEG395
COM65
COM64
COM63
COM62
SEG383
ST7632
E
/RST
D8
D9
D10
D11
D12
D13
D14
D15
D0
D1
D2
D3
D4
D5
D6
D7
A0
RW
VDD
V0IN
V0OUT
V1
V2
V3
V4
VREF
VSS
VSS1
VDD1
VDD
CL
CLS
VSS
VDD
A0
RW_WR
VSS
VDD
D0
D1
D2
D3
D4
D5
D6
D7
VSS
VDD
D8
D9
D10
D11
D12
D13
D14
D15
VSS
VDD
E_RD
RST
VSS
VDD
I F1
I F2
I F3
CSEL
VSS
VDD
SI
SCL
/CS
VDD
VDD1
VSS1
VSS
VSS2
VSS4
VDD4
VDD3
VDD2
VDD5
TCAP
VOUTin
VOUTout
COM129
COM130
COM131
VSS
497~502
503~508
509
510
511
512
513
514~519
520,521
522,523
524~529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571~576
577,578
579,580
581~586
587~598
599,600
601,602
603,604
605~614
615~618
619
620~625
626~631
494
495
496
COM100
COM101
COM102
V1
V2
V3
V4
V0
465
466
467
COM99
COM98
COM97
6
5
4
3
2
1
38
37
36
35
34
33
32
31
47
437
436
435
434
433
432
431
430
429
428
427
464
463
462
ST7632
Application circuit :
(A) 6800-16 bit interface (V0 and VLCD –internal )
C?
C1
2.2uF
COM31
COM29
COM28
663
662
661
COM2
COM1
COM0
634
633
632
C2
2.2uF
Ver 1.7
Vss
C3
C4
C5
C6
C8
C7
88/96
Note :
6800--8 bit interface
IF1: IF2: IF3 = 0 : 1: 1
CLS='1',using internal colock
Vdd operation voltage range 2.0V to 3.6V
Vdd2 operation voltage range 2.4 V to 3.3 V
Vop=12~14V
C3~C7=1uF~3.3uF
C8,C9=0.1uF~1uF
2006/08/15
C9
1.5M
VDD2
V0IN
V0OUT
V1
V2
V3
V4
VREF
VSS
VSS1
VDD1
VDD
CL
CLS
VSS
VDD
A0
RW_WR
VSS
VDD
D0
D1
D2
D3
D4
D5
D6
D7
VSS
VDD
D8
D9
D10
D11
D12
D13
D14
D15
VSS
VDD
E_RD
RST
VSS
VDD
I F1
I F2
I F3
CSEL
VSS
VDD
SI
SCL
/CS
VDD
VDD1
VSS1
VSS
VSS2
VSS4
VDD4
VDD3
VDD2
VDD5
TCAP
VOUTin
VOUTout
COM72
COM71
COM70
COM69
COM68
COM67
COM66
SEG0
SEG1
SEG2
SEG3
COM37
COM36
COM35
COM34
COM33
COM32
SEG392
SEG393
SEG394
SEG395
COM65
COM64
COM63
COM62
SEG383
ST7632
/CS
E
/RST
D0
D1
D2
D3
D4
D5
D6
D7
A0
RW
VDD
VSS
497~502
503~508
509
510
511
512
513
514~519
520,521
522,523
524~529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571~576
577,578
579,580
581~586
587~598
599,600
601,602
603,604
605~614
615~618
619
620~625
626~631
COM129
COM130
COM131
V1
V2
V3
V4
V0
494
495
496
COM100
COM101
COM102
1.5M
465
466
467
COM99
COM98
COM97
6
5
4
3
2
1
38
37
36
35
34
33
32
31
47
437
436
435
434
433
432
431
430
429
428
427
464
463
462
ST7632
(B) 6800-8 bit interface (V0 and VLCD –internal )
C?
C1
2.2uF
COM31
COM29
COM28
663
662
661
COM2
COM1
COM0
634
633
632
C2
2.2uF
1.5M
Ver 1.7
C3
C4
C5
C6
Vss
C3~C7=1uF~3.3uF
C8,C9=0.1uF~1uF
89/96
C8
2006/08/15
/CS
C9
1.5M
VDD2
COM72
COM71
COM70
COM69
COM68
COM67
COM66
SEG0
SEG1
SEG2
SEG3
COM37
COM36
COM35
COM34
COM33
COM32
SEG392
SEG393
SEG394
SEG395
COM65
COM64
COM63
COM62
SEG383
ST7632
/RD
/RST
D8
D9
D10
D11
D12
D13
D14
D15
D0
D1
D2
D3
D4
D5
D6
D7
A0
/WR
V0IN
V0OUT
V1
V2
V3
V4
VREF
VSS
VSS1
VDD1
VDD
CL
CLS
VSS
VDD
A0
RW_WR
VSS
VDD
D0
D1
D2
D3
D4
D5
D6
D7
VSS
VDD
D8
D9
D10
D11
D12
D13
D14
D15
VSS
VDD
E_RD
RST
VSS
VDD
IF1
IF2
IF3
CSEL
VSS
VDD
SI
SCL
/CS
VDD
VDD1
VSS1
VSS
VSS2
VSS4
VDD4
VDD3
VDD2
VDD5
TCAP
VOUTin
VOUTout
COM129
COM130
COM131
VDD
497~502
503~508
509
510
511
512
513
514~519
520,521
522,523
524~529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571~576
577,578
579,580
581~586
587~598
599,600
601,602
603,604
605~614
615~618
619
620~625
626~631
494
495
496
COM100
COM101
COM102
VSS
V0
V1
V2
V3
V4
465
466
467
COM99
COM98
COM97
6
5
4
3
2
1
38
37
36
35
34
33
32
31
47
437
436
435
434
433
432
431
430
429
428
427
464
463
462
ST7632
(C) 8080-16 bit interface (V0 and VLCD –internal )
C?
C1
2.2uF
COM31
COM29
COM28
663
662
661
COM2
COM1
COM0
634
633
632
C2
2.2uF
C7
Note :
8080--16 bit interface
IF1: IF2: IF3 = 1 : 1: 1
CLS='1',using inte rnal colock
Vdd operation voltage range 2.0V to 3.6V
Vdd2 ope ration voltage range 2.4 V to 3.3 V
Vop=12~14V
Title
Ver 1.7
Vss
C3
C4
C5
C6
C3~C7=1uF~3.3uF
C8,C9=0.1uF~1uF
90/96
C8
2006/08/15
C9
1.5M
VDD2
V0IN
V0OUT
V1
V2
V3
V4
VREF
VSS
VSS1
VDD1
VDD
CL
CLS
VSS
VDD
A0
RW_WR
VSS
VDD
D0
D1
D2
D3
D4
D5
D6
D7
VSS
VDD
D8
D9
D10
D11
D12
D13
D14
D15
VSS
VDD
E_RD
RST
VSS
VDD
IF1
IF2
IF3
CSEL
VSS
VDD
SI
SCL
/CS
VDD
VDD1
VSS1
VSS
VSS2
VSS4
VDD4
VDD3
VDD2
VDD5
TCAP
VOUTin
VOUTout
COM72
COM71
COM70
COM69
COM68
COM67
COM66
SEG0
SEG1
SEG2
SEG3
COM37
COM36
COM35
COM34
COM33
COM32
SEG392
SEG393
SEG394
SEG395
COM65
COM64
COM63
COM62
SEG383
ST7632
/CS
/RD
/RST
D0
D1
D2
D3
D4
D5
D6
D7
A0
/WR
VDD
497~502
503~508
509
510
511
512
513
514~519
520,521
522,523
524~529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571~576
577,578
579,580
581~586
587~598
599,600
601,602
603,604
605~614
615~618
619
620~625
626~631
COM129
COM130
COM131
VSS
V0
V1
V2
V3
V4
494
495
496
COM100
COM101
COM102
1.5M
465
466
467
COM99
COM98
COM97
6
5
4
3
2
1
38
37
36
35
34
33
32
31
47
437
436
435
434
433
432
431
430
429
428
427
464
463
462
ST7632
(D) 8080-8 bit interface (V0 and VLCD –internal )
C?
C1
2.2uF
COM31
COM29
COM28
663
662
661
COM2
COM1
COM0
634
633
632
C2
2.2uF
C7
Note :
8080--8 bit interface
IF1: IF2: IF3 = 1 : 1: 0
CLS='1',using inte rnal colock
Vdd operation voltage range 2.0V to 3.6V
Vdd2 operation voltage range 2.4 V to 3.3 V
Vop=12~14V
Title
1.5M
Ver 1.7
C3
C4
C5
C6
Vss
C3~C7=1uF~3.3uF
C8,C9=0.1uF~1uF
91/96
C8
C7
Note :
4 Lines (8 bits) interface
IF1: IF2: IF3 = 0 : 0: 0
CLS='1',using inte rnal colock
Vdd operation voltage range 2.0V to 3.6V
Vdd2 ope ration voltage range 2.4 V to 3.3 V
Vop=12~14V
2006/08/15
C9
1.5M
VDD2
COM72
COM71
COM70
COM69
COM68
COM67
COM66
SEG0
SEG1
SEG2
SEG3
COM37
COM36
COM35
COM34
COM33
COM32
SEG392
SEG393
SEG394
SEG395
COM65
COM64
COM63
COM62
SEG383
ST7632
SI
SCL
/CS
/RST
A0
V0IN
V0OUT
V1
V2
V3
V4
VREF
VSS
VSS1
VDD1
VDD
CL
CLS
VSS
VDD
A0
RW_WR
VSS
VDD
D0
D1
D2
D3
D4
D5
D6
D7
VSS
VDD
D8
D9
D10
D11
D12
D13
D14
D15
VSS
VDD
E_RD
RST
VSS
VDD
IF1
IF2
IF3
CSEL
VSS
VDD
SI
SCL
/CS
VDD
VDD1
VSS1
VSS
VSS2
VSS4
VDD4
VDD3
VDD2
VDD5
TCAP
VOUTin
VOUTout
COM129
COM130
COM131
VDD
497~502
503~508
509
510
511
512
513
514~519
520,521
522,523
524~529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571~576
577,578
579,580
581~586
587~598
599,600
601,602
603,604
605~614
615~618
619
620~625
626~631
494
495
496
COM100
COM101
COM102
VSS
V0
V1
V2
V3
V4
465
466
467
COM99
COM98
COM97
6
5
4
3
2
1
38
37
36
35
34
33
32
31
47
437
436
435
434
433
432
431
430
429
428
427
464
463
462
ST7632
(E) 4 Lines (8 bits) interface (V0 and VLCD –internal )
C?
C1
2.2uF
COM31
COM29
COM28
663
662
661
COM2
COM1
COM0
634
633
632
C2
2.2uF
1.5M
Ver 1.7
C3
C4
C5
C6
C8
C7
Vss
C3~C9=1uF~3.3uF
C8,C9=0.1uF~1uF
Note :
3 Lines (9 bits) interface
IF1: IF2: IF3 = 0 : 0: 1
CLS='1',using inte rnal colock
Vdd operation voltage range 2.0V to 3.6V
Vdd2 ope ration voltage range 2.4 V to 3.3 V
Vop=12~14V
92/96
2006/08/15
SI
SCL
/CS
/RST
C9
1.5M
VDD2
V0IN
V0OUT
V1
V2
V3
V4
VREF
VSS
VSS1
VDD1
VDD
CL
CLS
VSS
VDD
A0
RW_WR
VSS
VDD
D0
D1
D2
D3
D4
D5
D6
D7
VSS
VDD
D8
D9
D10
D11
D12
D13
D14
D15
VSS
VDD
E_RD
RST
VSS
VDD
I F1
I F2
I F3
CSEL
VSS
VDD
SI
SCL
/CS
VDD
VDD1
VSS1
VSS
VSS2
VSS4
VDD4
VDD3
VDD2
VDD5
TCAP
VOUTin
VOUTout
COM129
COM130
COM131
VDD
497~502
503~508
509
510
511
512
513
514~519
520,521
522,523
524~529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571~576
577,578
579,580
581~586
587~598
599,600
601,602
603,604
605~614
615~618
619
620~625
626~631
494
495
496
COM100
COM101
COM102
VSS
V0
V1
V2
V3
V4
465
466
467
COM37
COM36
COM35
COM34
COM33
COM32
SEG392
SEG393
SEG394
SEG395
COM65
COM64
COM63
COM62
SEG383
COM72
COM71
COM70
COM69
COM68
COM67
COM66
SEG0
SEG1
SEG2
SEG3
COM99
COM98
COM97
6
5
4
3
2
1
38
37
36
35
34
33
32
31
47
437
436
435
434
433
432
431
430
429
428
427
464
463
462
ST7632
(F) 3 Lines (9 bits) interface (V0 and VLCD –internal )
U1
ST7632
C1
2.2uF
COM31
COM29
COM28
COM2
COM1
COM0
C2
2.2uF
663
662
661
634
633
632
ST7632
(G) Example 132X132 :
Duty=1/132 Vop=12~14V Bias=1/12 bias
COM0
COM1
COM2
COM3
COM4
COM5
COM66
COM67
COM68
(P12,P11,P10)=(0,0,1)
Ver 1.7
6
5
4
3
2
1
COM37
COM36
COM35
COM34
COM33
COM32
631
VLCDOUT
38
37
36
35
34
33
32
SEG392
SEG393
SEG394
SEG395
COM65
COM64
COM63
434
433
432
431
430
429
428
427
V0IN
ST7632 (CSEL=0)
497
COM129
COM130
COM131
S?
COM69
COM68
COM67
COM66
SEG0
SEG1
SEG2
SEG3
464
463
462
494
495
496
COM100
COM101
COM102
COM64
COM65
COM130
COM131
COM99
COM98
COM97
465
466
467
132X132
93/96
2006/08/15
COM31
COM29
COM28
COM2
COM1
COM0
663
662
661
634
633
632
ST7632
(H) Example 128X128 :
Duty=1/128 Vop=12~14V Bias=1/12 bias
COM0
COM1
COM2
COM3
COM4
COM5
COM66
COM67
COM68
(P12,P11,P10)=(0,0,1)
128X128
COM64
COM65
Ver 1.7
6
5
4
3
2
1
COM37
COM36
COM35
COM34
COM33
COM32
VLCDOUT
40
39
38
37
36
35
34
33
32
SEG390
SEG391
SEG392
SEG393
SEG394
SEG395
COM65
COM64
COM63
436
435
434
433
432
431
430
429
428
427
COM71
COM70
COM69
COM68
COM67
COM66
SEG0
SEG1
SEG2
SEG3
ST7632 (CSEL=0)
631
COM129
COM130
COM131
S?
497
494
495
496
COM100
COM101
COM102
V0IN
465
466
467
COM99
COM98
COM97
464
463
462
seg0
seg0
seg0
COM127
COM128
94/96
2006/08/15
COM31
COM29
COM28
COM2
COM1
COM0
663
662
661
634
633
632
ST7632
(I)128X96
Duty=1/132 Vop=12~14V Bias=1/12 bias
Display window set: start page=16，end page=111
COM48
COM49
COM50
COM94
COM95
COM94
COM95
128X96
COM0
COM1
COM46
COM47
COM46
COM47
6
5
4
3
2
1
COM37
COM36
COM35
COM34
COM33
COM32
631
ST7632 (CSEL=0)
VLCDOUT
40
39
38
37
36
35
34
33
32
SEG390
SEG391
SEG392
SEG393
SEG394
SEG395
COM65
COM64
COM63
448
447
436
435
434
433
432
431
430
429
428
427
COM71
COM70
COM69
COM68
COM67
COM66
SEG0
SEG1
SEG2
SEG3
V0IN
COM129
COM130
COM131
S?
497
494
495
496
COM100
COM101
COM102
COM83
COM82
465
466
467
COM99
COM98
COM97
464
463
462
seg0
seg0
seg0
(P12,P11,P10)=(0,0,1)
COM48
COM49
COM0
COM1
COM2
COM3
COM4
COM5
NOTE: Microprocessor interface pins should not be floating in any operation mode.
Ver 1.7
95/96
2006/08/15
COM31
COM29
COM28
COM17
COM16
COM0
663
662
661
649
648
632
ST7632
ST7632 Serial Specification Revision History
Ver 1.7
Version
Date
Description
1.0
2004/8/31
Remove preliminary
1.1
2004/10/11
Correct errors in writting words & Modify Timing Characteristic
1.2
2004/12/07
Addition V3&V4 must <Vdd (p1), p48,p49 graphic diagram, and
analog set flow p70,modify timing character
1.3
2005/02/01 Modify p75 LIMITING VALUES
1.4
2005/5/20
1.5
2005/09/15 Addition DC/AC application range
1.6
2006/7/31
Modify Application Circuit P87~P92
1.7
2006/8/15
Add microprocessor notice item(p.16, p.95).
Remove the IIC Interface
96/96
2006/08/15