SITRONIX ST7920

ST
Sitronix
ST7920
Chinese Fonts built in LCD controller/driver
Main Features
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Operation Voltage Range:
Ø
2.7V to 5.5V
Support 8-bit, 4-bit and serial bus MPU interface
64 x 16-bit display RAM (DDRAM)
Ø
Supports 16 words x 4 lines (Max)
Ø
LCD display range 16 words x 2 lines
64 x 256-bit Graphic Display RAM (GDRAM)
2M-bits Character Generation ROM (CGROM):
Support 8192 Chinese words (16x16 dot matrix)
16K-bit half-width Character Generation ROM
(HCGROM):
Supports 126 characters (16x8 dot matrix)
32-common x 64-segment (2 lines of character)
LCD drivers
Automatic power on reset (POR)
External reset pin (XRESET)
With the extension segment drivers, the display
area can up to 16x2 lines
Built-in RC oscillator:
Frequency is adjusted by an external resistor
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Low power consumption design
Ø
Normal mode (450uA Typ VDD=5V)
Ø
Standby mode (30uA Max VDD=5V)
VLCD (V0 to VSS): max 7V
Graphic and character mixed display mode
Multiple instructions:
Ø
Display Clear
Ø
Return Home
Ø
Display ON/OFF
Ø
Cursor ON/OFF
Ø
Display Character Blink
Ø
Cursor Shift
Ø
Display Shift
Ø
Vertical Line Scroll
Ø
Reverse Display (by line)
Ø
Standby Mode
Built-in voltage booster (2 times)
VOUT: max 7V
1/33 Duty (with ICON)
Function Description
ST7920 LCD controller/driver IC can display alphabets, numbers, Chinese fonts and self-defined characters. It
supports 3 kinds of bus interface, namely 8-bit, 4-bit and serial. All functions, including display RAM, Character
Generation ROM, LCD display drivers and control circuits are all in a one-chip solution. With a minimum system
configuration, a Chinese character display system can be easily achieved.
ST7920 includes character ROM with 8192 16x16 dots Chinese fonts and 126 16x8 dots half-width alphanumerical
fonts. Besides, it supports 64x256 dots graphic display area for graphic display (GDRAM). Mix-mode display with
both character and graphic data is possible. ST7920 has built-in CGRAM and provide 4 sets software programmable
16x16 fonts.
ST7920 has wide operating voltage range (2.7V to 5.5V). It also has low power consumption. So ST7920 is suitable
for battery-powered portable device.
ST7920 LCD driver consists of 32-common and 64-segment. Company with the extension segment driver (ST7921)
ST7920 can support up to 32-common x 256-segment display.
V4.0
Part Number
Font Code
ST7920-0A
ST7920-0B
ST7920-0C
ST7920-0F
BIG-5 Code Set (Traditional Chinese)
GB Code Set (Simplified Chinese)
Chinese (Traditional/Simplified) & Japanese
Chinese (Traditional/Simplified), Japanese & Korean
1/49
2008/08/18
ST7920
ST7920 Specification Reversion History
Version
V4.0
Date
Description
1.
2.
3.
4.
1.
2.
3.
4.
5.
6.
1.
2.
3.
4.
5.
VCC changed to VDD.
VLCD changed from VCC-V5 to V0-VSS.
DC characteristics input High voltage (Vih) changed to 0.7VDD.
DC characteristics output High voltage (Voh) changed to 0.8VDD.
Chip Size changed.
ICON 256 dots changed to 240 dots.
XOFF normal high sleep Low changed to normal low sleep High.
Added XOFF application.
Modified application of ST7920: PIN 4~6 are floating. (PIN 4~6 are test pin)
Modified voltage doubler CAP1P, CAP1M, CAP2M capacitors polarity
Icon RAM TABLE changed. (TABLE-6)
Booster description modified. (PAGE-29)
AC Characteristics modified.
Added 2Line 16 Chinese Word (32Com X 256Seg) application circuit.
Added oscillation resistor’s relation to power consumption and frequency.
C1.7
2000/12/15
C1.8
2001/03/01
C1.9
2001/05/28
C2.0
2001/07/03
1. Added Register initial values.
2. Voltage booster CAP1M CAP1P polarity changed (PAGE-30).
V2.0
2001/08/17
1. Modified Table 7 (PAGE-14).
2. Change to English version.
V2.0c
2001/10/18
1. Modified page-38 Serial interface timing diagram.
V2.0d
2002/05/09
1. Add the standard code (Japan, GB code, BIG-5 code).
V3.0
2002/10/11
1. Delete sleep mode function.
V3.1
2003/04/11
1. Modified GDRAM Address (AC5…AC0, 00h…3Fh).
V3.2
2003/09/09
1. Add the CGROM and HCGROM test application circuit.
V3.3
2004/03/29
1. Updat the using method for ICON.
V3.4
2005/5/24
1. ICON no used.
V3.5
2005/5/24
V3.6
2005/6/6
V3.7
V3.8
V3.9
2007/7/24
2007/12/20
2008/3/3
V4.0
2008/8/18
1. Add VOUT voltage limitation.
2. Remove IRAM related descriptions.
1. Fix the check sum count number on Page 28~30.
655360->655362, 10240->10242.
2. Modify the description about serial interface.
1. Add CGROM/HCGROM checksum operation time.
1. Add “Clear DDRAM” step before check sum process.
1. Modify 4-bit initial sequence.
1. Add Font Code “0F” at Page 1.
2. Modify the description of Font Code Table at Page 1.
2/49
2008/08/18
ST7920
System Block Diagram
RESI
Reset
Circuit
RESO
CLK
CL1
CL2
M
Timing
Generator
PSB
DOUT
Instruction
Register (IR)
RS
MPU
Interface
RW
E
Instruction
Decoder
Input/
Output
Buffer
33/49-bit
shift
register
COM1 to
Common COM32
Signal
Driver
SEG1 to
SEG64
64-bit
shift
register
Address
Counter
DB4 to
DB7
DB0 to
DB3
Display
Data RAM
(DDRAM)
64 x 16 bits
64-bit
latch
circuit
Data
Register
(DR)
Segment
Signal
Driver
LCD Drive
Voltage
Selector
Busy
Flag
Graphic
RAM
(GDRAM)
1024 x 16
bits
Vss
Half size
Character
ROM
(HCGROM)
1024x16 bits
Character
Generator
RAM
(CGRAM)
1024 bits
Character
Generator
ROM
(CGROM)
2M bits
Cursor
Blink
Scroll
Controller
Parallel/Serial converter
and
Attribute Circuit
VDD
XOFF
XRESET
V0
V4.0
V1
3/49
V2
V3
V4
2008/08/18
ST7920
Pad Diagram
30
1
“ST7920
ST7920
31
136
(0,0)
99
1
68
98
69
Origin: center of chip
Chip size: 5305 X 4074
Pad pitch: 125
Coordinates: from pad center
Pad open: 90 X 90
unit: μm
* Chip substrate must connect to VSS
V4.0
4/49
2008/08/18
ST7920
PAD Coordinates
V4.0
(Unit: um)
No.
Name
X
Y
No.
Name
X
Y
1
V0
-2548
1812
39
VD2
-1306
-1933
2
V1
-2548
1688
40
C[1]
-1181
-1933
3
V2
-2548
1562
41
C[2]
-1056
-1933
4
CLK
-2548
1438
42
C[3]
-931
-1933
5
TT1
-2548
1312
43
C[4]
-806
-1933
6
TT2
-2548
1188
44
C[5]
-681
-1933
7
V3
-2548
1062
45
C[6]
-556
-1933
8
V4
-2548
938
46
C[7]
-431
-1933
9
VSS
-2548
812
47
C[8]
-306
-1933
10
VDD
-2548
688
48
C[9]
-181
-1933
11
XRESET
-2548
562
49
C[10]
-56
-1933
12
CL1
-2548
438
50
C[11]
69
-1933
13
CL2
-2548
312
51
C[12]
194
-1933
14
VDD
-2548
188
52
C[13]
319
-1933
15
M
-2548
62
53
C[14]
444
-1933
16
DOUT
-2548
-62
54
C[15]
569
-1933
17
RS
-2548
-188
55
C[16]
694
-1933
18
RW
-2548
-312
56
C[17]
819
-1933
19
E
-2548
-438
57
C[18]
944
-1933
20
VSS
-2548
-562
58
C[19]
1069
-1933
21
OSC1
-2548
-688
59
C[20]
1194
-1933
22
OSC2
-2548
-812
60
C[21]
1319
-1933
23
PSB
-2548
-938
61
C[22]
1444
-1933
24
D0
-2548
-1062
62
C[23]
1569
-1933
25
D1
-2548
-1188
63
C[24]
1694
-1933
26
D2
-2548
-1312
64
C[25]
1819
-1933
27
D3
-2548
-1438
65
C[26]
1944
-1933
28
D4
-2548
-1562
66
C[27]
2069
-1933
29
D5
-2548
-1688
67
C[28]
2194
-1933
30
D6
-2548
-1812
31
D7
-2306
-1933
68
C[29]
2319
-1933
32
XOFF
-2181
-1933
69
C[30]
2548
-1812
33
VOUT
-2056
-1933
70
C[31]
2548
-1688
34
CAP3M
-1931
-1933
71
C[32]
2548
-1562
35
CAP1P
-1806
-1933
72
C[33]
Not use
2548
-1438
36
CAP1M
-1681
-1933
73
S[64]
2548
-1312
37
CAP2P
-1556
-1933
74
S[63]
2548
-1188
38
CAP2M
-1431
-1933
75
S[62]
2548
-1062
76
S[61]
2548
-938
5/49
2008/08/18
ST7920
V4.0
No.
Name
X
Y
No.
Name
X
Y
77
S[60]
2548
-812
116
S[21]
194
1933
78
S[59]
2548
-688
117
S[20]
69
1933
79
S[58]
2548
-562
118
S[19]
-56
1933
80
S[57]
2548
-438
119
S[18]
-181
1933
81
S[56]
2548
-312
120
S[17]
-306
1933
82
S[55]
2548
-188
121
S[16]
-431
1933
83
S[54]
2548
-62
122
S[15]
-556
1933
84
S[53]
2548
62
123
S[14]
-681
1933
85
S[52]
2548
188
124
S[13]
-806
1933
86
S[51]
2548
312
125
S[12]
-931
1933
87
S[50]
2548
438
126
S[11]
-1056
1933
88
S[49]
2548
562
127
S[10]
-1181
1933
89
S[48]
2548
688
128
S[9]
-1306
1933
90
S[47]
2548
812
129
S[8]
-1431
1933
91
S[46]
2548
938
130
S[7]
-1556
1933
92
S[45]
2548
1062
131
S[6]
-1681
1933
93
S[44]
2548
1188
132
S[5]
-1806
1933
94
S[43]
2548
1312
133
S[4]
-1931
1933
95
S[42]
2548
1438
134
S[3]
-2056
1933
96
S[41]
2548
1562
135
S[2]
-2181
1933
97
S[40]
2548
1688
136
S[1]
-2306
1933
98
S[39]
2548
1812
99
S[38]
2319
1933
100
S[37]
2194
1933
101
S[36]
2069
1933
102
S[35]
1944
1933
103
S[34]
1819
1933
104
S[33]
1694
1933
105
S[32]
1569
1933
106
S[31]
1444
1933
107
S[30]
1319
1933
108
S[29]
1194
1933
109
S[28]
1069
1933
110
S[27]
944
1933
111
S[26]
819
1933
112
S[25]
694
1933
113
S[24]
569
1933
114
S[23]
444
1933
115
S[22]
319
1933
6/49
2008/08/18
ST7920
Pin Description
Name
No.
I/O
Connects to
Function
XRESET
11
I
―
PSB
23
I
―
RS(CS*)
17
I
MPU
RW(SID*)
18
I
MPU
E(SCLK*)
19
I
MPU
D4 to D7
28~31
I/O
MPU
D0 to D3
24~27
I/O
MPU
CL1
12
O
Extension segment drv.
CL2
13
O
Extension segment drv.
M
15
O
Extension segment drv.
DOUT
16
O
Extension segment drv.
System reset input (low active).
Interface selection:
0: serial mode;
1: 8/4-bit parallel bus mode.
Parallel Mode: Register select.
0: Select instruction register (write)
or busy flag, address counter (read);
1: Select data register (write/read).
Serial mode: Chip select.
1: chip enabled;
0: chip disabled.
When chip is disabled, SID and SCLK
should be set as “H” or “L”. Transcient
of SID and SCLK is not allowed.
Parallel Mode: Read/Write control.
0: Write;
1: Read.
Serial Mode: Sserial data input.
Parallel Mode: 1: Enable trigger.
Serial Mode: Serial clock.
Higher nibble data bus of 8-bit interface
and data bus for 4-bit interface
Lower nibble data bus of 8-bit interface.
Latch signal for extension segment
drivers.
Shift clock for extension segment
drivers.
AC signal for extension segment drivers
voltage inversion.
Data output for extension segment
drivers.
40~71
O
LCD
Common signals.
136~73
O
LCD
Segment signals.
COM1 to
COM32
SEG1 to
SEG64
LCD bias voltage.
V0 ~ V4 ≦ 7V.
VDD
10,14
I
Power
VDD : 2.7V to 5.5V.
Vss
9,20
I
Power
VSS: 0V.
Using internal oscillator:
5.0V R=33K;
OSC1,
21,22
I, O
Resistors
2.7V R=18K.
OSC2
Using external clock:
Use OSC1 as external clock input.
LCD voltage doubler output.
VOUT
33
O
Resistors
VOUT ≦ 7V.
*Note: The OSC pin must have the shortest wiring pattern of all other pins. To prevent noise from other
signal lines, it should also be enclosed by the largest GND pattern. Poor anti-noise characteristics on the
OSC line will result in malfunction, or adversely affect the clock’s duty ratio.
V0 to V4
V4.0
1~3,7,8
―
―
7/49
2008/08/18
ST7920
Pin Description (continued)
Name
No.
CAP3M
CAP1P
CAP1M
CAP2M
XOFF
CAP2P
C[33]
34
35
36
38
32
37
72
I/O
Connects to
I/O
Capacitors
O
―
O
―
―
―
VD2
39
I
Reference voltage
CLK
TT1
TT2
4
5
6
I
―
―
―
Description
Capacitor pins for voltage doubler
Voltage ≦ 7V.
Reserved (no connection).
Reserved (no connection).
Reserved (no connection).
Voltage doubler reference voltage.
If use internal voltage doubler, please
make sure that:
l VD2 ≦ 3.5V or
l VOUT ≦ 7V and CAP3M ≦ 7V.
For CGROM/HCGROM checksum.
Refer to checksum application.
Note:
1.
7V>=VOUT>=V0>=V1>=V2>=V3>=V4 must be maintained
2.
Two clock options: As shown below.
OSC1
OSC2
R
OSC1
OSC2
Clock input
R=33K (VDD=5.0V)
R=18K (VDD=2.7V)
External Resistor vs. Current
(VDD=5V)
800
900
700
800
700
Frequency(KHz)
600
Iss (uA)
500
400
300
200
100
600
500
400
300
200
100
0
0
5
3.
External Resistor vs. Frequency
(VDD=5V)
15
25
40
60
Resistor(K)
80
5
100
15
25
40
60
80
100
Resistor(K)
When using voltage doubler (VOUT), it is recommended that the sum of those divide resistors (R1~R5) should be larger than 20K Ohm.
So that the voltage doubler can provide sufficient power.
V4.0
8/49
2008/08/18
ST7920
Voltage Doubler
Voltage Doubler
Reference Voltage
Vss
VD2
CAP1M
CAP1P
CAP2M
CAP2P
CAP3M
VOUT
VOUT
VOUT vs. VD2
10
9
Do not operate in this area.
8
VOUT (V)
7
6
5
4
3
2
1
0
5
4.8 4.6 4.4 4.2
4
3.8 3.6 3.4 3.2
3
2.8 2.6 2.4 2.2
2
1.8
VD2 (V)
Voltage Doubler mode: VD2 & Vout output characteristic
Notes:
l
Total resistance of the Follower deviding resistors should larger than 20K Ohm.
l
Booster Capacitor uses 4.7uF
l
Panel size: 80mm x 28mm (check display)
V4.0
9/49
2008/08/18
ST7920
Function Description
System interface
ST7920 supports 3 kinds of bus interface to communicate with MPU: 8-bit parallel, 4-bit parallel and clock
synchronized serial interface. Parallel interface is selected by PSB=”1” and serial interface is by PSB=”0”. 8-bit / 4-bit
interface is selected by function set instruction DL bit.
Two 8-bit registers (Data Register DR and Instruction Register IR) are used in ST7920 to access DRAM or Register.
Data Register (DR) can access DDRAM, CGRAM and GDRAM through the address pointer implemented by Address
Counter (AC). Instruction Register (IR) stores the instruction sent by MPU to ST7920.
4 kinds of parallel interface access mode can be selected through RS and RW:
RS
RW
Description
L
L
MPU write instruction to instruction register (IR)
L
H
MPU read busy flag (BF) and address counter (AC)
H
L
MPU write data to data register (DR)
H
H
MPU read data from data register (DR)
* The serial interface access modes do not have Read operation.
Busy Flag (BF)
ST7920 needs a process time for any received instruction. Before finishing the received instruction, any further
instruction is not accepted. The process time of each instruction is not equal and the internal process is finished or
not can be determined by the BF. Internal operation is in progress while BF=”1”, that means ST7920 is in busy state.
No further instructions will be accepted until BF=”0”. MPU must check BF to determine whether the internal operation
is finished or not before issuing instruction.
Address Counter (AC)
Address Counter (AC) is used as the address pointer of DDRAM, CGRAM and GDRAM. (AC) can be set by
instruction. After that, accesses (Read/Write operations) to the memories, such as DDRAM, CGRAM or GDRAM,
(AC) will be increased or decreased by 1 (according to the setting in “Entry Mode Set” Register). When RS=”0”,
RW=”1” and E=”1” the value of (AC) will be output to DB6~DB0.
Character Generation ROM (CGROM) and Half-width Character Generation ROM (HCGROM)
ST7920 is built in a Character Generation ROM (CGROM) to provide 8192 16x16 character fonts and a Half-width
Character Generation ROM to provide 126 8x16 alphanumeric characters. It is easy to support multi-language
applications such as Chinese and English. Two consecutive bytes are used to specify one 16x16 character or two
8x16 half-width characters. Character codes are written into DDRAM and the corresponding fonts are mapped from
CGROM or HCGROM to the display drivers.
Character Generation RAM (CGRAM)
ST7920 is built in a Character Generation RAM (CGRAM) to support user-defined fonts. Four sets of 16x16
bit-maped RAM spaces are available. These user-defined fonts are displayed the same ways as CGROM fonts by
writing the related character code into the DDRAM.
V4.0
10/49
2008/08/18
ST7920
Display Data RAM (DDRAM)
There are 64x2 bytes RAM spaces for the Display Data RAM. It can store display data such as 16 characters (16x16)
by 4 lines or 32 characters (8x16) by 4 lines. However, only 2 character-lines (maximum 32 common outputs) can be
displayed at one time. Character codes stored in DDRAM will refer to the fonts specified by CGROM, HCGROM and
CGRAM.
ST7920 can display half-width HCGROM fonts, user-defined CGRAM fonts and full 16x16 CGROM fonts. The
character codes in 0000H~0006H will use user-defined fonts in CGRAM. The character codes in 02H~7FH will use
half-width alpha numeric fonts. The character code larger than A1H will be treated as 16x16 fonts and will be
combined with the next byte automatically. The 16x16 BIG5 fonts are stored in A140H~D75FH while the 16x16 GB
fonts are stored in A1A0H~F7FFH. In short:
1. To display HCGROM fonts:
Write 2 bytes of data into DDRAM to display two 8x16 fonts. Each byte represents 1 character.
The data is among 02H~7FH.
2. To display CGRAM fonts:
Write 2 bytes of data into DDRAM to display one 16x16 font.
Only 0000H, 0002H, 0004H and 0006H are acceptable.
3. To display CGROM fonts:
Write 2 bytes of data into DDRAM to display one 16x16 font.
A140H~D75FH are BIG5 code, A1A0H~F7FFH are GB code.
The higher byte (D15~D8) is written first and the lower byte (D7~D0) is the next.
Please refer to Table 5 for the relationship between DDRAM and the address/data of CGRAM.
CGRAM fonts and CGROM fonts can only be displayed in the start position of each address. (Refer toTable 4)
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
80
H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L
S i t r o n i x
S T 7 9 2 0
矽
創
電
子
中
文
編
碼
正
確
(
. .
)
矽
創
電
子
中
文
編
碼
. . .
Table 4
Incorrect start position
V4.0
11/49
2008/08/18
ST7920
Graphic RAM (GDRAM)
Graphic Display RAM has 64x256 bits bit-mapped memory space. GDRAM address is set by writing 2 consecutive
bytes of vertical address and horizontal address. Two-byte data (16 bits) configures one GDRAM horizontal address.
The Address Counter (AC) will be increased by one automatically after receiving the 16-bit data for the next operation.
After the horizontal address reaching 0FH, the horizontal address will be set to 00H and the vertical address will not
change. The procedure is summarized below:
1. Set vertical address (Y) for GDRAM
2. Set horizontal address (X) for GDRAM
3. Write D15~D8 to GDRAM (first byte)
4. Write D7~D0 to GDRAM (second byte)
Please refer to Table 7 for Graphic Display RAM mapping.
LCD driver
ST7920 embedded LCD driver has 33 commons and 64 segments to drive the LCD panel. Segment data from
CGRAM, CGROM and HCGROM are shifted into the 64 bits segment latche to display. Extended segment driver
(ST7921) can be used to extend the segment outputs upto 256 segments.
V4.0
12/49
2008/08/18
ST7920
DDRAM data
CGRAM CGRAM data CGRAM data
(char. code)
Addr.
(higher byte) (lower byte)
B B B B B B B BB B DDDDDDDDDDDDDDDD
B15~ B4 3 2 1 0 5 4 3 2 1 0 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
543210
00000000010001100000
00011111111001000000
00100001000001000100
00110001000001111110
01000010010010000100
01010011110010000100
01100110010101001000
01111010011001001000
0
X 00 X 00
10000010010001010000
10010010010000010000
10100010010000100000
10110011110000100000
11000010010001000000
11010000000010000000
11100000000100000000
11110000000000000000
00000000110000000110
00010001101000000100
00100010000100110100
00110101110110100100
01001000000010100100
01010111111100100100
01100100000100100100
01110111111100100100
0
X 01 X 01
10000100000100100100
10010111111100100100
10100100000000100100
10110111111110 00100
11001010000010100100
11011011111110011100
11101010000010001000
11110000000000000000
Table 5: DDRAM data (character code) vs. CGRAM data/address map
Note:
1.
DDRAM data (character code) bit1 and bit2 are identical with CGRAM address bit4 and bit5.
2.
CGRAM address bit0 to bit3 specify total 16 rows. Row-16 is for cursor display. The data in Row-16 will be logically OR to the cursor.
3.
CGRAM data for each address is 16 bits.
4.
To select the CGRAM font, the bit4 through bit15 of DDRAM data must be “0” while bit0 and bit3 are “don’t care”.
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ST7920
Table 6
V4.0
16x8 half-width characters
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ST7920
GDRAM Horizontal address（ X）
0
GDRAM Vertical address
︵
Y
︶
Table 7
15
...........
...........
b15 b14 b13
V4.0
...........
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
...........
b0
GDRAM display coordinates and corresponding address
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ST7920
Instructions
ST7920 offers basic instruction set and extended instruction set:
Instruction Set 1: (RE=0: Basic Instruction)
Code
Inst.
Description
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Display
Clear
Return
Home
Entry Mode
Set
Display
Control
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
X
0
0
0
0
0
0
0
1
I/D
S
to "00H".
Set DDRAM address counter (AC) to "00H", and put cursor
to origin ；the content of DDRAM are not changed
Set cursor position and display shift when doing write or read
operation
(540KHZ)
1.6 ms
72 us
72 us
D=1: Display ON
0
0
0
0
0
0
1
D
C
B
C=1: Cursor ON
72 us
B=1: Character Blink ON
Cursor
Display
Fill DDRAM with "20H" and set DDRAM address counter (AC)
Exec time
0
0
0
0
0
1
S/C R/L
X
X
Control
Cursor position and display shift control; the content of
DDRAM are not changed
72 us
DL=1 8-bit interface
Function
Set
0
0
0
0
1
DL
X
0
RE
X
X
DL=0 4-bit interface
RE=1: extended instruction
72 us
RE=0: basic instruction
Set
CGRAM
Set CGRAM address to address counter (AC)
0
0
0
1
AC5 AC4 AC3 AC2 AC1 AC0 Make sure that in extended instruction SR=0 (scroll or
Set
DDRAM
1
0
0
0
0
1
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write RAM
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Read RAM
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Address.
AC6
AC5 AC4 AC3 AC2 AC1 AC0
Read
Busy Flag
(BF) & AC.
V4.0
72 us
RAM address select)
Address.
Set DDRAM address to address counter (AC)
AC6 is fixed to 0
Read busy flag (BF) for completion of internal operation, also
Read out the value of address counter (AC)
Write data to internal RAM
(DDRAM/CGRAM/GDRAM)
Read data from internal RAM
(DDRAM/CGRAM/GDRAM)
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72 us
0 us
72 us
72 us
2008/08/18
ST7920
Instruction set 2: (RE=1: extended instruction)
Code
Inst.
Description
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Standby
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
SR
Enter standby mode, any other instruction can terminate.
COM1…32 are halted.
Exec time
(540KHZ)
72 us
Scroll or
RAM
Address.
SR=1: enable vertical scroll position
SR=0: enable CGRAM address (basic instruction)
72 us
Select
Reverse
(by line)
Select 1 out of 4 line (in DDRAM) and decide whether to
0
0
0
0
0
0
0
1
R1
R0 reverse the display by toggling this instruction
72 us
R1,R0 initial value is 0,0
DL=1 :8-bit interface
DL=0 :4-bit interface
Extended
Function
0
0
0
0
1
DL
Set
X
1
RE
G
0
RE=1: extended instruction set
RE=0: basic instruction set
72 us
G=1 :graphic display ON
G=0 :graphic display OFF
Set Scroll
Address
0
0
0
1
AC5 AC4 AC3 AC2 AC1 AC0 SR=1: AC5~AC0 the address of vertical scroll
Set GDRAM address to address counter (AC)
Set Graphic
Display
RAM
72 us
0
0
1
0
0
0
0
AC3 AC2 AC1 AC0
AC5 AC4 AC3 AC2 AC1 AC0
Address
Set the vertical address first and followed the horizontal
address by consecutive writings
72 us
Vertical address range: AC5…AC0
Horizontal address range: AC3…AC0
Note:
1.
Make sure that ST7920 is not in busy state by reading the busy flag before sending instruction or data. If using delay loop instead, please
make sure the delay time is enough. Please refer to the instruction execution time.
2.
“RE” is the selection bit of basic and extended instruction set. After setting the RE bit, the value will be kept. So that the software doesn’t
have to set RE every time when using the same instruction set.
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ST7920
Initial Setting (Register flag) (RE=0: basic instruction)
Code
Inst.
Description
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Entry Mode
0
0
0
0
0
0
0
1
I/D
S
1
0
D
C
B
0
0
0
X
X
Cursor move to right ,DDRAM address counter (AC) plus 1
Set
Display
0
0
0
0
0
0
1
Display, cursor and blink are ALL OFF
Control
CURSOR
0
0
0
0
0
1
S/C R/L
No cursor or display shift operation
DISPLAY
X
SHIFT
FUNCTION
0
0
0
0
1
SET
DL
X
1
X
0
RE
X
X
8-bit MPU interface , basic instruction set
0
Initial Setting (Register flag) (RE=1: extended instruction set)
Code
Inst.
Description
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
SCROLL
0
0
0
0
0
0
0
0
1
SR
OR RAM
Allow vertical scroll or set CGRAM address
ADDR.
0
SELECT
0
0
0
0
0
0
0
1
R1
R0
0
0
G
0
REVERSE
EXTENDED
FUNCTION
SET
V4.0
Begin with normal and toggle to reverse
0
0
0
0
1
DL
X
1
RE
Graphic display OFF
0
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ST7920
Description of basic instruction set
l
Display Clear
RS
Code
l
0
0
0
0
0
0
0
0
0
1
This instruction will change the following items:
1. Fill DDRAM with "20H"(space code).
2. Set DDRAM address counter (AC) to"00H".
3. Set Entry Mode I/D bit to be "1". Cursor moves right and AC adds 1 after write or read operation.
Return Home
RS
Code
l
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
1
X
Set address counter (AC) to "00H". Cursor moves to origin. Then content of DDRAM is not changed.
Enry Mode Set
RS
Code
0
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
I/D
S
Set the cursor movement and display shift direction when doing write or read operation.
I/D: Address Counter Control: (Increase/Decrease)
When I/D = "1", cursor moves right, address counter (AC) is increased by 1.
When I/D = "0", cursor moves left, address counter (AC) is decreased by 1.
S: Display Shift Control: (Shift Left/Right)
S
I/D
DESCRIPTION
H
H
Entire display shift left by 1
H
L
Entire display shift right by 1
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ST7920
l
Display Control
RS
Code
0
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
1
D
C
B
Controls display, cursor and blink ON/OFF.
D: Display ON/OFF control bit
When D = "1", display ON
When D = "0", display OFF, the content of DDRAM is not changed
C: Cursor ON/OFF control bit
When C = "1", cursor ON.
When C = "0", cursor OFF.
B: Character Blink ON/OFF control bit
When B = "1", cursor position blink ON. Then display data (character) in cursor position will blink.
When B = "0", cursor position blink OFF
l
Cursor/Display Shift Control
RS
Code
0
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
S/C R/L
X
X
This instruction configures the cursor moving direction or the display shifting direction. The content of DDRAM is
not changed.
S/C
R/L
Description
AC Value
L
L
Cursor moves left by 1 position
AC=AC-1
L
H
Cursor moves right by 1 position
AC=AC+1
H
L
Display shift left by 1, cursor also follows to shift.
AC=AC
H
H
Display shift right by 1, cursor also follows to shift.
AC=AC
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ST7920
l
Function Set
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RS
Code
0
0
0
0
1
DL
X
RE
X
X
DL: 4/8-bit interface control bit
When DL = "1", 8-bit MPU bus interface
When DL = "0", 4-bit MPU bus interface
RE: extended instruction set control bit
When RE = "1", extended instruction set
When RE = "0", basic instruction set
In same instruction cannot alter DL and RE at once. Make sure that change DL first then RE.
l
Set CGRAM Address
RS
RW
0
0
DB7
DB6
0
1
DB5
DB4
DB3
DB2
DB1
DB0
AC5 AC4 AC3 AC2 AC1 AC0
Code
Set CGRAM address into address counter (AC)
AC range is 00H…3FH
Make sure that in extended instruction SR=0 (scroll address or RAM address select)
l
Set DDRAM Address
RS
RW
0
0
DB7
1
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Code
Set DDRAM address into address counter (AC).
First line AC range is 80H…8FH
Second line AC range is 90H…9FH
Third line AC range is A0H…AFH
Fourth line AC range is B0H…BFH
Please note that only 2 lines can be display with one ST7920.
l
Read Busy Flag (BF) and Address
RS
RW
DB7
0
1
BF
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Code
Read busy flag (BF) can check whether the internal operation is finished or not. At the same time, the value of
address counter (AC) is also read. When BF = “1”, further instruction(s) will not be accepted until BF = “0”.
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ST7920
l
Write Data to RAM
RS
Code
1
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
D7 D6 D5 D4 D3 D2 D1 D0
Write data to the internal RAM and increase/decrease the (AC) by 1
Each RAM address (CGRAM, DDRAM and GDRAM…) must write 2 consecutive bytes for 16-bit data. After
receiving the second byte, the address counter will increase or decrease by 1 according to the entry mode set
control bit.
l
Read RAM Data
RS
Code
1
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
D7 D6 D5 D4 D3 D2 D1 D0
Read data from the internal RAM and increase/decrease the (AC) by 1
After the operation mode changed to Read (CGRAM, DDRAM and GDRAM…), a “Dummy Read” is required.
There is no need to add a “Dummy Read” for the following bytes unless a new address set instruction is issued.
V4.0
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ST7920
Description of extended instruction set
l
Standby
RS
0
Code
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
1
This Instruction will set ST7920 entering the standby mode. Any other instruction follows this instruction will
terminate the standby mode.
The content of DDRAM remains the same.
l
Vertical Scroll or RAM Address Select
RS
0
Code
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
1
SR
When SR = "1", the Vertical Scroll mode is enabled.
When SR = "0", “Set CGRAM Address” instruction (basic instruction) is enabled.
l
Reverse
RS
0
Code
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
R1 R0
Select 1 out of 4 lines to reverse the display and to toggle the reverse condition by repeating this instruction.
R1, R0 initial vale is 00. The first time issuing this instruction, the display will be reversed while the second time
will return the display become normal.
R1
L
R0
L
Description
First line normal or reverse
L
H
Second line normal or reverse
H
L
Third line normal or reverse
H
H
Fourth line normal or reverse
Please note that only 2 lines out of 4 lines of display data can be displayed with one ST7920.
V4.0
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ST7920
l
Extended Function Set
RS
Code
0
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
DL
X
RE
G
X
DL: 4/8-bit interface control bit
When DL = "1", 8-bit MPU interface.
When DL = "0", 4-bit MPU interface.
RE: extended instruction set control bit
When RE = "1", extended instruction set
When RE = "0", basic instruction set
G: Graphic display control bit
When G = "1", Graphic Display ON
When G = "0", Graphic Display OFF
In same instruction cannot alter DL, RE and G at once. Make sure that change DL or G first and then RE.
l
Set Scroll Address
RS
RW
0
0
DB7
0
DB6
1
DB5
DB4
DB3
DB2
DB1
DB0
AC5 AC4 AC3 AC2 AC1 AC0
Code
SR=1: AC5~AC0 is vertical scroll displacement address
l
Set Graphic RAM Address
RS
RW
0
0
RS
RW
0
0
DB7
1
DB6
0
DB5
DB4
DB3
DB2
DB1
DB0
AC5 AC4 AC3 AC2 AC1 AC0
Code
DB7
1
DB6
0
DB5
0
DB4
0
DB3
DB2
DB1
DB0
AC3 AC2 AC1 AC0
Code
Set GDRAM address into address counter (AC). This is a 2-byte instruction.
The first instruction sets the vertical address while the second one sets the horizontal address (write 2
consecutive bytes to complete the vertical and horizontal address setting).
Vertical address range is AC5...AC0
Horizontal address range is AC3…AC0
The address counter (AC) of graphic RAM (GRAM) will be increased automatically after the vertical and
horizontal addresses are set. After horizontal address is increased upto 0FH, it will automatically return to 00H.
However, the vertical address will not increase as the result of the same action.
V4.0
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ST7920
Parallel interface:
ST7920 is in parallel mode by pulling up PSB pin. ST7920 can select 8-bit or 4-bit bus interface by setting the DL
control bit in “Function Set” instruction. MPU can control RS, RW, E and DB0…DB7 pins to complete the data
transmission.
In 4-bit transfer mode, every 8-bit data or instruction is separated into 2 parts. The higher 4 bits (bit-7~bit-4) data will
be transfered first through data pins (DB7~DB4). The lower 4 bits (bit-3~bit-0) data will be transfered second through
data pins (DB7~DB4). The (DB3~DB0) data pins are not used during 4-bit transfer mode.
RS
RW
E
DB0-DB7
Instruction write
Dummy read RAM read
Timing Diagram of 8-bit Parallel Bus Mode Data Transfer
RS
RW
E
DB0-DB7
Upper
Lower
Upper
Lower
Upper
Lower
4-bit
4-bit
4-bit
4-bit
4-bit
4-bit
Instruction write
Dummy read
RAM read
Timing Diagram of 4-bit Parallel Bus Mode Data Transfer
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ST7920
Serial interface:
ST7920 is in serial interface mode when pulling down PSB pin. Two pins (SCLK and SID) are used to complete the
data transfer. Only write data is available in the serial interface mode.
When chip select (CS) is low, ST7920 serial clock counter and serial data will be reset. Serial transfer counter is set
to the first bit and data register is cleared. After CS is “L”, any further change on SID or SCLK is not allowed. It is
recommended to keep SCLK at “L” and SID at the last status before set CS to “L”. For a minimal system with only
one ST7920 and one MPU, only SCLK and SID pins are necessary. CS pin should pull to high.
ST7920’s serial clock (SCLK) is asynchronous to the internal clock and is generated by MPU. When multiple
instruction/data is transferred, the instruction execution time must be considered. MPU must wait till the previous
instruction is finished and then send the next instruction. ST7920 has no internal instruction buffer area.
When starting a transmission, a start byte is required. It consists of 5 consecutive “1” (sync character). Serial transfer
counter will be reset and synchronized. Followed by 2-bit flag that indicates: read/write (RW) and register/data
selected (RS) operation. Last 4 bits are filled by “0”.
After receiving the sync character, RW and RS bits, every 8 bits instruction/data will be separated into 2 groups.
Higher 4 bits (DB7~DB4) will be placed in the first section followed by 4 “0”s. And lower 4 bits (DB3~DB0) will be
placed in the second section followed by 4 “0”s.
CS
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1
1
1
1
1 RW RS 0 D7 D6 D5 D4 0
SCLK
SID
Synchronizing
Bit string
Higher
data
0
0
0 D3 D2 D1 D0 0
0
0
0
Lower
data
1st byte
2nd byte
Timing Diagram of Serial Mode Data Transfer
V4.0
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ST7920
8051 demo program for serial interface
;-------------------------------------------------------------; Write data from A into INSTRUCTION Register
;-------------------------------------------------------------WRINS:
SETB
CS
SETB
SID
; SID = 1
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
CLR
SID
; SID = 0
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
MOVBIT SID, A.7 ; SID = A.7
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
MOVBIT SID, A.6 ; SID = A.6
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
MOVBIT SID, A.5 ; SID = A.5
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
MOVBIT SID, A.4 ; SID = A.4
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
CLR
SID
; SID = 0
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
MOVBIT SID, A.3 ; SID = A.3
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
MOVBIT SID, A.2 ; SID = A.2
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
MOVBIT SID, A.1 ; SID = A.1
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
MOVBIT SID, A.0 ; SID = A.0
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
CLR
SID
; SID = 0
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
CLR
CS
CALL
DLY8
RET
V4.0
;------------------------------------------------; Write data from A into DATA Register
;------------------------------------------------WRDATA:
SETB
CS
SETB
SID
; SID = 1
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
CLR
SID
; SID = 0
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SID
; SID = 1
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
CLR
SID
; SID = 0
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
MOVBIT SID, A.7 ; SID = A.7
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
MOVBIT SID, A.6 ; SID = A.6
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
MOVBIT SID, A.5 ; SID = A.5
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
MOVBIT SID, A.4 ; SID = A.4
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
CLR
SID
; SID = 0
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
MOVBIT SID, A.3 ; SID = A.3
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
MOVBIT SID, A.2 ; SID = A.2
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
MOVBIT SID, A.1 ; SID = A.1
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
MOVBIT SID, A.0 ; SID = A.0
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
CLR
SID
; SID = 0
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
SETB
SCLK
; READ DATA FROM SID
CLR
SCLK
CLR
CS
CALL
DLY8
RET
27/49
2008/08/18
ST7920
Application circuit for testing CGROM and HCGROM:
We can use the function of “CHECK SUM” to check the CGROM is right or error.
See the following notes: Useing IC Pad (Pin4àCLK, Pin5àTT1, Pin6àTT2) to do the “CHECK SUM” function.
The application circuit is at Page49.
Timing Diagram for checking CGROM (TT1=0, TT2=1)
The ST7920 check sum process: (DDRAM must be cleared by 0x00 before this process)
In the first place: Resetting the internal counter (set TT1 and TT2 to Height)
In the second place: Setting CGROM mode (set TT1 to Low, TT2 to Height).
In the third place: CLK starts to count 655362 times.
In the final place: Finishing the counting, read the last four bytes to CHECK SUM (reading only when the CLK is
Height).
ST7920 check sum circuit: Data is available when CLK is height; if CLK is low then the data is always FFH. The last
four bytes are Y0, Y1, Y2, and Y3.
The fatest execution time is: tCYC=1us (1MHz at 5V).
The table below is a comparing table of CGROM for different versions.
Version
(Font)
V4.0
CGROM Last four bytes
Y0
Y1
Y2
Y3
1
Big5 (0A)
38
88
CC
F1
2
GB (0B)
9D
81
79
29
3
0C
FD
6F
B5
85
28/49
2008/08/18
ST7920
Timing Diagram for checking HCGROM (TT1=1, TT2=0)
The ST7920 check sum process: (DDRAM must be cleared by 0x00 before this process)
In the first place: Resetting the internal counter (set TT1 and TT2 to Height)
In the second place: Setting CGROM mode (set TT1 to Height, TT2 to Low).
In the third place: CLK starts to count 10242 times.
In the final place: Finishing the counting, read the last four bytes to CHECK SUM (reading only when the CLK is
Height).
ST7920 check sum circuit: Data is available when CLK is height; if CLK is low then the data is always FFH. The last
four bytes are Y0, Y1, Y2, and Y3.
The fatest execution time is: tCYC=2us (0.5MHz at 5V).
The table below is a comparing table of HCGROM for different versions.
Version
(Font)
V4.0
HCGROM last four bytes
Y0
Y1
Y2
Y3
1
Big5 (0A)
B5
11
B5
11
2
GB (0B)
B5
11
B5
11
3
0C
B5
11
B5
11
29/49
2008/08/18
ST7920
Testing Step:
1. Clear whole DDRAM area by writing data 0x00.
2. Composing TT1 and TT2 to make the ‘Reset’ action, and clear the internal counter.
3. Selecting the test mode by setting TT1 and TT2 (CGROM or HCGROM).
4. After setp1 and setp2, entering some impulse signals through Pin4 (CLK).
5. Reading the CHECK SUM data through D0 to D7.
6. Comparing CHECK SUM with the Code Table (upper table) to check if the data is correct or not.
TT1
TT2
No. of counts
Status
1
1
--
RESET
0
1
655362
CGROM
1
0
10242
HGROM
Test process flow:
V4.0
30/49
2008/08/18
ST7920
8051 CGROM、HCGROM illustrative test program
CLK
TT1
TT2
TT3
TT4
TT5
STACK
FUNC
RESET:
CGROM:
CN4:
CN3:
CN2:
CN5:
CN6:
V4.0
;*******************************;
;*
CHECK_ROM
*;
;*******************************;
;*******************************;
;*
Definition of outside Pin *;
;*******************************;
REG
P3.5
;
REG
P3.0
;
REG
P3.1
;
REG
P3.2
;CHECK CGROM FLAG
REG
P3.3
;CHECK HCGROM FLAG
REG
P3.4
;ERROR FLAG
;*******************************;
;* Definition of internal RAM *;
;*******************************;
EQU
6FH
;
EQU
20H
;
;*******************************;
;
Interrupt set
*;
;*******************************;
ORG
00H
;
AJMP
RESET
;
;*******************************;
;*
PROGRAM START
*;
;*******************************;
MOV
SP,#STACK
;
MOV
P1,#FFH
;
MOV
P3,#FFH
;
;*******************************;
;*
CHECK_CGROM
*;
;*******************************;
;*******************************;
;*
Initial DDRAM
*;
;*******************************;
CALL
WR0x00
;Write 0x00 to whole DDRAM
;*******************************;
;*
Initial setting
*;
;*******************************;
SETB
TT1
;
SETB
TT2
;TT1,TT2 SET HIGH (RESET)
CALL
DELAY_100US
;Wait Reset 100us
CLR
TT1
;TT1=LOW TT2=HIGH ( CHECK CGROM)
SETB
CLK
;
CALL
DELAY_100US
;
;*******************************;
;*
start counter
*;
;*******************************;
MOV
R3,#9
;
MOV
R2,#0
;<---MOV
R1,#0
;
|
CLR
CLK
;
|
SETB
CLK
;
|
DJNZ
R1,CN2
;
|
DJNZ
R2,CN3
;
|
DJNZ
R3,CN4
;
|
;
|
MOV
R3,#0
;
|
MOV
R2,#255
;
|
CLR
CLK
;
|
SETB
CLK
;
|
DJNZ
R2,CN6
;
|
DJNZ
R3,CN5
;
|
;
|
31/49
2008/08/18
ST7920
CN7:
CN8:
CN9:
MOV
R3,#63
;
|
MOV
R2,#2
;
|
MOV
R1,#2
;
|
CLR
CLK
;
|
SETB
CLK
;
|
DJNZ
R1,CN9
;
|
DJNZ
R2,CN8
;
|
DJNZ
R3,CN7
;
|
CLR
CLK
;
|
SETB
CLK
;
|
CLR
CLK
;
|
SETB
CLK
;<---- Counter 655356
;-------------------------------;
CLR
CLK
;Counter 655357
SETB
CLK
;
MOV
A,P1
;A=Y0
CJNE
A,#FDH,ERRORC
;COMPARE Y0 DATA
CLR
CLK
;Counter 655358
SETB
CLK
;
MOV
A,P1
;A=Y1
CJNE
A,#6FH,ERRORC
;COMPARE Y1 DATA
CLR
CLK
;Counter 655359
SETB
CLK
;
MOV
A,P1
;A=Y2
CJNE
A,#B5H,ERRORC
;COMPARE Y2 DATA
CLR
SETB
MOV
CJNE
CLR
CLR
CALL
;Counter 655360
;
;A=Y3
;COMPARE Y3 DATA
;
;IF OK CLR TT3
;
ERRORC:
;
CLR
TT5
;IF CGROM CHECK ERROR CLR TT5
;---------------------------------------;
;*******************************;
;*
CHECK_HCGROM
*;
;*******************************;
;*******************************;
;*
Initial setting
*;
;*******************************;
HCGROM: SETB
TT1
;
SETB
TT2
;TT1,TT2 SET HIGH (RESET)
CALL
DELAY_100US
;Wait Reset 100us
CLR
TT2
;TT2=LOW TT1=HIGH ( CHECK HCGROM)
SETB
CLK
;
CALL
DELAY_100US
;
;*******************************;
;*
start counter
*;
;*******************************;
MOV
R3,#9
;
N4:
MOV
R2,#32
;<---N3:
MOV
R1,#32
;
|
N2:
CLR
CLK
;
|
SETB
CLK
;
|
DJNZ
R1,N2
;
|
DJNZ
R2,N3
;
|
DJNZ
R3,N4
;
|
;
|
MOV
R3,#32
;
|
N5:
MOV
R2,#31
;
|
N6:
CLR
CLK
;
|
SETB
CLK
;
|
DJNZ
R2,N6
;
|
DJNZ
R3,N5
;
|
;
|
MOV
R2,#30
;
|
V4.0
CLK
CLK
A,P1
A,#85H,ERRORC
CLK
TT3
HCGROM
32/49
2008/08/18
ST7920
N7:
CLR
CLK
;
|
SETB
CLK
;
|
DJNZ
R2,N7
;
|
;---------------------------------------;<---- Counter 10236
CLR
CLK
;Counter 10237
SETB
CLK
;
MOV
A,P1
;A=Y0
CJNE
A,#B5H,ERROR
;COMPARE Y0 DATA
CLR
CLK
;Counter 10238
SETB
CLK
;
MOV
A,P1
;A=Y1
CJNE
A,#11H,ERROR
;COMPARE Y1 DATA
CLR
CLK
;Counter 10239
SETB
CLK
;
MOV
A,P1
;A=Y2
CJNE
A,#B5H,ERROR
;COMPARE Y2 DATA
CLR
CLK
;Counter 10240
SETB
CLK
;
MOV
A,P1
;A=Y3
CJNE
A,#11H,ERROR
;COMPARE Y3 DATA
CLR
CLK
;
CLR
TT4
;IF HCGROM CHECK OK THEN CLR TT4
AJMP
$
;
ERROR:
;
CLR
TT5
;IF HCGROM CHECK ERROR THEN CLR TT5
AJMP
$
;
;*******************************;
;*
DELAY TIME 100US
*;
;*******************************;
DELAY_100US
;
DEL_10 MOV
R6,#5
;
DEL_9
MOV
R7,#3
;
DJNZ
R7,$
;
DJNZ
R6,DEL_9
;
RET
;
END
;
V4.0
33/49
2008/08/18
ST7920
8-bit interface:
POWER ON
Wait time >40ms
XRESET
LOW
HIGH
Function set
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
X
0
X
X
Wait time >100uS
Function set
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
X
0
X
X
Wait time >37uS
Display ON/OFF control
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
D
C
B
Wait time >100uS
Display clear
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
1
Wait time >10mS
Entry mode set
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
1
I/D
S
Initialization end
V4.0
34/49
2008/08/18
ST7920
4-bit interface:
POWER ON
Wait time > 40mS
(for VDD stable)
XRESET: LOW
HIGH
Function set
RS
0
0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
0
X
X
X
X
0
X
0
X
X
X
X
X
X
Wait time > 100μS
Function set
RS
0
0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
0
X
X
X
X
0
X
0
X
X
X
X
X
X
Wait time > 100μS
Display ON/OFF Control
RS
0
0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
X
X
X
X
0
1
D
C
B
X
X
X
X
Wait time > 100μS
Display Clear
RS
0
0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
X
X
X
X
0
0
0
0
1
X
X
X
X
Wait time > 10mS
Entry Mode Set
RS
0
0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
X
X
X
X
0
0
1
I/D
S
X
X
X
X
INITIALIZATION END
V4.0
35/49
2008/08/18
ST7920
Built in voltage booster
Voltage Doubler
Reference Voltage
VOUT
Vss
VD2
CAP1M
Voltage Doubler
Reference Voltage
CAP1P
VD2
CAP2M
CAP2P
CAP3M
VOUT
VSS
VOUT
External reset timing
VDD
Tres
XRESET
Trw
XRESET pulse width
RESET start time
V4.0
Trw
Tres
36/49
10us
50ns
2008/08/18
ST7920
LCD driving wave form (1/33 duty, 1/5 bias )
When oscillation frequency is 540KHZ, 1 clock cycle time = 1.85us
1 frame = 1.85us x 300 x 33 = 18315us=18.3ms
300 clocks
1
2
3
4
33
1
2
3
4
33
1
2
3
4
33
V0
V1
V2
COM1
V3
V4
VSS
V0
V1
V2
COM2
V3
V4
VSS
V0
V1
V2
COM33
SEGx
off
SEGx
on
V4.0
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
1 frame
37/49
2008/08/18
ST7920
Absolute Maximum Ratings
Characteristics
Power Supply Voltage
LCD Driver Voltage
Voltage Doubler Output
Input Voltage
Operating Temperature
Storage Temperature
Symbol
VDD
VLCD or V0
VOUT
VIN
TA
TSTO
Value
-0.3V to +6.0V
-0.3V to +7.0V
-0.3V to +7.0V
-0.3V to VDD+0.3V
-30℃ to + 85℃
-65℃ to + 150℃
DC Characteristics (TA = -30℃ ~ 85℃, VDD = 2.7 V - 4.5 V)
Symbol
Characteristics
VDD
VLCD
Operating Voltage
LCD Voltage
ICC
VIH1
VIL1
VIH2
VIL2
VOH1
VOL1
VOH2
VOL2
ILEAK
IPUP
V4.0
Test Condition
V0-VSS
fOSC = 530KHz, VDD=3.0V
Power Supply Current
Rf=18KΩ
Input High Voltage
(Except OSC1)
Input Low Voltage
(Except OSC1)
Input High Voltage
(OSC1)
Input Low Voltage
(OSC1)
Output High Voltage
IOH = -0.1mA
(DB0 - DB7)
Output Low Voltage
IOL = 0.1mA
(DB0 - DB7)
Output High Voltage
IOH = -0.04mA
(Except DB0 - DB7)
Output Low Voltage
IOL = 0.04mA
(Except DB0 - DB7)
Input Leakage
VIN = 0V to VDD
Current
Pull Up MOS Current
VDD = 3V
38/49
Min.
Typ.
Max.
Unit
2.7
3.0
-
5.5
7
V
V
-
0.20
0.45
mA
0.7VDD
-
VDD
V
- 0.3
-
0.6
V
VDD – 1
-
VDD
V
-
-
1.0
V
0.8VDD
-
VDD
V
-
-
0.1
V
0.8VDD
-
VDD
V
-
-
0.1VDD
V
-1
-
1
µA
22
27
32
µA
2008/08/18
ST7920
DC Characteristics (TA = -30℃ ~ 85℃, VDD = 4.5 V - 5.5 V)
Symbol
Characteristics
VDD
VLCD
Operating Voltage
LCD Voltage
ICC
VIH1
VIL1
VIH2
VIL2
VOH1
VOL1
VOH2
VOL2
ILEAK
IPUP
V4.0
Test Condition
Min.
4.5
V0-VSS
3.0
fOSC = 540KHz, VDD=5V
Power Supply Current
Rf=33KΩ
Input High Voltage
0.7VDD
(Except OSC1)
Input Low Voltage
-0.3
(Except OSC1)
Input High Voltage
VDD-1
(OSC1)
Input Low Voltage
(OSC1)
Output High Voltage
IOH = -0.1mA
0.8VDD
(DB0 - DB7)
Output Low Voltage
IOL = 0.1mA
(DB0 - DB7)
Output High Voltage
IOH = -0.04mA
0.8VDD
(Except DB0 - DB7)
Output Low Voltage
IOL = 0.04mA
(Except DB0 - DB7)
Input Leakage
VIN = 0V to VDD
-1
Current
Pull Up MOS Current
VDD = 5V
75
39/49
Typ.
Max.
Unit
-
5.5
7
V
V
0.45
0.75
mA
-
VDD
V
-
0.6
V
-
VDD
V
-
1.0
V
-
VDD
V
-
0.4
V
-
VDD
V
-
0.1VDD
V
-
1
µA
80
85
µA
2008/08/18
ST7920
AC Characteristics (TA = -30℃ ~ 85℃, VDD = 4.5V) Parallel Mode Interface
Symbol
fOSC
fEX
TR,TF
TC
TPW
TR,TF
TAS
TAH
TDSW
TH
TC
TPW
TR,TF
TAS
TAH
TDDR
TH
TCWH
TCWL
TCST
TSU
TDH
TDM
V4.0
Characteristics
Test Condition
Min.
Typ.
Internal Clock Operation
R = 33KΩ
OSC Frequency
480
540
External Clock Operation
External Frequency
480
540
Duty Cycle
45
50
Rise/Fall Time
Write Mode (Writing data from MPU to ST7920)
Enable Cycle Time
Pin E
1200
Enable Pulse Width
Pin E
140
Enable Rise/Fall Time
Pin E
Address Setup Time
Pins: RS,RW,E
10
Address Hold Time
Pins: RS,RW,E
20
Data Setup Time
Pins: DB0 - DB7
40
Data Hold Time
Pins: DB0 - DB7
20
Read Mode (Reading Data from ST7920 to MPU)
Enable Cycle Time
Pin E
1200
Enable Pulse Width
Pin E
140
Enable Rise/Fall Time
Pin E
Address Setup Time
Pins: RS,RW,E
10
Address Hold Time
Pins: RS,RW,E
20
Data Delay Time
Pins: DB0 - DB7
Data Hold Time
Pins: DB0 - DB7
20
Interface Mode with LCD Driver(ST7921)
Clock Pulse with High
Pins: CL1, CL2
800
Clock Pulse with Low
Pins: CL1, CL2
800
Clock Setup Time
Pins: CL1, CL2
500
Data Setup Time
Pin: D
300
Data Hold Time
Pin: D
300
M Delay Time
Pin: M
-1000
-
40/49
Max.
Unit
600
KHz
600
55
0.2
KHz
%
µs
25
-
ns
ns
ns
ns
ns
ns
ns
25
100
-
ns
ns
ns
ns
ns
ns
ns
1000
ns
ns
ns
ns
ns
ns
2008/08/18
ST7920
AC Characteristics (TA = -30℃ ~ 85℃, VDD = 2.7V) Parallel Mode Interface
Symbol
fOSC
fEX
TR,TF
TC
TPW
TR,TF
TAS
TAH
TDSW
TH
TC
TPW
TR,TF
TAS
TAH
TDDR
TH
TCWH
TCWL
TCST
TSU
TDH
TDM
V4.0
Characteristics
Test Condition
Min.
Typ.
Internal Clock Operation
R = 18KΩ
OSC Frequency
470
530
External Clock Operation
External Frequency
470
530
Duty Cycle
45
50
Rise/Fall Time
Write Mode (Writing data from MPU to ST7920)
Enable Cycle Time
Pin E
1800
Enable Pulse Width
Pin E
160
Enable Rise/Fall Time
Pin E
Address Setup Time
Pins: RS,RW,E
10
Address Hold Time
Pins: RS,RW,E
20
Data Setup Time
Pins: DB0 - DB7
40
Data Hold Time
Pins: DB0 - DB7
20
Read Mode (Reading Data from ST7920 to MPU)
Enable Cycle Time
Pin E
1800
Enable Pulse Width
Pin E
320
Enable Rise/Fall Time
Pin E
Address Setup Time
Pins: RS,RW,E
10
Address Hold Time
Pins: RS,RW,E
20
Data Delay Time
Pins: DB0 - DB7
Data Hold Time
Pins: DB0 - DB7
20
Interface Mode with LCD Driver(ST7921)
Clock Pulse with High
Pins: CL1, CL2
800
Clock Pulse with Low
Pins: CL1, CL2
800
Clock Setup Time
Pins: CL1, CL2
500
Data Setup Time
Pin: D
300
Data Hold Time
Pin: D
300
M Delay Time
Pin: M
-1000
-
41/49
Max.
Unit
590
KHz
590
55
0.2
KHz
%
µs
25
-
ns
ns
ns
ns
ns
ns
ns
25
260
-
ns
ns
ns
ns
ns
ns
ns
1000
ns
ns
ns
ns
ns
ns
2008/08/18
ST7920
8-bit interface timing diagram
l
MPU write data to ST7920
RS
VIH1
VIL1
TAS
TAH
R/W
TPW
TAH
E
TH
TDSW
TR
Valid data
DB0-DB7
TC
l
MPU read data from ST7920
RS
VIH1
VIL1
TAS
TAH
R/W
TPW
TAH
TR
E
TH
TDDR
DB0-DB7
Valid data
TC
V4.0
42/49
2008/08/18
ST7920
AC Characteristics (TA = -30℃ ~ 85℃, VDD = 4.5V) Serial Mode Interface
Symbol
Characteristics
Test Condition
Min.
Typ.
Max.
Unit
R = 33KΩ
470
External Clock Operation
530
590
KHz
Internal Clock Operation
fOSC
OSC Frequency
fEX
External Frequency
-
470
530
590
KHz
Duty Cycle
-
45
50
55
%
TR,TF
Rise/Fall Time
-
-
-
0.2
µs
TSCYC
Serial clock cycle
SCLK high pulse
width
SCLK low pulse width
SID data setup time
SID data hold time
CS setup time
CS hold time
Pin E
400
-
-
ns
Pin E
200
-
-
ns
Pin E
Pins RW
Pins RW
Pins RS
Pins RS
200
40
40
60
60
-
-
ns
ns
ns
ns
ns
Min.
Typ.
Max.
Unit
470
530
590
KHz
TSHW
TSLW
TSDS
TSDH
TCSS
TCSH
AC Characteristics (TA = -30℃ ~ 85℃, VDD = 2.7V) Serial Mode Interface
Symbol
Characteristics
Test Condition
Internal Clock Operation
fOSC
OSC Frequency
R = 18KΩ
External Clock Operation
fEX
External Frequency
-
470
530
590
KHz
Duty Cycle
-
45
50
55
%
TR,TF
Rise/Fall Time
-
-
-
0.2
µs
TSCYC
Pin E
600
-
-
ns
Pin E
300
-
-
ns
TSLW
TSDS
TSDH
TCSS
Serial clock cycle
SCLK high pulse
width
SCLK low pulse width
SID data setup time
SID data hold time
CS setup time
Pin E
Pins RW
Pins RW
Pins RS
300
40
40
60
-
-
ns
ns
ns
ns
TCSH
CS hold time
Pins RS
60
-
-
ns
TSHW
V4.0
43/49
2008/08/18
ST7920
Serial interface timing diagram
l
MPU write data to ST7920
TCSS
TCSH
CS
TSCYC
TSLW
SCLK
TSHW
Tf
Tr
TSDS
SID
V4.0
TSDH
Valid data
44/49
2008/08/18
ST7920
I/O pin diagram
Input PAD: E (No Pull-up)
Input PAD: RS, RW (with Pull-up)
Output PAD: CL1, CL2, M, D
Enable
DATA
I/O PAD: DB0 – DB7
V4.0
45/49
2008/08/18
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
R2
4.7K
R3
2.2K
J1
R4
4.7K
V4.0
1
2
3
JP1
HEADER 16
1
2
1
C
R1
4.7K
VCC
R7
CON3
2K
R6
C1
104
B
33K
R5
4.7K
JK
CON2
2
1
2
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
R8
JP2
HEADER 2
V0
V1
V2
CLK
VXA
TT1
VXB
VXC
TT2
V3
V4
VSS
VDD
XRESET
CL1
CL2
VDD
M
DOUT
RS
RW
E
VSS
OSC1
OSC2
PSB
D0
D1
D2
D3
D4
D5
D6
R9
2
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
C33
C32
C31
C30
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
3
46/49
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
S95
S96
S97
S98
S99
S100
S101
S102
S103
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
C25
C26
C27
C28
C29
C30
C31
C32
S160
S159
S158
S157
S156
S155
S154
S153
S152
S151
S150
S149
S148
S147
S146
S145
S144
S143
S142
S141
S120
S119
S118
S117
S116
S115
S114
S113
S112
S111
S110
S109
S108
S107
S106
S105
S104
S103
S102
S101
S80
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S65
VCC
4
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
C16
C15
C14
C13
C12
C11
C10
C9
33
33
Title
JA
CON2
Size
Date:
File:
B
5
1-Mar-2001
D:\Buffer-2\7920V1.DDB
Number
C16
C15
C14
C13
C12
C11
C10
C9
C1
C2
C3
C4
C5
C6
C7
C8
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S100
S99
S98
S97
S96
S95
S94
S93
S92
S91
S90
S89
S88
S87
S86
S85
S84
S83
S82
S81
S140
S139
S138
S137
S136
S135
S134
S133
S132
S131
S130
S129
S128
S127
S126
S125
S124
S123
S122
S121
C24
C23
C22
C21
C20
C19
C18
C17
C24
C23
C22
C21
C20
C19
C18
C17
S140
S139
S138
S137
S136
S135
S134
S133
S132
S131
S130
S129
S128
S127
S126
S125
S124
S123
S122
S121
S100
S99
S98
S97
S96
S95
S94
S93
S92
S91
S90
S89
S88
S87
S86
S85
S84
S83
S82
S81
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
C1
C2
C3
C4
C5
C6
C7
C8
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
4
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S80
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S120
S119
S118
S117
S116
S115
S114
S113
S112
S111
S110
S109
S108
S107
S106
S105
S104
S103
S102
S101
S160
S159
S158
S157
S156
S155
S154
S153
S152
S151
S150
S149
S148
S147
S146
S145
S144
S143
S142
S141
C25
C26
C27
C28
C29
C30
C31
C32
D
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
2
S114
S115
S116
S117
S118
S119
S120
S121
S122
S123
S124
S125
S126
S127
S128
S129
S130
S131
S132
S133
S134
S135
S136
S137
S138
S139
S140
S141
S142
S143
S144
S145
S146
S147
S148
S149
S150
S151
R10
10K
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
1
S113
VCC
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
D7
XOFF
VOUT
CAP3M
CAP1P
CAP1M
CAP2P
CAP2M
VD2
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
ST7920
Application circuit 1:
LCD
: 32-COM x 160-SEG
LCD Voltage : VCC
5
6
L1
WDG1603P
D
VCC
U1
S1
V0
V2
V3
VSS
VDD
CL1
SHL1
SHL2
CL2
DL1
DR1
DL2
DR2
M
S49
S40
S41
S42
S43
S44
S45
S46
S47
S48
S96
S95
S94
S93
S92
S91
S90
S89
S88
U2
Sitronix
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
Revision
S104
S105
S106
S107
S108
S109
S110
S111
S112
S160
S159
S158
S157
S156
S155
S154
S153
S152
VCC
ST7920 LCM
Sheet 1 of 1
Drawn By: Paul Yung
1.2
6
2008/08/18
C
ST7921
C32
C31
C30
B
ST7920
VCC
A
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
R3
2.2K
J1
R4
4.7K
+
V4.0
1
2
3
JP1
HEADER 16
1
2
1
C
R1
4.7K
R2
4.7K
VCC
R7
CON3
2K
C1
104
R6
B
33K
R5
4.7K
JK
CON2
2
1
2
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
R8
JP2
HEADER 2
V0
V1
V2
CLK
VXA
TT1
VXB
VXC
TT2
V3
V4
VSS
VDD
XRESET
CL1
CL2
VDD
M
DOUT
RS
RW
E
VSS
OSC1
OSC2
PSB
D0
D1
D2
D3
D4
D5
D6
R9
33
+ C3
4.7u
JA
CON2
2
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
C33
C32
C31
C30
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
3
47/49
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
S95
S96
S97
S98
S99
S100
S101
S102
S103
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
C25
C26
C27
C28
C29
C30
C31
C32
S160
S159
S158
S157
S156
S155
S154
S153
S152
S151
S150
S149
S148
S147
S146
S145
S144
S143
S142
S141
S120
S119
S118
S117
S116
S115
S114
S113
S112
S111
S110
S109
S108
S107
S106
S105
S104
S103
S102
S101
S80
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S65
VCC
4
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
C16
C15
C14
C13
C12
C11
C10
C9
33
Title
C2
4.7u
Size
Date:
File:
B
5
Number
C16
C15
C14
C13
C12
C11
C10
C9
C1
C2
C3
C4
C5
C6
C7
C8
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S100
S99
S98
S97
S96
S95
S94
S93
S92
S91
S90
S89
S88
S87
S86
S85
S84
S83
S82
S81
S140
S139
S138
S137
S136
S135
S134
S133
S132
S131
S130
S129
S128
S127
S126
S125
S124
S123
S122
S121
C24
C23
C22
C21
C20
C19
C18
C17
C24
C23
C22
C21
C20
C19
C18
C17
S140
S139
S138
S137
S136
S135
S134
S133
S132
S131
S130
S129
S128
S127
S126
S125
S124
S123
S122
S121
S100
S99
S98
S97
S96
S95
S94
S93
S92
S91
S90
S89
S88
S87
S86
S85
S84
S83
S82
S81
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
C1
C2
C3
C4
C5
C6
C7
C8
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
4
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S80
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S120
S119
S118
S117
S116
S115
S114
S113
S112
S111
S110
S109
S108
S107
S106
S105
S104
S103
S102
S101
S160
S159
S158
S157
S156
S155
S154
S153
S152
S151
S150
S149
S148
S147
S146
S145
S144
S143
S142
S141
C25
C26
C27
C28
C29
C30
C31
C32
D
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
2
S114
S115
S116
S117
S118
S119
S120
S121
S122
S123
S124
S125
S126
S127
S128
S129
S130
S131
S132
S133
S134
S135
S136
S137
S138
S139
S140
S141
S142
S143
S144
S145
S146
S147
S148
S149
S150
S151
R10
10K
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
1
S113
VCC
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
D7
XOFF
VOUT
CAP3M
CAP1P
CAP1M
CAP2P
CAP2M
VD2
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
ST7920
Application circuit 2:
LCD
: 32-COM x 160-SEG
LCD Voltage : VCC x 2 (Voltage doubler is used). *VLCD (V0), VOUT and VCAP3M should not over 7V.
5
6
L1
WDG1603P
D
U1
S1
V0
V2
V3
VSS
VDD
CL1
SHL1
SHL2
CL2
DL1
DR1
DL2
DR2
M
S49
S40
S41
S42
S43
S44
S45
S46
S47
S48
S96
S95
S94
S93
S92
S91
S90
S89
S88
U2
Sitronix
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
Revision
S104
S105
S106
S107
S108
S109
S110
S111
S112
S160
S159
S158
S157
S156
S155
S154
S153
S152
VCC
ST7920 LCM (Booster)
17-Aug-2001
Sheet 1 of 1
D:\adom\Documents\sch\7920_B~13.DDB Drawn By: Paul Yang
1.4
6
2008/08/18
C
ST7921
C32
C31
C30
B
ST7920
VCC
A
ST7920
Application circuit 3:
Com 1-32
ST7920
DB0-DB7
To MPU
Seg 1-64
Dout
VDD
VSS
CL2
CL1
M
V0
V1
V2
V3
V4
Vcc(+5V/+3V)
VR
DL1
VDD
SHL1
SHL2
VSS
V0
V2
DR2
DL2
DR1
CL1
CL2
M
Regsister
Dot Matrix LCD Panel
Seg 1-96
V3
Regsister
ST7921
Regsister
Regsister
DL1
VDD
SHL1
SHL2
VSS
V0
V2
Seg 1-96
V3
VSS
ST7921
Regsister
VR=1K~30Kohm
Note:Regsister=2.2K~10K ohm
DR2
DL2
DR1
CL1
CL2
M
2008/08/18
48/49
V4.0
2Line 16Chinese Word (32-COM x 256-SEG)
:
LCD
ST7920
Application circuit for testing CGROM and HCGROM:
R1
R2
R2
R2
V4.0
49/49
2008/08/18