ST Sitronix ST7093 26 COM / 80 SEG LCD CONTROLLER/DRIVER FEATURES z CGROM :10240 bits(256chars 5 x 8 dots) z z z z z z z CGRAM :320 bits(8 chars 5 x 8 dots) DDRAM :64 bytes(16 x 4 ) ICONRAM :80 bits Low power operation support: -- 2.4 to 3.6V Wide range of LCD driver power -- 3.0 to 7.0V 4-bit or 8-bit MPU interface for both 68 and 80 series 4 pin clock synchronized serial interface COM/SEG bi-directional setting Voltage converter/regulator/follower/bias circuit built in z z z z z z 26 common x 80 segment liquid crystal display driver 32 steps electronic volume control Wide range of instruction functions: return home, display on/off, cursor on/off, display character blink, double height, line shift, function set, power and bias control Hardware reset pin available Internal oscillator or external clock Power save mode for low power consumption Bare Chip available GENERAL DESCRIPTION on one chip, a minimal system can be interfaced with this controller/driver. The ST7093 dot-matrix liquid crystal display controller can drive LSI displays alphanumeric, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4bit, 8 bit or 4 pin clock synchronized serial bus interface. For 4 bit and 8 bit bus interface both 68 series and 80 series type are available. Since all the functions such as display RAM, character generator, liquid crystal driver, oscillator and voltage control functions required for driving a dot-matrix liquid crystal display are internally provided Ver 2.1 The ST7093 character generator ROM is extended to generate 256 5 x 8 dot character fonts. The low power supply (2.4V to 3.6V) of the ST7093 is suitable for any portable battery-driven product requiring low power dissipation. The ST7093 LCD driver consists of 26 common signal drivers and 80 segment signal drivers with COG gold bump available. 1/43 2003/09/23 ST7093 BLOCK DIAGRAM RESETB CK Reset Circuit Timing Generator CPG DIRS COM1 to COM24 PS 25-bit shift registe IF MI CSB RS RW_WR E_RD MPU Instruction Register (IR) Display data RAM (DDRAM) 64X8bits interface Instruction Decoder Common Signal Driver 80-bit shift register DB4 to DB7 Address Counter Input/ Output Buffer COMI1 COMI2 80-bit latch circuit Segment Signal Driver SEG1 to SEG80 Data Register (DR) DB0 to DB3 LCD Drive Voltage Selector ICON RAM 80 bits Character generator RAM 320 bits (CGRAM) Character generator ROM 10,240 bits (CGROM) Cursor blink control Parallel/Serial Converter VDD LCD Power Circuit GND Voltage booster CAP1+ CAP1- CAP2+ CAP2- Ver 2.1 Voltage regulator Vout Vext REF 2/43 Bias Circuit V0 V1 V2 V3 V4 VR 2003/09/23 ST7093 PAD DIMENSIONS (COB) ........................ .. 167 (0,0) 179 86 74 ................................ 1 Ver 2.1 87 .. 166 73 Chip Size : 6775 X 1872 μm Min Pitch : 72 μm (Seg.) Pad Size : PAD No. 1~73 81.0μm x 64.8μm : PAD No. 74~86 64.8μm x 81.0μm : PAD No. 87~166 63.0μm x 84.6μm : PAD No. 167~179 64.8μm x 81.0μm 3/43 2003/09/23 ST7093 PAD DIMENSIONS (COG) 166 87 ........................ 86 .. .. 167 (0,0) 179 74 ................................ 1 73 Chip Size : 6775 X 1872 μm Min Pitch : 72 μm (Seg.) Bump Size : PAD No. Bump Height 1~73 68.4μm x 52.2μm : PAD No. 74~86 52.2μm x 68.4μm : PAD No. 87~166 50.4μm x 72μm : PAD No. 167~179 52.2μm x 68.4μm : 18 μm (Typ.) COG Align Key Coordinate 10um 50um 10um (-3270.5,819.3) 30um 30um 50um 50um 10um 10um 50um (3270.5,819.3) 30um 30um 30um 30um 30um 60um 30um 30um 30um (-2917,-731.5) Ver 2.1 (2672,-547) 4/43 2003/09/23 ST7093 PAD LOCATION Table 2. PAD Center Coordinates NO. PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PAD NAME DUMMY DUMMY DUMMY DUMMY DUMMY RS VSS RW VDD E CSB D7 D6 D5 D4 D3 D2 D1 D0 VDD VDD VDD VSS VSS VSS V4 V4 V3 V3 V2 V2 V1 V1 V0 V0 V0 V0 VR VR VOUT VOUT CAP2N CAP2N CAP2P CAP2P CAP1N CAP1N CAP1P CAP1P VEXT VSS VSS VSS VR DUMMY REF DIRS VDD VDD VDD Ver 2.1 X -3249 -3159 -3069 -2979 -2889 -2799 -2709 -2619 -2529 -2439 -2349 -2259 -2169 -2079 -1989 -1899 -1809 -1719 -1629 -1539 -1449 -1359 -1269 -1179 -1089 -999 -909 -819 -729 -639 -549 -459 -369 -279 -189 -99 -9 81 171 261 351 441 531 621 711 801 891 981 1071 1161 1251 1341 1431 1521 1611 1701 1791 1881 1971 2061 Y -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 NO. PAD 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PAD NAME X 2151 2241 2331 2421 2511 2601 2691 2781 2871 2961 3051 3141 3231 3272 3272 3272 3272 3272 3272 3272 3272 3272 3272 3272 3272 3272 2868 2796 2724 2652 2580 2508 2436 2364 2292 2220 2148 2076 2004 1932 1860 1788 1716 1644 1572 1500 1428 1356 1284 1212 1140 1068 996 924 852 780 708 636 564 492 CK VSS PSB VDD IF VSS MI VDD RESETB TEST3 TEST2 TEST1 TEST0 COMI1 COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] COM[17] COM[18] COM[19] COM[20] SEG[1] SEG[2] SEG[3] SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] SEG[33] SEG[34] 5/43 Y -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -454 -364 -274 -184 -94 -4 86 176 266 356 446 536 626 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 NO. PAD 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 PAD NAME SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] SEG[62] SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] COMI2 COM[24] COM[23] COM[22] COM[21] COM[16] COM[15] COM[14] COM[13] COM[12] COM[11] COM[10] COM[9] X Y 420 348 276 204 132 60 -12 -84 -156 -228 -300 -372 -444 -516 -588 -660 -732 -804 -876 -948 -1020 -1092 -1164 -1236 -1308 -1380 -1452 -1524 -1596 -1668 -1740 -1812 -1884 -1956 -2028 -2100 -2172 -2244 -2316 -2388 -2460 -2532 -2604 -2676 -2748 -2820 -3272 -3272 -3272 -3272 -3272 -3272 -3272 -3272 -3272 -3272 -3272 -3272 -3272 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 626 536 446 356 266 176 86 -4 -94 -184 -274 -364 -454 2003/09/23 ST7093 PIN DESCRIPTION NAME I/O Interfaced RS I MPU RW_WR I MPU E_RD I MPU DB4 to DB7 I/O MPU DB0 to DB3 I/O MPU CSB RESETB I I MPU MPU CK I MPU MI I MPU DIRS I MPU IF I MPU PS I MPU O LCD O LCD COM1 to COM24 COMI1,COMI2 SEG1 to SEG80 CAP1+, CAP1CAP2+, CAP2Vout VR O FUNCTION Select registers. 0: Instruction register (for write) address counter (for read) 1: Data register (for write and read) Select read or write. In 68 mode In 80 mode 0: Write 0: Write 1: Read 1: Not active Starts data read/write. In 68 mode In 80 mode 0: Not active 0: Read 1: Enable 1: Not active Four high order bi-directional tristate data bus pins. Used for data transfer and receive between the MPU and the ST7093. In serial interface mode DB7 is SI (input data), DB6 is SCL (serial clock). Four low order bi-directional tristate data bus pins. Used for data transfer and receive between the MPU and the ST7093. These pins are not used during 4-bit operation. (Fixed high) Chip select signal. Active low. Reset signal. Active low. External clock input pin. it must be fixed to “Vss” , when the internal oscillator circuit is used. In case of the external clock mode, CK is used as the clock and OS bit should be turn off. Interface selection 0: 80 mode interface 1: 68 mode interface SEG direction selection 0: SEG1 Æ SEG80 1: SEG80 Æ SEG1 Interface selection valid when PS=1 0: 4 bit bus mode 1: 8 bit bus mode Interface selection 0: serial mode 1: 4bit/ 8bit bus mode Common signals. COMI1 and COMI2 are the same signal Segment signals Capacitor connection pins for voltage booster Voltage booster output pin Voltage adjust pin between V0 and VSS Reference voltage selection pin REF I MPU 0: internal regulator is selected 1: external reference voltage input to Vext Vext I/O External reference voltage input Power supply for LCD drive V0 to V4 Power supply V0 - Vss = 7 V (Max) VDD , GND Power supply VDD : 2.4V to 3.6V, GND: 0V Test 0 to Test3 I Test pin. open Note: 1. V0>=V1>=V2>=V3>=V4>=VSS must be maintained Ver 2.1 I/O I 6/43 2003/09/23 ST7093 FUNCTION DESCRIPTION System Interface This chip has all two kinds of parallel interface type with MPU : 4-bit bus and 8-bit bus. 4-bit bus or 8-bit bus is selected by IF pin. During read or write operation, two 8-bit registers are used. One is data register (DR), the other is instruction register(IR). The data register(DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the next DDRAM/CGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM automatically. The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use RS input pin in 4-bit/8-bit bus mode and serial mode. Table 1. Various kinds of operations according to RS and R/W bits for 68 interface. RS RW_WR Operation L L Instruction Write operation (MPU writes Instruction code into IR) L H Read address counter (DB0 ~ DB6) H L Data Write operation (MPU writes data into DR) H H Data Read operation (MPU reads data from DR) Table 1.1. Various kinds of operations according to RS and R/W bits for 80 interface. RS RW_WR E_RD Operation L L H Instruction Write operation (MPU writes Instruction code into IR) L H L Read address counter (DB0 ~ DB6) H L H Data Write operation (MPU writes data into DR) H H L Data Read operation (MPU reads data from DR) Address Counter (AC) Address Counter(AC) stores DDRAM/CGRAM address, transferred from IR. After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports. RS RW_WR E_RD DB0-DB7 Instr Circuit Dummy read RAM read ite Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (68 Series MPU Mode) Ver 2.1 7/43 2003/09/23 ST7093 RS RW_WR E_RD DB0-DB7 RAM read Dummy read Instruction write Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (80 Series MPU Mode) RS RW_WR E_RD Upper lower DB4-DB7 4-bit 4-bit Instruction write Upper lower Upper lower 4-bit 4-bit 4-bit Dummy read 4-bit RAM read Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (68 Series MPU Mode) RS RW_WR E_RD Upper lower DB0-DB7 4-bit 4-bit Instruction write Upper lower Upper lower 4-bit 4-bit 4-bit Dummy read 4-bit RAM read Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (80 Series MPU Mode) Ver 2.1 8/43 2003/09/23 ST7093 Display Data RAM (DDRAM) Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 64 x 8 bits, or 64 characters. The area in display data RAM (DDRAM) that is not used for display can be used as general data RAM. See Figure 1 for the relationships between DDRAM addresses and positions on the liquid crystal display. The DDRAM address (ADD ) is set in the address counter (AC) as hexadecimal. z DDRAM address and corresponding display position There is 4 line display data stored in DDRAM but only 2 lines are shown at a time. (2 line mode) Hidden lines can be displayed by issuing line shift instruction. Figure 1 DDRAM Address High Low Order Order bits bits AC AC AC AC AC AC AC AC Example: DDRAM Address 37H 0 1 1 0 1 1 1 Display Position 00 COM1~8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F COM9~16 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Hidden 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F Hidden 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Figure 2 2-Line Mode by 16-Character Display Example Display Position 00 COM1~8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F COM17~24 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F COM9~16 Hidden 30 Figure 3 3-Line Mode by 16-Character Display Example Ver 2.1 9/43 2003/09/23 ST7093 Character Generator ROM (CGROM) The character generator ROM generates 5 x 8 dot character patterns from 8-bit character codes. It can generate 256 5 x 8 dot character patterns. User-defined character patterns are also available by mask-programmed ROM. Character Generator RAM (CGRAM) In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight character patterns can be written. Write into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the character patterns stored in CGRAM. See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not used for display can be used as general data RAM. Timing Generation Circuit The timing generation circuit generates timing signals for the operation of internal circuits such as DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than the display area. LCD Driver Circuit LCD Driver circuit has 26 common and 80 segment signals for LCD driving. Data from CGRAM/CGROM is transferred to 80 bit segment latch serially, and then it is stored to 80 bit shift latch. When each common is selected by 26 bit common register, segment data also output through segment driver from 80 bit segment latch. Cursor/Blink Control Circuit It can generate the cursor or blink in the cursor/blink control circuit. The cursor or the blink appears in the digit at the display data RAM address set in the address counter. Applicable Panel Size Font 5X8 Ver 2.1 Display Duty Contents of outputs 2 Line X 16 Char 1/17 2x16 characters + 80icons 3 Line x 16 Char 1/25 3x16 characters + 80icons 10/43 2003/09/23 ST7093 Correspondence between Character Codes and Character Patterns Table 4-1 Ver 2.1 11/43 2003/09/23 ST7093 Table 4-2 Ver 2.1 12/43 2003/09/23 ST7093 NO.7093-0C Ver 2.1 13/43 2003/09/23 ST7093 Character Code CGRAM Character Patterns (DDRAM Data) Address (CGRAM Data) b7 b6 b5 b4 b3 b2 b1 b0 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 - - 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 0 1 0 1 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 0 0 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 - - - - - - Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character patterns (CGRAM Data) Notes: 1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types). 2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line CGRAM address (b2,b1,b0) = (1,1,1) is the cursor line. Should the cursor position is displayed with CGRAM character the 8th line output data will become (1,1,1,1,1). 3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left). 4. 1 for CGRAM data corresponds to display selection and 0 to non-selection. “-“: Indicates no effect. Ver 2.1 14/43 2003/09/23 ST7093 z Relationship between ICONRAM address and display pattern When ICONRAM data is filled the corresponding position displayed is described as the following table. ICONRAM address ICONRAM bits D7 D6 D5 D4 D3 D2 00H S1 S2 S3 01H S6 S7 S8 02H S11 S12 S13 : : : : : : : 0DH S66 S67 S68 0EH S71 S72 S73 0FH S76 S77 S78 Notes : S1~S80 corresponds to display position of SEG1 ~ SEG80. z D1 S4 S9 S14 : S69 S74 S79 D0 S5 S10 S15 : S70 S75 S80 Segment data shift direction corresponding to DIRS pin setting Segment data shift direction can be altered by setting values to the DIRS pin described as the following table. DIRS Low High z Segment data shift direction S1 Æ S2 Æ S3 Æ S4 Æ S5 Æ ............... S78 Æ S79 Æ S80 S80 Æ S79 Æ S78 Æ S77 Æ S76 Æ ............... S3 Æ S2 Æ S1 Common data shift direction corresponding to S Common data shift direction can be altered by setting the S value through function set instruction. The directions corresponding to S value is described as the following table. S Low High Ver 2.1 Common data shift direction COM1 Æ COM2 Æ COM3 Æ ........... COM15 Æ COM24 Æ COMI1(COMI2) COMI1(COMI2) Æ COM24 Æ COM15 Æ .......... COM3 Æ COM2 Æ COM1 15/43 2003/09/23 ST7093 z Instructions There are four categories of instructions that: z Designate ST7093 functions, such as display format, data length, etc. z Set internal RAM addresses z Perform data transfer with internal RAM z Others Instruction Table: Instruction Code Instruction Return Home RS RW Description DB DB DB DB DB DB DB DB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 x Execution Time Set DDRAM address to "00H" from AC and return cursor to its 0 0 original position if shifted. The contents of DDRAM are not 80us changed. Set double height mode (DH2, DH1) = (0,0) : normal (default) (0,1) :1)2-line mode COM1..COM16 is a double height COM17..COM24 is no use Double height Mode 2) 3-line mode 0 0 0 0 0 0 1 0 COM1..COM16 is a double height DH2 DH1 Set 80us COM17..COM24 is normal (1,0) : 1) 2-line mode normal display 2) 3-line mode COM1..COM8 is normal COM9..COM24 is a double height l (1,1) : normal Display control Power save control C=0 : cursor off(default) C=1: cursor on 0 0 0 0 1 0 1 C B D B=0 : blink off (default) B=1: blink on 80us D=0 : display off(default) D=1: display on 0 0 0 0 0 0 1 1 OS PS OS=0 : OSC off(default) OS=1 : OSC on PS=0 : save off(default) PS=1 : save on 80us (Display line mode) N=0 : 2 line display(default) N=1 : 3 line display (Shifting direction of COM) Function Set 0 0 0 0 0 1 0 N S CG S=0 : 1) 2-line mode COM1ÆCOM16(default) 2) 3-line mode COM1ÆCOM24(default) 80us S=1 : 1) 2-line mode COM16 Æ COM1 2) 3-line mode COM24 Æ COM1 (Select CGRAM or CGROM) CG=0 : CGROM(default) CG=1 : CGRAM Ver 2.1 16/43 2003/09/23 ST7093 Instruction Code Instruction RS RW Description DB DB DB DB DB DB DB DB 7 6 5 4 3 2 1 0 Execution Time (LS2,LS1) = (0,0) : DDRAM line 1 on top Line shift mode 0 0 0 0 0 1 1 0 LS2 LS1 (0,1) : DDRAM line 2 on top (1,0) : DDRAM line 3 on top 80us (1,1) : DDRAM line 4 on top Bias control 0 0 0 0 0 1 1 1 x BS BS=0 : 1/5 bias(default) BS=1 : 1/4 bias 80us VC=0 : voltage booster off(default) =1 : voltage booster on Power control 0 0 0 0 1 0 0 VC VR VF VR=0 : voltage regulator off(default) =1 : voltage regulator on 80us VF =0 : voltage follower off(default) =1 : voltage follower on ICONRAM address 0 0 0 0 0 1 CGRAM/ DDRAM address Write data to RAM Read data from RAM 1 0 AC AC AC AC AC Set ICONRAM address in address counter 4 3 2 1 0 AC AC AC AC AC AC AC 6 5 4 3 2 1 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 EV addr : 10H 80us Set CGRAM/DDRAM address DDRAM : 00H ~ 3FH 80us CGRAM : 40H ~ 7FH Write data into internal RAM (DDRAM/CGRAM) Read data from internal RAM (DDRAM/CGRAM) 80us 80us Note: 1. “x” Don’t care 2. Make sure to use enough delay time(100us) between instruction Ver 2.1 17/43 2003/09/23 ST7093 INSTRUCTION DESCRIPTION z Return Home RS Code RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 x Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to the left edge on first line of display. z Double height mode RS Code RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 DH2 DH1 Set double height mode DH2 DH1 Action Low Low Normal display (default) 1) 2-line mode COM1..COM16 is a double height Low High COM17..COM24 is no use 2) 3-line mode COM1..COM16 is a double height COM17..COM24 is normal 1) 2-line mode normal display High Low 2) 3-line mode COM1..COM8 is normal COM9..COM24 is a double height High Ver 2.1 High Normal display 18/43 2003/09/23 ST7093 3 Line mode normal display (DH2,DH1=0,0) 3 Line mode COM1 ..16 is a double height line, COM17 .. 24 is normal (DH2,DH1=0,1) COM1 ..8 is normal , COM9 .. 24 is a double height line (DH2.DH1 = 1,0) Ver 2.1 19/43 2003/09/23 ST7093 2 line mode normal display (DH2,DH1=0,0) 2 line mode COM1 ..16 is a double height line (DH2,DH1=0,1) z Bias Control RS Code 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 1 * BS Bias control instruction will set the internal bias level generator BS = “Low” (default) : 1/5 bias = ”High” : 1/4 bias z Display control RS Code 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 1 C B D Control display/cursor/blink ON/OFF 1 bit register. C : Cursor ON/OFF control bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display. The cursor data performs exclusive OR with any display data on the cursor line. B : Cursor Blink ON/OFF control bit Ver 2.1 20/43 2003/09/23 ST7093 When B = "High", C=”High” then performs alternate between reverse display character and display character at the cursor position. If C=”Low” then display is normal regardless of B. When B = "Low", blink is off. D : Display ON/OFF control bit When D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM. z Function set RS Code 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 N S CG (Display line mode) N : Number of display lines =”Low” (default) : 2 lines COM1~COM16 are displayed =”High” : 3 lines COM1~COM24 are displayed (Shifting direction of COM) S : Common data shift direction =”Low” (default) : 1) 2-line mode COM1ÆCOM16(default) 2) 3-line mode COM1ÆCOM24(default) =”High” : 1) 2-line mode COM16 Æ COM1 2) 3-line mode COM24 Æ COM1 (Select CGRAM or CGROM) CG: CGRAM enable bit =”Low” (default) : CGRAM is disabled, CGROM data pattern will appear on the display instead. =”High” : CGRAM enabled. z Power save set RS Code 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 1 OS PS OS : Oscillator on/off bit When OS = "High", internal oscillator is enabled. When OS = "Low" (default), internal oscillator is disabled PS : Power save mode When PS = "Low" (default) Power save mode is disabled. When PS = "High" , Power save mode is enabled. Ver 2.1 21/43 2003/09/23 ST7093 z Set ICONRAM Address RS Code RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 AC AC AC AC AC Set ICONRAM address to AC. Before writing or reading data, set ICONRAM address should be performed. After each write or read the address counter will increase 1 automatically. 5 bit ICON is stored in each data byte. If (C,B) = (1,1) then ICON display will blink. ICONRAM address is from 00H to 0FH. Address 10H is reserved for electronic volume level setting. z Set CGRAM/DDRAM Address RS Code RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 AC AC AC AC AC AC AC Set CGRAM /DDRAM address to AC. CGRAM and DDRAM share the same address space. Before accessing CGRAM/DDRAM, set CGRAM/DDRAM address should be performed. Address counter will automatically increase by 1 after each write or read operation. After accessing 7FH the address will reset to 00H. Addr z 0 1 2 3 4 5 6 7 8 9 A 00H DDRAM LINE 1 (00H~0FH) 10H DDRAM LINE 2 (10H~1FH) 20H DDRAM LINE 3 (20H~2FH) 30H DDRAM LINE 4 (30H~3FH) B C D 40H CGRAM (pattern 0) CGRAM (pattern1) 50H CGRAM (pattern 2) CGRAM (pattern 3) 60H CGRAM (pattern 4) CGRAM (pattern5) 70H CGRAM (pattern 6) CGRAM (pattern 7) E F Read Data from CGRAM/DDRAM or ICONRAM RS Code 1 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 D7 D6 D5 D4 D3 D2 D1 D0 Before RAM data read, address set of either CGRAM/DDRAM or ICONRAM should be performed. The first read is a dummy read. The data is invalid. The correct data is obtain from the second read. After read data the address counter will increase by 1 automatically. If multiple read in succession only the first read data is dummy. Ver 2.1 22/43 2003/09/23 ST7093 z Line shift mode RS Code 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 0 LS2 LS1 Set Line Shift mode LS2 LS1 Action Low Low DDRAM Line1 shows at the first line of LCD (default) Low High DDRAM Line2 shows at the first line of LCD High Low DDRAM Line3 shows at the first line of LCD High High DDRAM Line4 shows at the first line of LCD Reset Function Initializing by Internal Reset Circuit External reset can be achieved by pulling low RESETB pin. 1. Function set: S = 0; COM left shift CG = 0; CGRAM disable 2. Display on/off control: D = 0; Display off C = 0; Cursor off B = 0; Blinking off 3. Power control & bias BS = 0 ; 1/5 bias OS = 0 ; oscillator off PS = 0 ; power save off VC = 0; voltage booster off VR = 0; voltage regulator off VF = 0; voltage follower off 4. Line shift mode (LS2,LS1) = (0,0) ; DDRAM line 1 shown at the first line of LCD display 5. Electronic contrast control register (E4,E3,E2,E1,E0) = (0,0,0,0,0) RESETB pulse width Trw 10us RESET start time Tres 50ns Ver 2.1 23/43 2003/09/23 ST7093 VDD Tres RESETB Trw Ver 2.1 24/43 2003/09/23 ST7093 Interfacing to the MPU The ST7093 can send data in either two 4-bit operations or one 8-bit operation, or 4 pin clock synchronous serial interface is used. z For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3 are disabled. The data transfer between the ST7093 and the MPU is completed after the 4-bit data has been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7) are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). z For 8-bit interface data, all eight bus lines (DB0 to DB7) are used. z For serial interface, by setting PS = “Low” DB7 become SI (serial in data), DB6 become SCL (serial clock). Each bit of data transfer is at the rising edge of SCL. At the rising edge of 8th SCL the data is converted into 8 bit parallel data and RS bit is read in to select whether write data or write instruction. Read operation is not supported. CSB SI 100us 100us D7 D6 ……. D0 D7 D6 …..……D0 SCL RS Timing Diagram of Serial Mode Data Transfer (serial Mode) Supply Voltage for LCD Drive There are different voltages that supply to ST7093’s pin (V0 – V4) to obtain LCD drive waveform. The relations of the bias, duty factor and supply voltages are shown as below: Duty Factor 1/17 Bias Ver 2.1 Supply Voltage 1/4 1/5 V0 VLCD VLCD V1 3/4 VLCD 4/5 VLCD V2 1/2VLCD 3/5 VLCD V3 1/2VLCD 2/5 VLCD V4 1/4 VLCD 1/5 VLCD 25/43 2003/09/23 ST7093 Initialization sequence Power On RESETB = 0 Wait 10us RESETB = 1 Wait 10us Power save(PS, OS) Function set (S,CG) Power control(VC,VR,VF) Electronic contrast set Wait time > 20ms Clear DDRAM Clear CGRAM Clear ICONRAM Display on Initialization End Ver 2.1 26/43 2003/09/23 ST7093 Sleep mode set End of initialization Normal operation (PS=0 , OS=1) Display off (D=0) Power save (PS=1 , OS=0) Power control off (VC=0, VR=0, VF=0) Enter sleep mode Sleep mode release Sleep mode Power save (ps=0, os=1) Power control on (VC=1,VR=1,VF=1) Wait more than 20ms Display on (D=1) Resume normal operation Ver 2.1 27/43 2003/09/23 ST7093 Power off sequence Normal operation Display off (D=0) Power save (PS=1, OS=0) Power control off (VC=0,VR=0,VF=0) Wait more than 10ms Power off Ver 2.1 28/43 2003/09/23 ST7093 Voltage booster The voltage booster use internal generates reference voltage 1.8V to boost 4 times to produce Vout as 7.2V. vout Vdd + + - 1.8V X 4 =7.2V Cap1+ Cap1- + - 1.8v Cap2+ Cap2Vout vss Voltage regulator The voltage regulator circuit is used to obtain an appropriate LCD panel driving voltage. This voltage is obtained By adjusting resistors Ra and Rb as shown in equation (1) or (2) ,and by setting Electronic Contrast Control data Bits, see this equation (3) or (4). The potential of V0 Pin can be adjusted within Vout – Vref, Vref is the internal constant voltage source of the Chip and this value is 2.0V in the condition vdd ≧ 2.4V The REF selects which voltage is used for voltage regulator between the ecternal VEXT and internal Vref. ▓ Voltage regulation by adjusting resistors Ra, Rb Rb Vout When REF is “Low” V0 = ( 1 + Rb / Ra ) x Vref…..…(1) VR When REF is “High” V0 = ( 1 + Rb / Ra ) x VEXT …..(2) Reference set value Ra = 1MΩ Rb = 1.5MΩ VEXT + - Ra Vo + REF Vref Inside Chip Vss GND Ver 2.1 29/43 Voltage regulator circuit 2003/09/23 ST7093 Electronic contrast control (32 steps) Electronic contrast control data bits is 10H = (C4, C3, C2, C1, C0 ), Voltage regulation is adjusted as 32-contrast step According to the value of Electronic contrast control data bits. LCD drive voltage V0 has one of 32 voltage values if 5-bit data is set to the electronic contrast control register (ICONRAM address 10H). When using the electronic contrast control function, you need to turn the voltage regulators on using power control instruction. When REF is “Low” V0 = ( 1 + Rb / Ra ) x Ven ….. (3) Ven = Vref - nα ( n = 0, 1, 2, ….. 30, 31 ) α = Vref / 150 Rb Vout VR + VEXT When REF is “High” V0 = ( 1 + Rb / Ra ) x Ven ….. (4) Ven = Vext - nα ( n = 0, 1, 2, ….. 30, 31 ) α = Vext / 150 Ra Vref + Ven - Inside Chip + - Vo REF Vss GND Electronic contrast control circuit No. 1 2 3 4 . . . 31 32 Ver 2.1 C7 C6 C5 C4 - 0 - 0 - 0 - 0 - - - C3 C2 C1 C0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 n V0 Contrast 0 (default) Maximum High 1 . . 2 . . 3 . . . . . . . . . . . 1 1 1 1 0 30 . . 1 1 1 1 1 31 Minimum Low Electronic contrast control register (“-“ don’t care) 30/43 2003/09/23 ST7093 Voltage generator circuit VDD Vdd Cap1+ Cap1Cap2+ Cap2Vout C1 + C1 VR Ra Rb GND - + V0 V1 V2 V3 V4 Vss C2 C2 C2 C2 C2 C1: 0.1 .. 4.7Uf C2: 0.1uF Ra: 1MΩ Rb:1.5MΩ GND When built-in power supply is used (VC,VR,VF = 1,1,1) VDD VDD External l VDD Vdd Cap1+ Cap1Cap2+ Cap2Vout VR GND Ra C2 C2 C2 C2 C2 Vdd Cap1+ Cap1Cap2+ Cap2Vout VR VR External Power supply Rb GND Vdd Cap1+ Cap1Cap2+ Cap2Vout GND - + V0 V1 V2 V3 V4 Vss GND - + C2 C2 C2 C2 C2 V0 V1 V2 V3 V4 Vss GND (VC,VR,VF= 0,1,1) V0 V1 V2 V3 V4 Vss GND (VC,VR,VF= 0,0,1) When external power supply is used Ver 2.1 External Power supply 31/43 (VC,VR,VF= 0,0,0) (C2:01 to 4.7uF) 2003/09/23 ST7093 MPU Interface VCC 8080 series MPU VDD A0 A1-A7 IORQ PS MI RS Decoder CSB ST7093 /RD /WR D0~D7 /RES E_RD RW_WR DB[0~7] RESETB RESETB GND IF VSS Parallel interfacing with 8080-series microprocessors. VCC 6800 series MPU GND VDD A0 A1-A7 /VMA PS MI RS Decoder CSB ST7093 R/W E DB[0~7] /RES RW_WR E_RD DB[0~7] RESETB RESETB IF VSS Parallel interfacing with 6800-series microprocessors. Ver 2.1 32/43 2003/09/23 ST7093 VCC PORT4 RS ST7093 MPU GND Fixed to high VDD IF MI PORT3 CSB PORT1 PORT2 /RES RW_WR SCL(DB6) E_RD SI(DB7) DB0~DB5 RESETB PS RESETB VSS Clock synchronized serial interfacing with any microprocessors. Ver 2.1 33/43 2003/09/23 ST7093 z Absolute Maximum Ratings Characteristics Symbol Value Power Supply Voltage VDD -0.3V to +7.0V LCD Driver Voltage VLCD -0.3V to +10.0V Input Voltage VIN -0.3V to VDD+0.3V Operating Temperature TA -40oC to + 85oC Storage Temperature TSTO -55oC to + 125oC DC CHARACTERISTICS ( TA = 25oC , VDD =2.4V – 3.6V ) Symbol Characteristics Condition Min. Typ. Max. Unit VDD Operating Voltage - 2.4 - 3.6 V VLCD LCD Voltage V0- VSS 3.0 - 7.0 V IDD Power Supply fOSC = 160KHz, VDD =3.0V - 90 115 uA Current checker pattern - 0.7VDD - VDD V - - 0.3 - 0.6 V - VDD – 1 - VDD V - - - 1.0 V IOH = -0.1mA 0.8VDD - VDD V IOL = 0.1mA - - 0.4 V IOH = -0.04mA 0.8VDD - VDD V IOL = 0.04mA - - 0.2 VDD V no CPU access VIH1 Input High Voltage (Except OSC1) VIL1 Input Low Voltage (Except OSC1) VIH2 Input High Voltage (OSC1) VIL2 Input Low Voltage (OSC1) VOH1 Output High Voltage (DB0 - DB7) VOL1 Output Low Voltage (DB0 - DB7) VOH2 Output High Voltage (Except DB0 - DB7) VOL2 Output Low Voltage (Except DB0 - DB7) RCOM Common Resistance VLCD = 4V, Id = 0.05mA - 2 20 KΩ RSEG Segment Resistance VLCD = 4V, Id = 0.05mA - 2 30 KΩ ILEAK Input Leakage VIN = 0V to VDD -1 - 1 µA Current Ver 2.1 34/43 2003/09/23 ST7093 AC CHARACTERISTICS (TA = 25oC, VDD = 2.7 V - 3.6 V) Symbol Characteristics Test Condition Min. Typ. Max. Unit Internal Clock Operation fOSC OSC Frequency - 112 160 208 KHz 112 160 208 KHz 45 50 55 % 0.2 µs External Clock Operation fEX TR,TF Ver 2.1 External Frequency Duty Cycle - Rise/Fall Time - 35/43 2003/09/23 ST7093 TIMING CHARACTERISTICS z Writing data from MPU TO ST7093 by 68 mode parallel interface RS,CSB VIH1 VIL1 TAH TAS RW_WR TAH TPW E_RD TH TDSW TR DB0-DB7 Valid data TC z Reading data from ST7093 TO MCU by 68 mode parallel interface VIH1 VIL1 RS,CSB TAS TAH RW_WR TPW TR TAH E_RD TH TDDR DB0-DB7 Valid data TC Ver 2.1 36/43 2003/09/23 ST7093 68 INTERFACE READ/WRITE TIMING(TA = 25oC, VDD =3.6V) READ MODE WRITE MODE Symbol Characteristics Test Condition Min. Typ. Max. Unit TC Enable Cycle Time Pin E 100 - - us TPW Enable Pulse Width Pin E 300 - - ns - - 25 ns 100 - - ns TR,TF Enable Rise/Fall Time Pin E TAS Address Setup Time Pins: RS,RW,CSB TAH Address Hold Time Pins: RS,RW,CSB 20 - - ns TDSW Data Setup Time Pins: DB0 - DB7 150 - - ns TH Data Hold Time Pins: DB0 - DB7 20 - - ns TC Enable Cycle Time Pin E 100 - - us TPW Enable Pulse Width Pin E 300 - - ns - - 25 ns TR,TF Enable Rise/Fall Time Pin E TAS Address Setup Time Pins: RS,RW,CSB 360 - - ns TAH Address Hold Time Pins: RS,RW,CSB 20 - - ns TDDR DB output ready Time Pins: DB0 - DB7 - - 300 ns TH DB output Hold Time Pins: DB0 - DB7 50 - - ns READ MODE WRITE MODE 68 INTERFACE READ/WRITE TIMING (TA = 25oC, VDD = 2.7V) Ver 2.1 Symbol Characteristics TC TPW Enable Cycle Time Enable Pulse Width Enable Rise/Fall Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time TR,TF TAS TAH TDSW TH TC TPW TR,TF TAS TAH TDDR TH Test Condition Min. Typ. Max. Unit Pin E Pin E 100 300 - - us ns Pin E - - 25 ns Pins: RS,RW,CSB Pins: RS,RW,CSB Pins: DB0 - DB7 Pins: DB0 - DB7 500 20 300 20 - - ns ns ns ns Enable Cycle Time Pin E Enable Pulse Width Pin E Enable Rise/Fall Pin E Time Address Setup Time Pins: RS,RW,CSB Address Hold Time Pins: RS,RW,CSB DB output ready Time Pins: DB0 - DB7 DB output Hold Time Pins: DB0 - DB7 100 300 - - us ns - - 25 ns 580 20 50 - 340 - ns ns ns ns 37/43 2003/09/23 ST7093 z Writing data from MPU to ST7093 by 80 mode parallel interface RS,CSB VIH1 VIL1 TAH TAS E_RD TPW RW_WR TH TDSW TF DB0-DB7 Valid data TC z Reading data from ST7093 to MPU by 80 mode parallel interface RS,CSB VIH1 VIL1 TAH TAS RW_WR TPW E_RD TDDR DB0-DB7 TH Valid data TC Ver 2.1 38/43 2003/09/23 ST7093 READ MODE WRITE MODE 80 INTERFACE READ/WRITE TIMING (TA = 25oC, VDD = 3.6V) Symbol TC TPW TR,TF TAS TAH TDSW TH TC TPW TR,TF TAS TAH TDDR TH Characteristics Test Condition Enable Cycle Time Pin E Enable Pulse Width Pin E Enable Rise/Fall Pin E Time Address Setup Time Pins: RS,RW,CSB Address Hold Time Pins: RS,RW,CSB Data Setup Time Pins: DB0 - DB7 Data Hold Time Pins: DB0 - DB7 Enable Cycle Time Pin E Enable Pulse Width Pin E Enable Rise/Fall Pin E Time Address Setup Time Pins: RS,RW,CSB Address Hold Time Pins: RS,RW,CSB DB output ready Time Pins: DB0 - DB7 DB output Hold Time Pins: DB0 - DB7 Min. 100 300 Typ. - Max. - Unit us ns - - 25 ns 40 200 180 40 100 300 - - ns ns ns ns us ns - - 25 ns 360 20 50 - 300 - ns ns ns ns Typ. - Max. - Unit us ns - - 25 ns 40 380 280 40 100 300 - - ns ns ns ns us ns - - 25 ns 440 40 50 - 340 - ns ns ns ns READ MODE WRITE MODE 80 INTERFACE READ/WRITE TIMING (TA = 25oC, VDD = 2.7V) Ver 2.1 Symbol TC TPW TR,TF TAS TAH TDSW TH TC TPW TR,TF TAS TAH TDDR TH Characteristics Test Condition Enable Cycle Time Pin E Enable Pulse Width Pin E Enable Rise/Fall Pin E Time Address Setup Time Pins: RS,RW,CSB Address Hold Time Pins: RS,RW,CSB Data Setup Time Pins: DB0 - DB7 Data Hold Time Pins: DB0 - DB7 Enable Cycle Time Pin E Enable Pulse Width Pin E Enable Rise/Fall Pin E Time Address Setup Time Pins: RS,RW,CSB Address Hold Time Pins: RS,RW,CSB DB output ready Time Pins: DB0 - DB7 DB output Hold Time Pins: DB0 - DB7 39/43 Min. 100 300 2003/09/23 ST7093 z Writing data from MPU TO ST7093 by Serial mode interface tSU1 tC CSB tR tH1 tW tW SCL tF tSU2 tH2 RS tSU3 tH3 SI WRITE MODE SERIAL INTERFACE WRITE TIMING Symbol TC TW TR,TF TSU1 TH1 TSU2 TH2 TSU3 TH3 Characteristics Enable Cycle Time Enable Pulse Width Enable Rise/Fall Time CSB Setup Time CSB Hold Time Rs Data Setup Time Rs Data Hold Time SI Data Setup Time SI Data Hold Time Test Condition Pin SCL Pin SCL WRITE MODE Ver 2.1 TR,TF TSU1 TH1 TSU2 TH2 TSU3 TH3 Characteristics Enable Cycle Time Enable Pulse Width Enable Rise/Fall Time CSB Setup Time CSB Hold Time Rs Data Setup Time Rs Data Hold Time SI Data Setup Time SI Data Hold Time Min. 3.0 1.5 Typ. Pin SCL Pin CSB Pin CSB Pin RS Pin RS Pin SI Pin SI SERIAL INTERFACE WRITE TIMING Symbol TC TW (TA = 25oC, VDD = 3.6V) Max. Unit us us 25 ns 20 100 40 40 40 40 ns us ns ns ns ns (TA = 25oC, VDD = 2.7V) Test Condition Pin SCL Pin SCL Min. 5.0 2.5 Pin SCL Pin CSB Pin CSB Pin RS Pin RS Pin SI Pin SI 20 100 40 40 40 40 40/43 Typ. Max. Unit us us 25 ns ns us ns ns ns ns 2003/09/23 ST7093 I/O PAD Configuration Control Data Data Input PADs without pull up PMOS Input PADs with pull up PMOS Enable Cont Data DATA I/O PADs with pull up PMOS When PS=1 all inputs and I/O pins are without PMOS pull up. When PS=0 since only CSB, RS and DB6, DB7 is used for data transmission therefore RW_WR, E_RD and DB0~DB5 has internal pull up PMOS. All system configuration pins such as CK,MI,PS,IF and DIRS are without pull up. Ver 2.1 41/43 2003/09/23 ST7093 Typical application ST7093A 5x8 dots, 16 characters x 2 line (1/5 bias, 1/17 duty) COM1 . . . . . COM8 COM9 . . . . . . COM16 COMI1 SEG1 . . . . . . . SEG80 Ver 2.1 LCD Panel: 16 Characters x 2 line 42/43 2003/09/23 ST7093 ST7093 Specification Revision History Version Date Description 0.1A 2000/06/12 1. 17com*60segment (Original) 0.2A 2000/10/01 1. 26com*80segment 1. Changed DC characteristics VLCD=V0-VSS 0.3 2001/01/08 2. CGROM standard font 0B&C0A 3. Modify 3-Line mode double height instruction 4. Modify AC characteristics 1. Modify Booster 2.4Vx4 Æ 1.8Vx4 (page 27) 2. 2line17duty,3line25duty (Page 10) 0.3B 2001/03/12 3. COG Align Key Coordinate (page 4) 4.Reference Ra,Rb value (page 27,29) 5. Modify pin description CK , D0..D3 , TEST pin 0.4 2001/04/17 1. Modify AC characteristics 0.4b 2002/02/07 1. Add COB Pad Dimensions 1. Modify double height mode instruction ( P16 & P18 ) 2. Add illustration of electronic contrast control circuit ( P30 ) 1.0 2002/05/23 3. Add illustration of voltage regulator circuit ( P29 ) 4. Add illustration of MPU interface ( P32 & P33 ) 2.0 2002/08/29 2.0b 2002/09/05 2.1 2003/09/23 Ver 2.1 1. Modify Operating Voltage 2.4V .. 3.6V 1. Modify CK pin must fixed “Vss” 2. CGROM standard font 0C 1. Modify product number to ST7093 43/43 2003/09/23