SONY CXG1216UR

High Power DP4T Switch with Logic Control
CXG1216UR
Description
The CXG1216UR can be used in wireless communication systems, for example, dual-band and triple-band
CDMA handsets.
This IC has on-chip logic for operation with 4 COMS control inputs.
The Sony JPHEMT process is used for low insertion loss and on-chip logic circuit.
(Applications: Antenna switch for cellular handsets, dual-band and triple-band CDMA)
Features
‹ Low insertion loss: 0.35dB@900MHz, 0.50dB@2GHz
‹ 4 CMOS compatible control line
Package
Small package size: 20-pin UQFN
Structure
GaAs JPHEMT MMIC
Absolute Maximum Ratings
(Ta = 25°C)
Š Input power max. (RF port)
Pin
34
dBm
Š Bias voltage
VDD
7
V
Š Control voltage
Vctl
5
V
Š Operating temperature
Topr
–35 to +85
°C
Š Storage temperature
Tstg
–65 to +150
°C
This IC is an ESD sensitive device. Special handling precautions are required.
The actual ESD test data will be available later.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license
by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating
the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E06947
CXG1216UR
20
19
18
F9
RF6 (Ext)
CRF
RF2 (800MHz (2))
GND
CRF
RF1 (800MHz (1))
GND
GND
Block Diagram and Recommended Circuit
17
16
F10
F1
1
15
GND
F5
CRF
GND
F14
RF3 (2GHz)
F2
2
14
F6
GND
CRF
F11
F3
3
13
GND
F7
RF5 (Ant)
F4
4
12
RF4
F8
CRF
CRF
F12
F13
5
11
10
CTLD
9
CTLC
8
CTLB
7
GND
Cbypass
(100pF)
VDD
6
CTLA
GND
When using this IC, the following external components should be used:
CRF: This capacitor is used for RF decoupling and must be used for all applications.
Cbypass: This capacitor is used for DC line filtering.
-2-
CXG1216UR
Truth Table
State CTLA CTLB CTLC CTLD
ON state
F1
F2
F3
F4
F5
F6
F7
F8
F9 F10 F11 F12 F13 F14
1
L
L
H
L
RF5–1
ON OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON OFF ON
(800MHz(1)-Ant)
2
L
L
H
H
RF5–2
OFF ON OFF OFF OFF OFF OFF OFF ON OFF ON ON OFF ON
(800MHz(2)-Ant)
3
L
H
H
L
RF5–3
(2GHz-Ant)
OFF OFF ON OFF OFF OFF OFF OFF ON ON OFF ON OFF ON
4
H
L
H
L
RF5–4
(RF4-Ant)
OFF OFF OFF ON OFF OFF OFF OFF ON ON ON OFF OFF ON
5
L
L
L
L
RF6–1
OFF OFF OFF OFF ON OFF OFF OFF OFF ON ON ON ON OFF
(800MHz(1)-Ext)
6
L
L
L
H
RF6–2
OFF OFF OFF OFF OFF ON OFF OFF ON OFF ON ON ON OFF
(800MHz(2)-Ext)
7
L
H
L
L
RF6–3
(2GHz-Ext)
OFF OFF OFF OFF OFF OFF ON OFF ON ON OFF ON ON OFF
8
H
L
L
L
RF6–4
(RF4-Ext)
OFF OFF OFF OFF OFF OFF OFF ON ON ON ON OFF ON OFF
DC Bias Conditions
(Ta = 25°C)
Item
Min.
Typ.
Max.
Unit
Vctl (H)
1.5
2.6
3.2
V
Vctl (L)
0
—
0.5
V
2.6
2.85
3.2
V
VDD
Pin Description
Pin No.
Symbol
Pin No.
Symbol
1
RF6 (Ext)
11
GND
2
GND
12
RF4
3
GND
13
GND
4
RF5 (Ant)
14
RF3 (2GHz)
5
GND
15
GND
6
VDD
16
RF2 (800MHz (2))
7
CTLA
17
GND
8
CTLB
18
RF1 (800MHz (1))
9
CTLC
19
GND
10
CTLD
20
GND
-3-
CXG1216UR
Electrical Characteristics
(Ta = 25°C, VDD = 2.85V)
Item
Insertion loss
Isolation
Symbol
IL
ISO
Condition
Min.
Typ.
Max.
Unit
830 to 930MHz
0.35
0.55
dB
1575.42MHz
0.40
0.60
dB
1.92 to 2.17GHz
0.50
0.70
dB
830 to 930MHz
25
32
dB
1575.42MHz
23
30
dB
1.92 to 2.17GHz
20
30
dB
1.2
—
VSWR
VSWR
Switching speed
TSW
1dB compression input power
P1dB
VDD = 2.85V
2fo
*1
–70
–65
dBc
3fo
*1
–70
–65
dBc
2fo
*2
–65
–60
dBc
3fo
*2
–65
–60
dBc
Harmonics
Input IP3
IIP3
Bias current
Idd
Control current
Ictl
*1
*2
*3
*4
50Ω
5
10
32
μs
dBm
*3
55
60
dBm
*4
55
60
dBm
VDD = 2.85V
200
Vctl (H) = 2.6V to 1.5V
Vctl (L) = 0V
–8
–5
μA
μA
0
Pin = 25dBm, 0/2.6V control, VDD = 2.85V, 890 to 930MHz
Pin = 25dBm, 0/2.6V control, VDD = 2.85V, 1.92 to 1.98GHz
Pin = 25dBm (900MHz) + 25dBm (901MHz), 0/2.6V control, VDD = 2.85V
Pin = 25dBm (1.9GHz) + 25dBm (1.901GHz), 0/2.6V control, VDD = 2.85V
-4-
250
–3
μA
CXG1216UR
Package Outline
(Unit: mm)
20PIN UQFN (PLASTIC)
x4
0.1
S
C
A-B
0.4 ± 0.1
1.3
0.55 ± 0.05
2.7
4-R0.3
15
C
11
10
20
6
A
B
2.7
16
26
0.14
1
0.
5
0.4
PIN 1 INDEX
0.18
Thermal Die Pad
0.07
0.25
0.05 M
S
C
A-B
0.05
S
MAX0.02
S
Solder Plating
+ 0.09
0.25 – 0.03
+ 0.09
0.14 – 0.03
S
TERMINAL SECTION
PACKAGE STRUCTURE
Note:Cutting burr of lead are 0.05mm MAX.
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.02g
SONY CODE
UQFN-20P-01
LEAD PLATING SPECIFICATIONS
ITEM
LEAD MATERIAL
-5-
SPEC.
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18µm
Sony Corporation