SS6341 High Performance, Triple-Output, Auto-Tracking Combo Controller n n FEATURES l Provides Three Accurately Regulated Output Voltages l Optimized Voltage-Mode PWM Control l Dual N-Channel MOSFET Synchronous Drivers l Fast Transient Response l Adjustable Over-Current Protection Using External MOSFET RDS(ON) - No External Current Sense Resistors Required. l Programmable Soft Start Function l 200KHz Free-Running Oscillator l Robust Output Auto-Tracking Characteristics l Sink and Source Capabilities with External Circuit n APPLICATIONS l Advanced PC motherboards l Information PCs l Servers and Workstations l Internet Appliances l LCD Monitor l PC Add-On Cards l DDR Termination GENERAL DESCRIPTION The SS6341 combines a synchronous voltage-mode PWM controller with two linear controllers, including the associated monitoring and protection functions. It is able to power CPUs, GPUs, memories, chipsets and multi-voltage applications. The PWM controller regulates the output voltage using a synchronous rectified step-down converter. The built-in N-Channel MOSFET drivers also help to simplify the design of the step-down converter. The PWM controller features over-current protection using the RDS(ON) of the external MOSFET, improving efficiency and cost, as there is no expensive current sense resistor required. Two built-in adjustable linear controllers drive external MOSFETs to form two linear regulators that regulate power for multiple system I/Os. The output voltage of both linear regulators can also be adjusted by means of an external resistor divider. Both linear regulators feature current-limiting. For system I/Os requiring current less than 500mA, the SS6340 is recommended as it saves one external MOSFET. The programmable soft-start design provides a controlled output voltage rise, which limits the current during power-on. A shutdown function is also provided, for disabling the combo controller. Rev.2.01 6/26/2003 www.SiliconStandard.com 1 of 14 SS6341 n TYPICAL APPLICATION CIRCUIT SS6341CS +12VIN VCC +5VIN 4 14 SS 2 5 1 OCSET UGATE + GND Q1 PHASE VOUT1 +3.3VIN VIN2 7 16 GATE3 VOUT3 LGATE + Q2 10 FB3 15 11 PGND + +3.3VIN FB1 13 GATE2 8 VOUT2 FB2 6 + 12 14 GND COMP1 3 SD Typical Application with Three Outputs n ORDERING INFORMATION SS6341CXXX PIN CONFIGURATION PACKING TYPE TR: TAPE & REEL TB: TUBE SO-16 TOP VIEW PACKAGING TYPE S: SMALL OUTLINE PHASE 1 16 LGATE UGATE 2 15 PGND SD 3 VCC 4 SS 5 Example: SS6341CSTR à in SO-16 Package shipped in Tape & Reel Packing FB2 6 VIN2 7 GATE2 8 Rev.2.01 6/26/2003 www.SiliconStandard.com 14 OCSET 13 FB1 12 COMP1 11 FB3 10 GATE3 9 GND 2 of 14 SS6341 n ABSOLUTE MAXIMUM RATINGS Supply Voltage (VCC) ..................................................................................................................15V UGATE ...................................................................................................... GND - 0.3V to VCC + 0.3V LGATE....................................................................................................... GND - 0.3V to VCC + 0.3V Input Output and I/O Voltage................................................................................... GND - 0.3V to 7V Recommended Operating Conditions Ambient Temperature Range ..........................................................................................0° C to 85°C Maximum Operating Junction Temperature .............................................................................. 100°C Supply Voltage, VCC .......................................................................................................... 15V±10% Thermal Information Thermal Resistance θJA (°C/W) SOIC Package ........................................................................................................... 100°C/W Maximum Junction Temperature (Plastic Package) .................................................................. 150°C Maximum Storage Temperature Range...................................................................... -65°C to 150°C Maximum Lead Temperature (Soldering 10s) ........................................................................... 300°C n TEST CIRCUIT Refer to the APPLICATION CIRCUIT on page 14. n ELECTRICAL CHARACTERISTICS PARAMETER (Vcc=12V, T J=25°C, Unless otherwise specified) TEST CONDITIONS SYMBOL MIN. TYP. MAX. UNIT VCC SUPPLY CURRENT Supply Current UGATE, LGATE, GATE2 and GATE3 open ICC 1.8 5 mA POWER ON RESET Rising VCC Threshold VOCSET=4.5V VCCTHR 8.6 9.5 10.4 V Falling VCC Threshold VOCSET=4.5V VCCTHF 8.2 9.2 10.2 V Rising VIN2 Under-Voltage Threshold VIN2THR 2.5 2.6 2.7 V VIN2 Under-Voltage Hysteresis VIN2HYS 130 mV Rising VOCSET1 Threshold VOCSETH 1.3 V Rev.2.01 6/26/2003 www.SiliconStandard.com 3 of 14 SS6341 n ELECTRICAL CHARACTERISTICS PARAMETER (Continued) TEST CONDITIONS SYMBOL MIN. TYP. MAX. UNIT OSCILLATOR and REFERENCE Free Running Frequency F 170 200 230 KHz FB1 Reference Voltage VREF1 1.287 1.300 1.313 V FB2 Reference Voltage VREF2 1.245 1.270 1.295 V FB3 Reference Voltage VREF3 1.250 1.275 1.300 V LINEAR CONTROLLER Regulation 0 < IGATE2/3 < 10mA Under-Voltage Level FB2/3 falling -2.5 FB2/3UV 70 +2.5 % 80 % PWM CONTROLLER ERROR AMPLIFIER DC GAIN Gain Bandwidth Product Slew Rate COMP1=10pF 76 dB GBWP 11 MHz SR 6 V/µS PWM CONTROLLER GATE DRIVER Upper Drive Source VCC=12V, VUGATE=11V RUGH 5.2 6.5 Ω Upper Drive Sink VCC=12V, VUGATE =1V RUGL 3.3 5 Ω Lower Drive Source VCC=12V, VLGATE=11V RLGH 4.1 6 Ω Lower Drive Sink VCC=12V, VLGATE=1V RLGL 3 5 Ω PROTECTION Soft-Start Current ISS Chip Shutdown Soft Start Threshold Rev.2.01 6/26/2003 µA 11 1.0 www.SiliconStandard.com V 4 of 14 SS6341 n PIN DESCRIPTIONS Pin 1: PHASE: This pin can drive either a Darlington NPN transistor or an N-channel MOSFET. Over-current detection pin. Connect to the source high-side of the N-MOSFET. external This pin detects the voltage drop across the Pin 9: GND: high-side N-MOSFET RDS(ON) for over-current protection. Pin 2: Pin 10: GATE3: Linear Controller output drive pin. This pin can drive either a Darlington NPN transistor or an N-channel MOSFET. Pin 11: FB3 Negative feedback pin for the linear controller error amplifier. Connect this pin to a resistor divider to set the linear controller output voltage. Pin 12: COMP1 External UGATE: External high-side N-MOSFET gate drive pin. Connect to the gate of the external high-side N-MOSFET. Pin 3: SD: To shut down the system, active high or floating. If connecting a resistor to ground, keep the resistor less than 4.7KΩ. Pin 4: Pin 5: VCC: SS: Connect to the error amplifier output and PWM comparator. An RC the MOSFETs controlled by the IC. network is connected to FB1 to Recommended supply voltage is compensate the voltage control 12V. feedback loop of the converter. Soft-start pin. Connect a capacitor this pin to ground. This Pin 13: FB1 used drain Connect this pin to a resistor divider of the N-MOSFET. external ROCSET, high-side an internal 200µA current source (IOCSET), and voltage. Rev.2.01 6/26/2003 the resistor ROCSET from this pin to the to set the linear regulator output GATE2: compensate Pin 14: OCSET: Current limit sense pin. Connect a IC. Pin 8: to voltage-control feedback loop. the soft-start interval of the converter. Pulling this pin low will shut down the The error amplifier inverting input pin. The FB1 pin and COMP1 pin are 10µA (typically) current source, sets Pin 7: VIN2: pin. provides the gate bias charge for all capacitor, along with an internal FB2: compensation The chip power supply pin. It also from Pin 6: Signal GND for IC. All voltage levels are measured with respect to this pin. the upper N-MOSFET on-resistance Connect this pin to a suitable 3.3V source. Additionally, this pin is used to monitor the 3.3V supply. If the voltage drops below 2.6V (typically) following a start-up cycle, the chip shuts down. A new soft-start cycle is initiated upon the return of the 3.3V supply above the under-voltage threshold. Linear Controller output drive pin. (RDS(ON)) set the over-current trip point according to the following equation: IPEAK = Pin 15: PGND: IOCSET × ROCSET RDS(ON) Driver power GND pin. Connect to a low impedance ground plane close to the lower N-MOSFET source. Pin 16: LGATE: www.SiliconStandard.com Lower N-MOSFET gate drive pin. 5 of 14 SS6341 n TYPICAL PERFORMANCE CHARACTERISTICS UGATE UGATE LGATE LGATE FIG.1 The gate drive waveforms CH1 2V/div CH2 1V/div FAULT SS SS VOUT1=3.15V Over Load Applied VOUT1=2.20V 10A/div VOUT1=1.30V FIG. 2 Soft Start Initiates PWM Output Rev.2.01 6/26/2003 Inductor Current FIG. 3 Over-Current Operation on Inductor www.SiliconStandard.com 6 of 14 SS6341 n TYPICAL PERFORMANCE CHARACTERISTICS (Continued) VOUT1 0 to 400mA Load Step 2.0VDC 5A to 12A Load Step VOUT2 FIG. 4 Transient Response of Linear Regulator FIG. 5 Transient Response of PWM Output 210 VOUT3 ( 2mV/div) OCSET Current (µA) 205 1A to 2A Load Step 200 195 190 185 180 -20 FIG. 6 Transient Response of Linear Controller 20 40 60 80 100 FIG.7 OCSET Current vs.Temperature (°C) 0.3 9.55 9.50 NO LOAD 0.2 VOUT1 Drift (mV) SS Charge Current (uA) 0 9.45 9.40 9.35 0.1 0.0 -0.1 9.30 9.25 -20 -10 0 10 20 30 40 50 60 70 80 90 FIG.8 SS Current vs. Temperature (°C) Rev.2.01 6/26/2003 100 -0.2 4.0 4.5 5.0 5.5 6.0 6.5 7.0 FIG.9 VOUT1 Drift vs. VIN (V) ww w.Sil ic onStandard .com 7 of 14 SS6341 n BLOCK DIAGRAM VCC VIN2 SS FB3 + + + GATE3 LUV + OCSET 1.3V 9.5V 200uA + 0.3V + 2.6V + GATE2 SS 1.26V POR FB2 INHIBIT OC1 + PHASE VCC COUNT 3 LUV 3.6V OC1 UGATE S Q R R S + + Q POR GATE CONTROL 5V R S 10uA 0.2V PWM COMP Q VCC R + SS SLOW DISCHARGE 4V 5V 1.3V 70K GND ERROR AMP SD FB1 LGATE PGND + FAST DISCHARGE 20uA n 200KHz OSCILLATOR SS COMP1 APPLICATIONS INFORMATION The SS6341 is designed for applications with multiple approximate 1V. Then an internal 10µA current source voltage demand. This IC has one PWM controller and two charges an external capacitor (CSS) on the SS pin to 4V. linear controllers. The PWM controller is designed to As the SS pin voltage slews from 1V to 4V, the PWM regulate the voltage (VOUT1) by driving 2 MOSFETs error amplifier reference input (non-inverting terminal) (through UGATE and L GATE ) in a synchronous rectified buck and output (COMP1 pin) are clamped to a level converter configuration. The regulated voltage level is proportional to the SS pin voltage. As the SS pin voltage decided by a resistor divider network. slews from 1V to 4V, the output clamp generates PHASE pulses of increasing width that charge the output The Power-On Reset (POR) function continually capacitors. Additionally both linear regulators’ reference monitors the +12V input supply voltage at VCC pin, the inputs are clamped to a voltage proportional to the SS pin 5V input voltage at OCSET pin, and the 3.3V input at voltage. This method provides a controlled smooth rise in VIN2 pin. The POR function initiates soft-start operation output voltage. after all three input supply voltage exceed their POR Fig. 2 shows the soft-start sequence for a typical thresholds. application. The internal oscillator’s triangular waveform Soft-Start is compared to the clamped error amplifier output voltage. The POR function initiates the soft-start sequence. As the SS pin voltage increases, the pulse width on the Initially, the voltage on the SS pin rapidly increases to PHASE pin increases. The period of increasing pulse Rev.2.01 6/26/2003 www.SiliconStandard.com 8 of 14 SS6341 width continues until the output reaches sufficient voltage Shutdown to transfer control to the input reference clamp. Compatible with TTL logic levels, holding the SD (pin3) pin low will activate the controller. If connecting a resistor Each linear output (VOUT2 and VOUT3) initially follows a to ground, make sure the resistor is less than 4.7KΩ for ramp. When each output reaches sufficient voltage, the normal operation. input reference clamp slows the rate of output voltage rise. Layout Considerations Any inductance in the switched current path generates a Over-Current Protection large voltage spike during the switching interval. The All outputs are protected against excessive over-current. voltage spikes can degrade efficiency, radiate noise into The PWM controller uses the upper MOSFET’s the circuit, and lead to device over-voltage stress. Careful on-resistance, RDS(ON) to monitor the current for component protection against shorted outputs. Both the linear components using short, wide metal traces minimizes regulator and controller monitor FB2 and FB3 for these voltage spikes. under-voltage to protect against excessive current. When the voltage across Q1 (ID x RDS(ON)) exceeds the level (200µA x ROCSET), this signal inhibits all outputs, discharges the soft-start capacitor (Css) with 10µA current sink, and increments the counter. Css recharges and initiates a soft-start cycle again until the counter selection and tight layout of critical 1) A ground plane should be used. Locate the input capacitors (CIN) close to the power switches. Minimize the loop formed by CIN, the upper MOSFET (Q1) and the lower MOSFET (Q2) as much as possible. Connections should be as wide and as short as possible to minimize loop inductance. increments to 3. This sets the fault latch to disable all 2) The connection between Q1, Q2 and output inductor outputs. Fig. 3 illustrates the over-current protection for should be as wide and as short as practical, as this an over load on OUT1. connection has fast voltage transitions and can easily induce EMI. Should excessive current cause FB2 or FB3 to fall below the linear under-voltage threshold, the LUV signal sets the over-current latch if Css is fully charged. Cycling the bias input power off then on resets the counter and the fault latch. 3) The output capacitor (COUT) should be located as close to the load as possible. Minimizing the transient load magnitude for high slew rate requires low inductance and resistance in the circuit board. 4) The SS6341 is best placed over a quiet ground The over-current function for the PWM controller will trip plane area. The GND pin should be connected to the at a peak inductor current (IPEAK) determined by: groundside of the output capacitors. Under no IPEAK IOCSET × ROCSET = RDS(ON) circumstances should GND be returned to a ground inside the CIN, Q1, and Q2 loop. The GND and PGND pins should be shorted right at the IC. This helps to minimize internal ground disturbances in the The OC trip point varies with the MOSFET’s temperature. To avoid over-current tripping in the normal operating load range, determine the ROCSET resistor from the IC and prevents differences in ground potential from disrupting the internal circuit operation. 5) The wiring traces from the control IC to the MOSFET equation above with: gate and source should be sized to carry a current of 1. The maximum RDS(ON) at the highest junction. 1A. Locate COUT2 close to the SS6341. 2. The minimum IOCSET from the specification table. 3. Ensure IPEAK > IOUT(MAX) + (inductor ripple current) /2. 6) The Vcc pin should be decoupled directly to GND by a 1µF ceramic capacitor; trace lengths should be as short as possible. Rev.2.01 6/26/2003 www.SiliconStandard.com 9 of 14 SS6341 A multi-layer printed circuit board is recommended. The ESR (equivalent series resistance) and ESL Figure 10 shows the connections of the critical (equivalent series inductance) parameters determine the components in the converter. The CIN and COUT could buck capacitor values, rather than actual capacitance. each represent numerous physical capacitors. Dedicate For a given transient load magnitude, the output voltage one solid layer for a ground plane and make all critical transient change due to the output capacitor can be found component ground connections with vias to this layer. from the following equation: ∆VOUT = ESR × ∆IOUT + ESL × PWM Output Capacitors The load transient for the microprocessor core requires where high quality capacitors to supply the high slew rate (di/dt) ∆IOUT ∆T ∆IOUT is the transient load current step. current demand. + +12V VCC +3.3VIN GND +5VIN VIN2 OCSET GATE3 UGATE + Q3 + CIN Q1 VOUT3 PHASE + LOUT COUT3 VOUT + LGATE COUT Q2 Q4 GATE2 PGND SS VOUT2 Css + COUT2 Power Plane Layer Circuit Plane Layer Via Connection to Ground Plane Fig. 10 Printed circuit board power planes and islands Rev.2.01 6/26/2003 www.SiliconStandard.com 10 of 14 SS6341 After the initial transient, the ESL dependent term drops off. Because of the strong relationship between output capacitor ESR and output load transient, the output resistive power loss Input Capacitor Selection capacitor is usually chosen for ESR, not for capacitance Most of the input supply current is supplied by the input value. A capacitor with suitable ESR will usually have a bypass capacitor, and the resulting RMS current flow in larger capacitance value than is needed for energy the input capacitor will heat it up. Use a mix of input bulk storage. capacitors to control the voltage overshoot across the A common way to lower ESR and raise ripple current capability is to parallel several capacitors. In most case, multiple electrolytic capacitors of small case size are better than a single large case capacitor. Output Inductor Selection upper MOSFET. The ceramic capacitance for the high frequency decoupling should be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedance. The buck capacitors to supply the RMS current are approximate equal to: 1 VIN × D IRMS = (1− D) × D × I OUT + × 12 f × L The inductor value and type should be chosen based on output slew rate requirement, output ripple requirement and expected peak current, and is primarily controlled by where D= the required current response time. The SS6341 will provide either 0% or 85% duty cycle in response to a load transient. The response time to a transient is different for the application of load and remove of load. tRISE = L × ∆IOUT L × ∆IOUT , tFALL = VIN − VOUT VOUT where 2 2 ∆IOUT is transient load current step. In a typical 5V input, 2V output application, a 3µH inductor has a 1A/µS rise time, resulting in a 5µS delay in responding to a 5A load current step. To optimize performance, different combinations of input and output voltage and expected loads may require different inductor values. A smaller value of inductor will improve the transient response at the expense of increased output ripple voltage and inductor core saturation rating. VOUT VIN The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage. PWM MOSFET Selection In high current PWM application, the MOSFET power dissipation, package type and heatsink are the dominant design factors. The conduction loss is the only component of power dissipation for the lower MOSFET, since it turns on into near zero voltage. The upper MOSFET has conduction loss and switching loss. The gate charge losses are proportional to the switching frequency and are dissipated by the SS6341. However, the gate charge increases the switching interval, tSW , which increase the upper MOSFET switching losses. Ensure that both MOSFETs are within Peak current in the inductor will be equal to the maximum their maximum junction temperature at high ambient output load current plus half of inductor ripple current. The temperature ripple current is approximately equal to: according to package thermal resistance specifications. IRIPPLE = (VIN − VOUT) × VOUT f × L × VIN by calculating the temperature rise IOUT × VIN × tSW × f 2 × RDS(ON) × (1 − D) PUPPER = IOUT 2 × RDS(ON) × D + PLOWER = IOUT 2 where f = 200KHz oscillator frequency. The inductor must be able to withstand peak current The equations above do not model the power loss from the without saturation, and the copper resistance in the reverse recovery of the lower MOSFET’s body diode. winding should be kept as low as possible to minimize The RDS(ON) is different for the two previous equations Rev.2.01 6/26/2003 www.SiliconStandard.com 11 of 14 SS6341 even if the same device type is used for both. This is Select a package and heatsink that maintains junction because the gate drive applied to the upper MOSFET is temperature below the maximum rating while operating at different than the lower MOSFET. Logic level MOSFETs the highest expected ambient temperature. should be selected based on on-resistance considerations. RDS(ON) should be chosen based on input Linear Output Capacitor and output voltage, allowable power dissipation and The output capacitors for the linear controller provide maximum required output current. Power dissipation dynamic load current. The linear controller uses dominant should be calculated based primarily on required pole compensation integrated in the error amplifier and is efficiency or allowable thermal dissipation. insensitive to output capacitor selection. COUT2 and COUT3 A Schottky diode is used as a clamp to prevent the should be selected for transient load regulation. parasitic MOSFET body diode from conducting during the dead time between the turn off of the lower MOSFET Notes and the turn on of the upper MOSFET. The diode’s rated VOUT1 - The PWM output reverse breakdown voltage must be greater than twice VOUT2 - The output of the linear controller managed by FB2 and GATE2 the maximum input voltage. VOUT3 - The output of the linear controller managed by Linear Controller MOSFET Selection The power dissipated in a linear regulator is : PLINEAR = IOUT × (VIN2 − VOUT) Rev.2.01 6/26/2003 FB3 and GATE3 These refer to the TYPICAL APPLICATION CIRCUITS on pages 3 and 14. www.SiliconStandard.com 12 of 14 SS6341 n APPLICATION CIRCUIT 1000pF K SS6341CS 10 +12VIN 1µH 2K VCC 4 14 OCSET + 1000µF*2 SS 1µF 2 5 0.1µF 1 +5VIN 0.1µF UGATE PHASE GND 5V OUT +5.0VIN VIN2 7 7µH 16 GATE3 3.3V OUT LGATE + 1000µF *5 10 FB3 15 11 PGND 3.9K + 2.4K 24K +5.0VIN FB1 13 GATE2 8.2K 8 2.5V OUT 33pF 91K COMP1 1000pF FB2 6 + 2.4K 12 2.4K 14 GND 3 SD Typical Application Circuit for Multiple Outputs Rev.2.01 6/26/2003 www.SiliconStandard.com 13 of 14 SS6341 n PACKAGE DIMENSIONS l 16 LEAD PLASTIC SO (300 mil) (unit: mm) D E H MIN MAX A 2.35 2.65 A1 0.10 0.30 B 0.33 0.51 C 0.23 0.32 D 10.10 10.50 E 7.40 7.60 e e A1 A B SYMBOL c L 1.27(TYP) H 10.00 10.65 L 0.40 1.27 Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. Rev.2.01 6/26/2003 www.SiliconStandard.com 14 of 14