SSEPAA5-02N Low Capacitance ESD Protection Array For High Speed Data Interfaces Features z z ESD Protect for 2 high-speed I/O channels Provide ESD protection for each channel to immunity requirements of IEC 61000-4-2, Level 4 (± 15kV air, ±8kV contact discharge). IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) IEC 61000-4-5 (Lightning) 12A (8/20μs) 5V operating voltage z Low capacitance : 2pF typical z Fast turn-on and Low clamping voltage z Array of surge rated diodes with internal equivalent TVS diode z Small package saves board space z Solid-state silicon-avalanche and active circuit triggering technology Circuit Diagram z Applications USB2.0 Power and Data lines protection Notebook and PC Computers z Monitors and Flat Panel Displays z IEEE 1394 Firewire Ports z Video Graphics Cards z SIM ports 4 2 3 1 z z Pin Configuration Description SSEPAA5-02N is a high performance design which includes surge rated diode arrays to protect high speed data interfaces. The SSEPAA5-02N has been specifically designed to protect sensitive components, which are connected to data and transmission lines, from over-voltage caused by Electrostatic Discharging (ESD), Electrical Fast Transients (EFT), and Lightning. SSEPAA5-02N is a unique design which includes surge rated, low capacitance steering diodes and a unique design of clamping cell which is an equivalent TVS diode in a single package. During transient conditions, the steering diodes direct the transient to either the power supply line or to the ground line. The internal unique design of clamping cell prevents over-voltage on the power line, protecting any downstream components. SSEPAA5-02N may be used to meet the ESD 11/08/2007 Rev.1.00 VDD I/O 2 4 3 1 2 GND I/O 1 JEDEC SOT143-4L (Top View) www.SiliconStandard.com 1 SSEPAA5-02N SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETER PARAMETER RATING UNITS Peak Pulse Current (tp =8/20μs) IPP 13 A Operating Supply Voltage (VDD-GND) VDC 6 V ESD per IEC 61000-4-2 (Air) VESD 24 kV ESD per IEC 61000-4-2 (Contact) Lead Soldering Temperature 16 TSOL 260 (10 sec.) o C Operating Temperature TOP -55 to +125 o Storage Temperature TSTO -55 to +150 o DC Voltage at any I/O pin VIO (GND – 0.5) to (VDD + 0.5) C C V ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN TYP o MAX UNITS Reverse Stand-Off Voltage VRWM Pin 4 to pin 1, T=25 C 5 V Reverse Leakage Current ILeak VRWM = 5V, T=25 oC, Pin 4 to pin 1 5 μA Channel Leakage Current ICH_Leak VPin 4 = 5V, VPin 1 = 0V, T=25 oC 1 μA Reverse Breakdown Voltage VBV IBV = 1mA, T=25 oC Pin 4 to Pin 1 Forward Voltage VF IF = 15mA, T=25 oC Pin1 to Pin 4 Clamping Voltage VCL IPP=5A, tp=8/20μs, T=25 oC Any Channel pin to Ground ESD Holding Voltage Vhold IEC 61000-4-2, +6kV, T=25 oC, Contact mode (Any Channel pin to Ground). 13.5 Channel Input Capacitance CIN Vpin5 = 5V, Vpin2 = 0V, VIN = 2.5V, f = 1MHz, T=25 oC, Any Channel pin to Ground 2 3 pF Channel to Channel Input Capacitance CCROSS Vpin5 = 5V, Vpin2 = 0V, VIN = 2.5V, f = 1MHz, T=25 oC , Between Channel pins 0.08 0.15 pF Variation of Channel Input Capacitance △CIN Vpin5 = 5V, Vpin2 = 0V, VIN = 2.5V, f = 1MHz, T=25 oC , Channel_x pin to Ground - Channel_y pin to Ground 0.03 0.06 pF 11/08/2007 Rev.1.00 www.SiliconStandard.com V 6.1 0.7 1 V 8 9 V V 2 SSEPAA5-02N Typical Characteristics Clamping Voltage vs. Peak Pulse Current Power Derating Curve 110 90 Clamping Voltage (V) % of Rated Power or IPP 100 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 150 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 5 6 3.5 3.5 Input Capacitance (pF) Forward Voltage (V) 4.0 3.0 2.5 2.0 Waveform Parameters: tr=8μs td=20μs I/O pin to GND pin 0.5 0.0 4 5 6 7 8 9 10 11 9 10 11 12 13 12 3.0 2.5 2.0 1.5 1.0 VDD = 5V, GND = 0V, f = 1MHz, T=25 oC, 0.5 0.0 13 0 1 Peak pulse Current (A) 2 3 4 5 Input Voltage (V) Insertion Loss S21 Typical Variation of CIN vs. Temp 3.0 8 Typical Variation of CIN vs. VIN Forward Voltage vs. Forward Current 4.0 1.0 7 Peak pulse Current (A) Ambient Temperature, TA (oC) 1.5 Waveform Parameters: tr=8μs td=20μs I/O pin to GND pin 15 5 S21 (dB) Input Capacitance (pF) 10 2.5 2.0 -5 1.5 -10 VDD = 5V, GND = 0V, VIN = 2.5V, f = 1MHz, -15 1.0 20 Transmission Line Pulsing (TLP) Current (A) 0 40 60 80 Temperature (oC) 100 120 1e+6 START 0.3MHz 1e+7 Frequency (Hz) 1e+8 1e+9 STOP 1000MHz Transmission Line Pulsing (TLP) Measurement 20 18 16 V_pulse 14 Pulse from a transmission line 12 100ns 10 TLP_I + TLP_V 8 DUT - 6 4 I/O to GND 2 0 0 2 4 6 8 10 12 14 Transmission Line Pulsing (TLP) Voltage (V) 11/08/2007 Rev.1.00 www.SiliconStandard.com 3 SSEPAA5-02N Applications Information A. Design Considerations The ESD protection scheme for system I/O connector is shown in the Fig. 1. In Fig. 1, the diodes D1 and D2 are general used to protect data line from ESD stress pulse. If the power-rail ESD clamping circuit is not placed between VDD and GND rails, the positive pulse ESD current (IESD1) will pass through the ESD current path1. Thus, the ESD clamping voltage VCL of data line can be described as follow: VCL = Fwd voltage drop of D1 + supply voltage of VDD rail + L1 × d(IESD1)/dt + L2 × d(IESD1)/dt Where L1 is the parasitic inductance of data line, and L2 is the parasitic inductance of VDD rail. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30A in 1ns. Here d(IESD1)/dt can be approximated by ΔIESD1/Δt, or 30/(1x10-9). So power-rail ESD clamp ing circuit just 10nH of total parasitic inductance (L1 and L2 combined) will lead to over 300V increment in VCL! Besides, the ESD pulse current which is directed into the VDD rail may potentially damage any components that are attached to that rail. Moreover, it is common for the forward voltage drop of discrete diodes to exceed the damage threshold of the protected IC. This is due to the relatively small junction area of typical discrete components. Of course, the discrete diode is also possible to be destroyed due to its power dissipation capability is exceeded. The SSEPAA5-02N has an integrated power-rail ESD clamped circuit between VDD and GND rails. It can successfully overcome previous disadvantages. During an ESD event, the positive ESD pulse current (IESD2) will be directed through the integrated power-rail ESD clamped circuit to GND rail (ESD current path2). The clamping voltage VCL on the data line is small and protected IC will not be damaged because power-rail ESD clamped circuit offer a low impedance path to discharge ESD pulse current. SSEPAA5-02N L2 I ESD2 VDD rail I ESD1 D1 L1 + Vp data line _ VESD D2 + Protected IC V CL _ GND rail ESD current path 1 (I ESD1) ESD current path 2 (I ESD2) Fig. 1 11/08/2007 Rev.1.00 Application of positive ESD pulse between data line and GND rail. www.SiliconStandard.com 4 SSEPAA5-02N B. Device Connection The SSEPAA5-02N is designed to protect two data lines and power rails from transient over-voltage (such as ESD stress pulse). The device connection of SSEPAA5-02N is shown in the Fig. 2. In Fig. 2, the two protected data lines are connected to the ESD protection pins (pin2 and pin3) of SSEPAA5-02N. The ground pin (pin1) of SSEPAA5-02N is a negative reference pin. This pin should be directly connected to the GND rail of PCB (Printed Circuit Board). To get minimum parasitic inductance, the path length should keep as short as possible. In addition, the power pin (pin 4) of SSEPAA5-02N is a positive reference pin. This pin should directly connect to the VDD rail of PCB. When pin 4 of SSEPAA5-02N is connected to the VDD rail, the leakage current of ESD protection pin of SSEPAA5-02N becomes very small. Because the pin 4 of SSEPAA5-02N is directly connected to VDD rail, the VDD rail also can be protected by the power-rail ESD clamped circuit (not shown) of SSEPAA5-02N. SSEPAA5-02N can provide protection for 2 I/O signal lines simultaneously. If the number of I/O signal lines is less than 2, the unused I/O pins can be simply left as NC pins. In some cases, systems are not allowed to be reset or restart after the ESD stress directly applying at the I/O-port connector. Under this situation, in order to enhance the sustainable ESD Level, a 0.1μF chip capacitor can be added between the VDD and GND rails. The place of this chip capacitor should be as close as possible to the SSEPAA5-02N. VDD rail 1 2 To I/O-port Connector 4 *Optional 0.1μF Chip Cap. 3 I/O 1 I/O 1 data line I/O 2 Fig. 2 11/08/2007 Rev.1.00 SSEPAA5-02N GND rail data line I/O 2 To Protected IC Data lines and power rails connection of SSEPAA5-02N. www.SiliconStandard.com 5 SSEPAA5-02N C. Applications of SSEPAA5-02N. When ESD voltage pulse appears on the data line, the ESD pulse current will be conducted by SSEPAA5-02N away from the USB controller chip. In addition, the ESD pulse current also can be conducted by SSEPAA5-02N away from the USB controller chip when the ESD voltage pulse appears on the voltage bus (VBUS) of USB port. Therefore, the data lines (D+/D-) and voltage bus (VBUS) of two USB ports are complementally protected with an SSEPAA5-02N. 1. Universal Serial Bus (USB) ESD Protection The SSEPAA5-02N can be used to protect the USB port on the monitors, computers, peripherals or portable systems. The ESD protection scheme for single USB ports is shown in Fig. 3. In the Fig.3, the voltage bus (VBUS) of USB port is connected to the power pin (pin 4) of SSEPAA5-02N. Each data line (D+/D-) of USB port is connected to the ESD protection pin (pin2/pin3) V BUS USB Controller 2 CT SSEPAA5-02N 1 4 3 CT V BUS D+ RT D_ USB Port RT GND GND Fig. 3 11/08/2007 Rev.1.00 ESD Protection scheme for single USB ports by using SSEPAA5-02N. www.SiliconStandard.com 6 SSEPAA5-02N 2. Audio Interface ESD Protection For the audio interface, the Right/Left channels should be protected from the ESD stress. The SSEPAA5-02N can be used for the audio interface ESD protection. The ESD protection scheme for audio interface is shown in the Fig. 4. In the Fig. 4, the Right and Left channels of audio connector are connected to ESD protection pins (such as pin 2 and pin 3) of SSEPAA5-02N. For the power pin (pin 4) of Audio Chip GND 2 SSEPAA5-02N 1 SSEPAA5-02N, it should directly connect to the VDD power supply. As well, for the ground pin (pin 1) of SSEPA5-02N, it should directly connect to the Ground plate. When ESD voltage pulse appears on the Right/Left channel of audio connector, the ESD pulse current will be discharged by SSEPAA5-02N. Therefore, the Right/Left channels of audio chip are complementally protected with an SSEPAA5-02N. 4 3 VDD Audio Connector Right Channel Left Channel Fig. 4 11/08/2007 Rev.1.00 ESD Protection scheme for audio interface by using SSEPAA5-02N. www.SiliconStandard.com 7 SSEPAA5-02N Mechanical Details SOT143-4L PACKAGE DIAGRAMS PACKAGE DIMENSIONS TOP VIEW SIDE VIEW END VIEW 11/08/2007 Rev.1.00 www.SiliconStandard.com 8 SSEPAA5-02N LAND LAYOUT A A Dimensions F C E D C1 B A1 A Notes: This LAND LAYOUT is for reference purposes only. Please consult your manufacturing partners to ensure your company’s PCB design guidelines are met. Index Millimeter Inches A 1.00 0.039 A1 1.40 0.055 B 1.40 0.055 C 1.92 0.076 C1 1.72 0.068 D 2.20 0.087 E 0.80 0.031 F 3.60 0.141 MARKING CODE 4 3 Part Number Marking Code 102X SSEPAA5-02N 102XY 1 2 102 = Device Code X = Date Code Y = Control Code 11/08/2007 Rev.1.00 www.SiliconStandard.com 9 SSEPAA5-02N Revision History Revision Modification Description Revision 2006/11/10 Original Release. Revision 2007/01/19 1. 2. 3. 4. Revision 2007/02/27 Update the spec. of VF, VCL, and Vhold. Revision 2007/05/15 Update the Marking Code from 102X to 102XY. Change the clamping cell symbol for easy understanding. Change the expression of CIN from @ VIN=0V to @ VIN=2.5V. Add the TLP characterization. Add the ESD holding voltage characterization under IEC 61000-4-2 +6kV contact mode at I/O channel to GND. 5. Correct typos. 6. Update the Mechanical Details. Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 11/08/2007 Rev.1.00 www.SiliconStandard.com 10