SSM20G45EGH/J N-channel Insulated-Gate Bipolar Transistor PRODUCT SUMMARY V CES 450V V CE(sat) 5V typ. I CP 130A DESCRIPTION The SSM20G45E acheives fast switching performance with low gate charge without a complex drive circuit. It is suitable for use in short-duration, high-current strobe applications, such as still-camera flash. Pb-free; RoHS-compliant TO-251 (IPAK) and TO-252 (DPAK) G G D S D S TO-251 (suffix J) TO-252 (suffix H) The SSM20G45EGH is in a TO-252 package, which is widely used for commercial and industrial surface-mount applications. The through-hole version, the SSM20G45EGJ in TO-251, is available for vertical mounting, where a small footprint is required on the board, and/or an external heatsink is to be attached. These devices are manufactured with an advanced process, providing improved on-resistance and switching performance. The gate has internal ESD protection. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Units VCES Collector-emitter voltage 450 V VGE Gate-emitter voltage ±6 V V GEP Pulsed gate-emitter voltage ±8 V ICP Pulsed collector current1 130 A PD Total power dissipation, TC = 25°C 20 W TSTG Storage temperature range -55 to 150 °C TJ Operating junction temperature range -55 to 150 °C THERMAL CHARACTERISTICS Symbol Parameter RΘ JC Maximum thermal resistance, junction-case Value Units 6 °C/W Notes: 1.Pulse width must be limited to avoid exceeding the safe operating area. 2.Pulse width <300us, duty cycle <2%. 5/16/2006 Rev.3.01 www.SiliconStandard.com 1 of 7 SSM20G45EGH/J ELECTRICAL CHARACTERISTICS Parameter Symbol Tj = 25°C (unless otherwise specified) Min. Typ. Max. Units - - 10 uA - - 10 uA - 5 8 V Gate-emitter leakage current Test Conditions VGE=6V, VCE=0V ICES Collector-emitter leakage current VCE=450V, VGE=0V VCE(sate Collector-emitter saturation voltage VGE=4.5V, ICP=130A (Pulsed) VGE(th) Gate threshold voltage VCE=VGE, IC=250uA - - 1.2 V Qg Total gate charge IC=40A - 51 - nC Qge Gate-emitter charge VCE=300V - 2 - nC Qgc Gate-collector charge VGE=5V - 5.4 - nC td(on) Turn-on delay time VCC=200V - 5.5 - ns tr Rise time IC=40A - 72 - ns td(off) Turn-off delay time RG=25Ω - 640 - ns tf Fall fime VGE=5V - 2.6 - us Cies Input capacitance VGE=0V - 2095 - pF Coes Output capacitance VCE=25V - 145 - pF Cres Reverse transfer capacitance f=1.0MHz - 35 - pF IGES 5/16/2006 Rev.3.01 www.SiliconStandard.com 2 of 7 SSM20G45EGH/J 120 160 T C =150 o C o T C =25 C V G =5.0V V G =5.0V IC , Collector Current (A) 120 IC , Collector Current (A) V G =4.5V V G =4.0V 80 V G =3.0V V G =2.0V 40 V G =4.5V 80 V G =4.0V V G =3.0V 40 V G =2.0V V G =1.0V V G =1.0V 0 0 0 2 4 6 8 10 12 0 2 Fig 1. Typical Output Characteristics 6 8 10 12 Fig 2. Typical Output Characteristics 12 160 V CE =8V T C =25 o C V GE = 4.5 V T C =70 o C 10 VCE(sat) , Saturation Voltage (V) T C =100 o C 120 IC , Collector Current (A) 4 V CE , Collector-Emitter Voltage (V) V CE , Collector Emitter Voltage (V) T C =150 o C 80 40 I C = 130A 8 I C = 100A 6 I C = 70A 4 I C = 35A 2 0 0 0 1 2 3 4 5 6 0 20 80 100 120 140 160 T C , Case Temperature ( C ) Fig 4. Collector- Emitter Saturation Voltage Gate-Emitter Voltage 5/16/2006 Rev.3.01 60 o V GE , Gate- Emitter Voltage (V) Fig 3. Collector Current vs. 40 www.SiliconStandard.com vs. Case Temperature 3 of 7 SSM20G45EGH/J 160 T C = 25 o C V G =4.5V ICP , Peak Collector Current (A) VGE(th) Gate Threshold Voltage (V) 1.5 1 0.5 0 120 80 40 0 -50 0 50 100 150 0 2 4 6 8 o T C , Case Temperature ( C ) V GE , Gate-Emitter Voltage (V) Fig 5. Gate-Emitter Cut-Off Voltage Fig 6. Safe Operating Area vs. Case Temperature f=1.0MHz 10000 8 I CP =40A V CE =300V 1000 Coes 100 Cres VGE , Gate-Emitter Voltage (V) Capacitance (pF) Cies 6 4 2 10 1 8 15 22 29 0 0 15 V CE , Collector-Emitter Voltage (V) Fig 7. Collector vs. Collector-Emitter Voltage 5/16/2006 Rev.3.01 30 45 60 75 Q G , Gate Charge (nC) Fig 8. Gate Charge Waveform www.SiliconStandard.com 4 of 7 SSM20G45EGH/J VCE R 90% C C V R G G CE TO THE OSCILLOSCOPE VCC=200V 10% VGE E + 5 V V GE - td(on) tr Fig 9. Switching Time Test Circuit td(off) tf Fig 10. Switching Time Waveform V CE TO THE OSCILLOSCOPE C Flasher Vtrig G + 300V V E CM RG _ VCM GE + IGBT 1~3 mA IG VG IC Fig 11. Gate Charge Test Circuit 5/16/2006 Rev.3.01 VCM = 300V ICP = 130A CM = 160uF VG = 5V Fig 12. Application Test Circuit www.SiliconStandard.com 5 of 7 SSM20G45EGH/J PHYSICAL DIMENSIONS: TO-251 (I-PAK) D A D1 c1 E2 E1 E A1 B2 F B1 F1 c e Millimeters SYMBOLS MIN NOM MAX A 2.20 2.30 2.40 A1 0.90 1.20 1.50 B1 0.50 0.60 0.70 B2 0.60 0.72 0.90 c c1 0.45 0.50 0.60 0.45 0.50 0.55 D 6.40 6.60 6.80 D1 5.20 5.35 5.50 E 6.80 7.00 7.20 E1 5.40 5.60 5.80 E2 1.40 1.50 1.60 e -- 2.30 -- F 7.20 7.50 7.80 F1 1.50 1.60 1.80 1.All dimensions are in millimeters. 2.Dimensions do not include mold protrusions. e PHYSICAL DIMENSIONS: TO-252 (D-PAK) A E S Y M B O L c2 H D L4 A A e SEE VIEW B MIN. MAX. 1.80 2.80 c WITH PLATING BASE METAL SECTION A-A θ SEATING PLANE L1 0.00 0.13 0.40 1.00 b3 4.80 5.90 c 0.35 0.65 c2 0.40 0.89 D 5.10 6.30 E 6.00 7.00 2.30 BSC H 7.80 L 1.00 2.55 L1 2.20 3.05 L2 0.35 0.65 L3 0.50 2.03 L4 0.50 1.20 θ 0° 8° 11.05 A1 L2 L A1 b e b GAUGE PLANE TO-252-3L MILLIMETERS A L3 b3 VIEW B 5/16/2006 Rev.3.01 www.SiliconStandard.com 6 of 7 SSM20G45EGH/J PART MARKING PART NUMBER: 20G45EGH or 20G45EGJ XXXXXX DATE/LOT CODE: (YWWSSS) Y = last digit of the year WW = week SSS = lot code sequence YWWSSS PACKING: Moisture sensitivity level MSL3 TO-252: 3000 pcs in antistatic tape on a reel packed inside a moisture barrier bag (MBB). TO-251: 1000pcs in tubes packed inside a moisture barrier bag (MBB). Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 5/16/2006 Rev.3.01 www.SiliconStandard.com 7 of 7